1 /*- 2 * Copyright (c) 1998 - 2006 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/ata/ata-pci.c,v 1.121 2007/02/23 12:18:33 piso Exp $ 27 * $DragonFly: src/sys/dev/disk/nata/ata-pci.c,v 1.10 2008/03/28 11:03:44 sephe Exp $ 28 */ 29 30 #include "opt_ata.h" 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/bus_resource.h> 35 #include <sys/malloc.h> 36 #include <sys/module.h> 37 #include <sys/nata.h> 38 #include <sys/rman.h> 39 #include <sys/systm.h> 40 41 #include <bus/pci/pcireg.h> 42 #include <bus/pci/pcivar.h> 43 44 #include "ata-all.h" 45 #include "ata-pci.h" 46 #include "ata_if.h" 47 48 /* local vars */ 49 static MALLOC_DEFINE(M_ATAPCI, "ata_pci", "ATA driver PCI"); 50 51 /* misc defines */ 52 #define IOMASK 0xfffffffc 53 #define ATA_PROBE_OK -10 54 55 static const struct none_atapci { 56 uint16_t vendor; 57 uint16_t device; 58 uint16_t subvendor; 59 uint16_t subdevice; 60 } none_atapci_table[] = { 61 /* Appears on Intel PRO/1000 PM */ 62 { ATA_INTEL_ID, 0x108d, ATA_INTEL_ID, 0x0000 }, 63 { 0xffff, 0, 0, 0 } 64 }; 65 66 int 67 ata_legacy(device_t dev) 68 { 69 return (((pci_read_config(dev, PCIR_PROGIF, 1)&PCIP_STORAGE_IDE_MASTERDEV)&& 70 ((pci_read_config(dev, PCIR_PROGIF, 1) & 71 (PCIP_STORAGE_IDE_MODEPRIM | PCIP_STORAGE_IDE_MODESEC)) != 72 (PCIP_STORAGE_IDE_MODEPRIM | PCIP_STORAGE_IDE_MODESEC))) || 73 (!pci_read_config(dev, PCIR_BAR(0), 4) && 74 !pci_read_config(dev, PCIR_BAR(1), 4) && 75 !pci_read_config(dev, PCIR_BAR(2), 4) && 76 !pci_read_config(dev, PCIR_BAR(3), 4) && 77 !pci_read_config(dev, PCIR_BAR(5), 4))); 78 } 79 80 int 81 ata_pci_probe(device_t dev) 82 { 83 if (pci_get_class(dev) != PCIC_STORAGE) 84 return ENXIO; 85 86 /* if this is an AHCI chipset grab it */ 87 if (pci_get_subclass(dev) == PCIS_STORAGE_SATA) { 88 if (!ata_ahci_ident(dev)) 89 return ATA_PROBE_OK; 90 } 91 92 /* run through the vendor specific drivers */ 93 switch (pci_get_vendor(dev)) { 94 case ATA_ACARD_ID: 95 if (!ata_acard_ident(dev)) 96 return ATA_PROBE_OK; 97 break; 98 case ATA_ACER_LABS_ID: 99 if (!ata_ali_ident(dev)) 100 return ATA_PROBE_OK; 101 break; 102 case ATA_AMD_ID: 103 if (!ata_amd_ident(dev)) 104 return ATA_PROBE_OK; 105 break; 106 case ATA_ATI_ID: 107 if (!ata_ati_ident(dev)) 108 return ATA_PROBE_OK; 109 break; 110 case ATA_CYRIX_ID: 111 if (!ata_cyrix_ident(dev)) 112 return ATA_PROBE_OK; 113 break; 114 case ATA_CYPRESS_ID: 115 if (!ata_cypress_ident(dev)) 116 return ATA_PROBE_OK; 117 break; 118 case ATA_HIGHPOINT_ID: 119 if (!ata_highpoint_ident(dev)) 120 return ATA_PROBE_OK; 121 break; 122 case ATA_INTEL_ID: 123 if (!ata_intel_ident(dev)) 124 return ATA_PROBE_OK; 125 break; 126 case ATA_ITE_ID: 127 if (!ata_ite_ident(dev)) 128 return ATA_PROBE_OK; 129 break; 130 case ATA_JMICRON_ID: 131 if (!ata_jmicron_ident(dev)) 132 return ATA_PROBE_OK; 133 break; 134 case ATA_MARVELL_ID: 135 if (!ata_marvell_ident(dev)) 136 return ATA_PROBE_OK; 137 break; 138 case ATA_NATIONAL_ID: 139 if (!ata_national_ident(dev)) 140 return ATA_PROBE_OK; 141 break; 142 case ATA_NETCELL_ID: 143 if (!ata_netcell_ident(dev)) 144 return ATA_PROBE_OK; 145 break; 146 case ATA_NVIDIA_ID: 147 if (!ata_nvidia_ident(dev)) 148 return ATA_PROBE_OK; 149 break; 150 case ATA_PROMISE_ID: 151 if (!ata_promise_ident(dev)) 152 return ATA_PROBE_OK; 153 break; 154 case ATA_SERVERWORKS_ID: 155 if (!ata_serverworks_ident(dev)) 156 return ATA_PROBE_OK; 157 break; 158 case ATA_SILICON_IMAGE_ID: 159 if (!ata_sii_ident(dev)) 160 return ATA_PROBE_OK; 161 break; 162 case ATA_SIS_ID: 163 if (!ata_sis_ident(dev)) 164 return ATA_PROBE_OK; 165 break; 166 case ATA_VIA_ID: 167 if (!ata_via_ident(dev)) 168 return ATA_PROBE_OK; 169 break; 170 case ATA_CENATEK_ID: 171 if (pci_get_devid(dev) == ATA_CENATEK_ROCKET) { 172 ata_generic_ident(dev); 173 device_set_desc(dev, "Cenatek Rocket Drive controller"); 174 return ATA_PROBE_OK; 175 } 176 break; 177 case ATA_MICRON_ID: 178 if (pci_get_devid(dev) == ATA_MICRON_RZ1000 || 179 pci_get_devid(dev) == ATA_MICRON_RZ1001) { 180 ata_generic_ident(dev); 181 device_set_desc(dev, 182 "RZ 100? ATA controller !WARNING! data loss/corruption risk"); 183 return ATA_PROBE_OK; 184 } 185 break; 186 } 187 188 /* unknown chipset, try generic AHCI or DMA if it seems possible */ 189 if (pci_get_subclass(dev) == PCIS_STORAGE_IDE) { 190 uint16_t vendor, device, subvendor, subdevice; 191 const struct none_atapci *e; 192 193 vendor = pci_get_vendor(dev); 194 device = pci_get_device(dev); 195 subvendor = pci_get_subvendor(dev); 196 subdevice = pci_get_subdevice(dev); 197 for (e = none_atapci_table; e->vendor != 0xffff; ++e) { 198 if (e->vendor == vendor && e->device == device && 199 e->subvendor == subvendor && e->subdevice == subdevice) 200 return ENXIO; 201 } 202 203 if (!ata_generic_ident(dev)) 204 return ATA_PROBE_OK; 205 } 206 return ENXIO; 207 } 208 209 int 210 ata_pci_attach(device_t dev) 211 { 212 struct ata_pci_controller *ctlr = device_get_softc(dev); 213 u_int32_t cmd; 214 int unit; 215 216 /* do chipset specific setups only needed once */ 217 ctlr->legacy = ata_legacy(dev); 218 if (ctlr->legacy || pci_read_config(dev, PCIR_BAR(2), 4) & IOMASK) 219 ctlr->channels = 2; 220 else 221 ctlr->channels = 1; 222 ctlr->allocate = ata_pci_allocate; 223 ctlr->dev = dev; 224 225 /* if needed try to enable busmastering */ 226 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 227 if (!(cmd & PCIM_CMD_BUSMASTEREN)) { 228 pci_write_config(dev, PCIR_COMMAND, cmd | PCIM_CMD_BUSMASTEREN, 2); 229 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 230 } 231 232 /* if busmastering mode "stuck" use it */ 233 if ((cmd & PCIM_CMD_BUSMASTEREN) == PCIM_CMD_BUSMASTEREN) { 234 ctlr->r_type1 = SYS_RES_IOPORT; 235 ctlr->r_rid1 = ATA_BMADDR_RID; 236 ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, &ctlr->r_rid1, 237 RF_ACTIVE); 238 /* Only set a dma init function if the device actually supports it. */ 239 ctlr->dmainit = ata_pci_dmainit; 240 } 241 242 if (ctlr->chipinit(dev)) 243 return ENXIO; 244 245 /* attach all channels on this controller */ 246 for (unit = 0; unit < ctlr->channels; unit++) { 247 int freeunit = 2; 248 if ((unit == 0 || unit == 1) && ctlr->legacy) { 249 device_add_child(dev, "ata", unit); 250 continue; 251 } 252 /* XXX TGEN devclass_find_free_unit() implementation */ 253 while (freeunit < devclass_get_maxunit(ata_devclass) && 254 devclass_get_device(ata_devclass, freeunit) != NULL) 255 freeunit++; 256 device_add_child(dev, "ata", freeunit); 257 } 258 bus_generic_attach(dev); 259 return 0; 260 } 261 262 int 263 ata_pci_detach(device_t dev) 264 { 265 struct ata_pci_controller *ctlr = device_get_softc(dev); 266 device_t *children; 267 int nchildren, i; 268 269 /* detach & delete all children */ 270 if (!device_get_children(dev, &children, &nchildren)) { 271 for (i = 0; i < nchildren; i++) 272 device_delete_child(dev, children[i]); 273 kfree(children, M_TEMP); 274 } 275 276 if (ctlr->r_irq) { 277 bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle); 278 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ctlr->r_irq); 279 ctlr->r_irq = 0; 280 } 281 if (ctlr->r_res2) { 282 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 283 ctlr->r_res2 = 0; 284 } 285 if (ctlr->r_res1) { 286 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1); 287 ctlr->r_res1 = 0; 288 } 289 290 return 0; 291 } 292 293 struct resource * 294 ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 295 u_long start, u_long end, u_long count, u_int flags) 296 { 297 struct ata_pci_controller *controller = device_get_softc(dev); 298 int unit = ((struct ata_channel *)device_get_softc(child))->unit; 299 struct resource *res = NULL; 300 int myrid; 301 302 if (type == SYS_RES_IOPORT) { 303 switch (*rid) { 304 case ATA_IOADDR_RID: 305 if (controller->legacy) { 306 start = (unit ? ATA_SECONDARY : ATA_PRIMARY); 307 count = ATA_IOSIZE; 308 end = start + count - 1; 309 } 310 myrid = PCIR_BAR(0) + (unit << 3); 311 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 312 SYS_RES_IOPORT, &myrid, 313 start, end, count, flags); 314 break; 315 316 case ATA_CTLADDR_RID: 317 if (controller->legacy) { 318 start = (unit ? ATA_SECONDARY : ATA_PRIMARY) + ATA_CTLOFFSET; 319 count = ATA_CTLIOSIZE; 320 end = start + count - 1; 321 } 322 myrid = PCIR_BAR(1) + (unit << 3); 323 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 324 SYS_RES_IOPORT, &myrid, 325 start, end, count, flags); 326 break; 327 } 328 } 329 if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) { 330 if (controller->legacy) { 331 int irq = (unit == 0 ? 14 : 15); 332 333 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 334 SYS_RES_IRQ, rid, irq, irq, 1, flags); 335 } 336 else 337 res = controller->r_irq; 338 } 339 return res; 340 } 341 342 int 343 ata_pci_release_resource(device_t dev, device_t child, int type, int rid, 344 struct resource *r) 345 { 346 struct ata_pci_controller *controller = device_get_softc(dev); 347 int unit = ((struct ata_channel *)device_get_softc(child))->unit; 348 349 if (type == SYS_RES_IOPORT) { 350 switch (rid) { 351 case ATA_IOADDR_RID: 352 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 353 SYS_RES_IOPORT, 354 PCIR_BAR(0) + (unit << 3), r); 355 break; 356 357 case ATA_CTLADDR_RID: 358 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, 359 SYS_RES_IOPORT, 360 PCIR_BAR(1) + (unit << 3), r); 361 break; 362 default: 363 return ENOENT; 364 } 365 } 366 if (type == SYS_RES_IRQ) { 367 if (rid != ATA_IRQ_RID) 368 return ENOENT; 369 370 if (controller->legacy) { 371 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 372 SYS_RES_IRQ, rid, r); 373 } 374 else 375 return 0; 376 } 377 return EINVAL; 378 } 379 380 int 381 ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq, 382 int flags, driver_intr_t *function, void *argument, 383 void **cookiep) 384 { 385 struct ata_pci_controller *controller = device_get_softc(dev); 386 387 if (controller->legacy) { 388 return BUS_SETUP_INTR(device_get_parent(dev), child, irq, 389 flags, function, argument, cookiep, NULL); 390 } 391 else { 392 struct ata_pci_controller *controller = device_get_softc(dev); 393 int unit = ((struct ata_channel *)device_get_softc(child))->unit; 394 395 controller->interrupt[unit].function = function; 396 controller->interrupt[unit].argument = argument; 397 *cookiep = controller; 398 return 0; 399 } 400 } 401 402 int 403 ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 404 void *cookie) 405 { 406 struct ata_pci_controller *controller = device_get_softc(dev); 407 408 if (controller->legacy) { 409 return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie); 410 } 411 else { 412 struct ata_pci_controller *controller = device_get_softc(dev); 413 int unit = ((struct ata_channel *)device_get_softc(child))->unit; 414 415 controller->interrupt[unit].function = NULL; 416 controller->interrupt[unit].argument = NULL; 417 return 0; 418 } 419 } 420 421 int 422 ata_pci_allocate(device_t dev) 423 { 424 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 425 struct ata_channel *ch = device_get_softc(dev); 426 struct resource *io = NULL, *ctlio = NULL; 427 int i, rid; 428 429 rid = ATA_IOADDR_RID; 430 if (!(io = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, RF_ACTIVE))) 431 return ENXIO; 432 433 rid = ATA_CTLADDR_RID; 434 if (!(ctlio = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,RF_ACTIVE))){ 435 bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io); 436 return ENXIO; 437 } 438 439 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 440 ch->r_io[i].res = io; 441 ch->r_io[i].offset = i; 442 } 443 ch->r_io[ATA_CONTROL].res = ctlio; 444 ch->r_io[ATA_CONTROL].offset = ctlr->legacy ? 0 : 2; 445 ch->r_io[ATA_IDX_ADDR].res = io; 446 ata_default_registers(dev); 447 if (ctlr->r_res1) { 448 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 449 ch->r_io[i].res = ctlr->r_res1; 450 ch->r_io[i].offset = (i - ATA_BMCMD_PORT) + (ch->unit*ATA_BMIOSIZE); 451 } 452 } 453 454 ata_pci_hw(dev); 455 return 0; 456 } 457 458 void 459 ata_pci_hw(device_t dev) 460 { 461 struct ata_channel *ch = device_get_softc(dev); 462 463 ata_generic_hw(dev); 464 ch->hw.status = ata_pci_status; 465 } 466 467 int 468 ata_pci_status(device_t dev) 469 { 470 struct ata_pci_controller *controller = 471 device_get_softc(device_get_parent(dev)); 472 struct ata_channel *ch = device_get_softc(dev); 473 474 if ((dumping || !controller->legacy) && 475 ch->dma && ((ch->flags & ATA_ALWAYS_DMASTAT) || 476 (ch->dma->flags & ATA_DMA_ACTIVE))) { 477 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 478 479 /* 480 * Strictly speaking the DMA engine should already be stopped 481 * once we receive the interrupt. 482 * However at least ICH controllers seem to have the habbit 483 * of not clearing the active bit even though the interrupt 484 * is valid. 485 * To make sure we wait a little bit (to make sure that other 486 * buggy systems actually have a chance of finishing their 487 * DMA transaction) and then ignore the active bit. 488 */ 489 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) == 490 (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) { 491 DELAY(100); 492 bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 493 } 494 if ((bmstat & ATA_BMSTAT_INTERRUPT) == 0) 495 return 0; 496 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR); 497 DELAY(1); 498 } 499 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 500 DELAY(100); 501 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) 502 return 0; 503 } 504 return 1; 505 } 506 507 static int 508 ata_pci_dmastart(device_t dev) 509 { 510 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 511 u_int8_t val; 512 513 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) | 514 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 515 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->sg_bus); 516 ch->dma->flags |= ATA_DMA_ACTIVE; 517 val = ATA_IDX_INB(ch, ATA_BMCMD_PORT); 518 if (ch->dma->flags & ATA_DMA_READ) 519 val |= ATA_BMCMD_WRITE_READ; 520 else 521 val &= ~ATA_BMCMD_WRITE_READ; 522 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, val); 523 524 /* 525 * Issue the start command separately from configuration setup, 526 * in case the hardware latches portions of the configuration. 527 */ 528 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, val | ATA_BMCMD_START_STOP); 529 530 return 0; 531 } 532 533 static int 534 ata_pci_dmastop(device_t dev) 535 { 536 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 537 int error; 538 539 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 540 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 541 ch->dma->flags &= ~ATA_DMA_ACTIVE; 542 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 543 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 544 return error; 545 } 546 547 static void 548 ata_pci_dmareset(device_t dev) 549 { 550 struct ata_channel *ch = device_get_softc(dev); 551 552 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 553 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 554 ch->dma->flags &= ~ATA_DMA_ACTIVE; 555 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 556 ch->dma->unload(dev); 557 } 558 559 void 560 ata_pci_dmainit(device_t dev) 561 { 562 struct ata_channel *ch = device_get_softc(dev); 563 564 ata_dmainit(dev); 565 if (ch->dma) { 566 ch->dma->start = ata_pci_dmastart; 567 ch->dma->stop = ata_pci_dmastop; 568 ch->dma->reset = ata_pci_dmareset; 569 } 570 } 571 572 char * 573 ata_pcivendor2str(device_t dev) 574 { 575 switch (pci_get_vendor(dev)) { 576 case ATA_ACARD_ID: return "Acard"; 577 case ATA_ACER_LABS_ID: return "AcerLabs"; 578 case ATA_AMD_ID: return "AMD"; 579 case ATA_ATI_ID: return "ATI"; 580 case ATA_CYRIX_ID: return "Cyrix"; 581 case ATA_CYPRESS_ID: return "Cypress"; 582 case ATA_HIGHPOINT_ID: return "HighPoint"; 583 case ATA_INTEL_ID: return "Intel"; 584 case ATA_ITE_ID: return "ITE"; 585 case ATA_JMICRON_ID: return "JMicron"; 586 case ATA_MARVELL_ID: return "Marvell"; 587 case ATA_NATIONAL_ID: return "National"; 588 case ATA_NETCELL_ID: return "Netcell"; 589 case ATA_NVIDIA_ID: return "nVidia"; 590 case ATA_PROMISE_ID: return "Promise"; 591 case ATA_SERVERWORKS_ID: return "ServerWorks"; 592 case ATA_SILICON_IMAGE_ID: return "SiI"; 593 case ATA_SIS_ID: return "SiS"; 594 case ATA_VIA_ID: return "VIA"; 595 case ATA_CENATEK_ID: return "Cenatek"; 596 case ATA_MICRON_ID: return "Micron"; 597 default: return "Generic"; 598 } 599 } 600 601 static device_method_t ata_pci_methods[] = { 602 /* device interface */ 603 DEVMETHOD(device_probe, ata_pci_probe), 604 DEVMETHOD(device_attach, ata_pci_attach), 605 DEVMETHOD(device_detach, ata_pci_detach), 606 DEVMETHOD(device_shutdown, bus_generic_shutdown), 607 DEVMETHOD(device_suspend, bus_generic_suspend), 608 DEVMETHOD(device_resume, bus_generic_resume), 609 610 /* bus methods */ 611 DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource), 612 DEVMETHOD(bus_release_resource, ata_pci_release_resource), 613 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 614 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 615 DEVMETHOD(bus_setup_intr, ata_pci_setup_intr), 616 DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr), 617 618 { 0, 0 } 619 }; 620 621 devclass_t atapci_devclass; 622 623 static driver_t ata_pci_driver = { 624 "atapci", 625 ata_pci_methods, 626 sizeof(struct ata_pci_controller), 627 }; 628 629 DRIVER_MODULE(atapci, pci, ata_pci_driver, atapci_devclass, 0, 0); 630 MODULE_VERSION(atapci, 1); 631 MODULE_DEPEND(atapci, ata, 1, 1, 1); 632 633 static int 634 ata_pcichannel_probe(device_t dev) 635 { 636 struct ata_channel *ch = device_get_softc(dev); 637 device_t *children; 638 int count, i; 639 char buffer[32]; 640 641 /* take care of green memory */ 642 bzero(ch, sizeof(struct ata_channel)); 643 644 /* find channel number on this controller */ 645 device_get_children(device_get_parent(dev), &children, &count); 646 for (i = 0; i < count; i++) { 647 if (children[i] == dev) 648 ch->unit = i; 649 } 650 kfree(children, M_TEMP); 651 652 ksprintf(buffer, "ATA channel %d", ch->unit); 653 device_set_desc_copy(dev, buffer); 654 655 return ata_probe(dev); 656 } 657 658 static int 659 ata_pcichannel_attach(device_t dev) 660 { 661 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 662 struct ata_channel *ch = device_get_softc(dev); 663 int error; 664 665 if (ctlr->dmainit) 666 ctlr->dmainit(dev); 667 if (ch->dma) 668 ch->dma->alloc(dev); 669 670 if ((error = ctlr->allocate(dev))) { 671 if (ch->dma) 672 ch->dma->free(dev); 673 return error; 674 } 675 676 return ata_attach(dev); 677 } 678 679 static int 680 ata_pcichannel_detach(device_t dev) 681 { 682 struct ata_channel *ch = device_get_softc(dev); 683 int error; 684 685 if ((error = ata_detach(dev))) 686 return error; 687 688 if (ch->dma) 689 ch->dma->free(dev); 690 691 /* XXX SOS free resources for io and ctlio ?? */ 692 693 return 0; 694 } 695 696 static int 697 ata_pcichannel_locking(device_t dev, int mode) 698 { 699 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 700 struct ata_channel *ch = device_get_softc(dev); 701 702 if (ctlr->locking) 703 return ctlr->locking(dev, mode); 704 else 705 return ch->unit; 706 } 707 708 static void 709 ata_pcichannel_reset(device_t dev) 710 { 711 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 712 struct ata_channel *ch = device_get_softc(dev); 713 714 /* if DMA engine present reset it */ 715 if (ch->dma) { 716 if (ch->dma->reset) 717 ch->dma->reset(dev); 718 ch->dma->unload(dev); 719 } 720 721 /* reset the controller HW */ 722 if (ctlr->reset) 723 ctlr->reset(dev); 724 else 725 ata_generic_reset(dev); 726 } 727 728 static void 729 ata_pcichannel_setmode(device_t parent, device_t dev) 730 { 731 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 732 struct ata_device *atadev = device_get_softc(dev); 733 int mode = atadev->mode; 734 735 ctlr->setmode(dev, ATA_PIO_MAX); 736 if (mode >= ATA_DMA) 737 ctlr->setmode(dev, mode); 738 } 739 740 static device_method_t ata_pcichannel_methods[] = { 741 /* device interface */ 742 DEVMETHOD(device_probe, ata_pcichannel_probe), 743 DEVMETHOD(device_attach, ata_pcichannel_attach), 744 DEVMETHOD(device_detach, ata_pcichannel_detach), 745 DEVMETHOD(device_shutdown, bus_generic_shutdown), 746 DEVMETHOD(device_suspend, ata_suspend), 747 DEVMETHOD(device_resume, ata_resume), 748 749 /* ATA methods */ 750 DEVMETHOD(ata_setmode, ata_pcichannel_setmode), 751 DEVMETHOD(ata_locking, ata_pcichannel_locking), 752 DEVMETHOD(ata_reset, ata_pcichannel_reset), 753 754 { 0, 0 } 755 }; 756 757 driver_t ata_pcichannel_driver = { 758 "ata", 759 ata_pcichannel_methods, 760 sizeof(struct ata_channel), 761 }; 762 763 DRIVER_MODULE(ata, atapci, ata_pcichannel_driver, ata_devclass, 0, 0); 764