1a1917f14Szrj /*-
2a1917f14Szrj * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
3a1917f14Szrj * All rights reserved.
4a1917f14Szrj *
5a1917f14Szrj * Redistribution and use in source and binary forms, with or without
6a1917f14Szrj * modification, are permitted provided that the following conditions
7a1917f14Szrj * are met:
8a1917f14Szrj * 1. Redistributions of source code must retain the above copyright
9a1917f14Szrj * notice, this list of conditions and the following disclaimer,
10a1917f14Szrj * without modification, immediately at the beginning of the file.
11a1917f14Szrj * 2. Redistributions in binary form must reproduce the above copyright
12a1917f14Szrj * notice, this list of conditions and the following disclaimer in the
13a1917f14Szrj * documentation and/or other materials provided with the distribution.
14a1917f14Szrj *
15a1917f14Szrj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16a1917f14Szrj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17a1917f14Szrj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18a1917f14Szrj * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19a1917f14Szrj * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20a1917f14Szrj * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21a1917f14Szrj * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22a1917f14Szrj * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23a1917f14Szrj * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24a1917f14Szrj * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25a1917f14Szrj */
26a1917f14Szrj
27a1917f14Szrj /* local prototypes */
28a1917f14Szrj static int ata_ali_chipinit(device_t dev);
29a1917f14Szrj static int ata_ali_allocate(device_t dev);
30a1917f14Szrj static int ata_ali_sata_allocate(device_t dev);
31a1917f14Szrj static void ata_ali_reset(device_t dev);
32a1917f14Szrj static void ata_ali_setmode(device_t dev, int mode);
33a1917f14Szrj
34853eb30dSzrj /* misc defines */
35853eb30dSzrj #define ALI_OLD 0x01
36853eb30dSzrj #define ALI_NEW 0x02
37853eb30dSzrj #define ALI_SATA 0x04
38853eb30dSzrj
39a1917f14Szrj /*
40a1917f14Szrj * Acer Labs Inc (ALI) chipset support functions
41a1917f14Szrj */
42a1917f14Szrj int
ata_ali_ident(device_t dev)43a1917f14Szrj ata_ali_ident(device_t dev)
44a1917f14Szrj {
45a1917f14Szrj struct ata_pci_controller *ctlr = device_get_softc(dev);
4659503772Szrj static const struct ata_chip_id ids[] =
47853eb30dSzrj {{ ATA_ALI_5289, 0x00, 2, ALI_SATA, ATA_SA150, "M5289" },
48853eb30dSzrj { ATA_ALI_5288, 0x00, 4, ALI_SATA, ATA_SA300, "M5288" },
49853eb30dSzrj { ATA_ALI_5287, 0x00, 4, ALI_SATA, ATA_SA150, "M5287" },
50853eb30dSzrj { ATA_ALI_5281, 0x00, 2, ALI_SATA, ATA_SA150, "M5281" },
51853eb30dSzrj { ATA_ALI_5229, 0xc5, 0, ALI_NEW, ATA_UDMA6, "M5229" },
52853eb30dSzrj { ATA_ALI_5229, 0xc4, 0, ALI_NEW, ATA_UDMA5, "M5229" },
53853eb30dSzrj { ATA_ALI_5229, 0xc2, 0, ALI_NEW, ATA_UDMA4, "M5229" },
54853eb30dSzrj { ATA_ALI_5229, 0x20, 0, ALI_OLD, ATA_UDMA2, "M5229" },
55853eb30dSzrj { ATA_ALI_5229, 0x00, 0, ALI_OLD, ATA_WDMA2, "M5229" },
56a1917f14Szrj { 0, 0, 0, 0, 0, 0}};
57a1917f14Szrj
5859503772Szrj if (pci_get_vendor(dev) != ATA_ACER_LABS_ID)
59a1917f14Szrj return ENXIO;
60a1917f14Szrj
6159503772Szrj if (!(ctlr->chip = ata_match_chip(dev, ids)))
6259503772Szrj return ENXIO;
6359503772Szrj
6459503772Szrj ata_set_desc(dev);
65a1917f14Szrj ctlr->chipinit = ata_ali_chipinit;
66a1917f14Szrj return 0;
67a1917f14Szrj }
68a1917f14Szrj
69a1917f14Szrj static int
ata_ali_chipinit(device_t dev)70a1917f14Szrj ata_ali_chipinit(device_t dev)
71a1917f14Szrj {
72a1917f14Szrj struct ata_pci_controller *ctlr = device_get_softc(dev);
73a1917f14Szrj
7443156ad7Szrj if (ata_setup_interrupt(dev, ata_generic_intr))
75a1917f14Szrj return ENXIO;
76a1917f14Szrj
77a1917f14Szrj switch (ctlr->chip->cfg2) {
78853eb30dSzrj case ALI_SATA:
79a1917f14Szrj ctlr->channels = ctlr->chip->cfg1;
80a1917f14Szrj ctlr->allocate = ata_ali_sata_allocate;
81a1917f14Szrj ctlr->setmode = ata_sata_setmode;
82a1917f14Szrj
83a1917f14Szrj /* AHCI mode is correctly supported only on the ALi 5288. */
84a1917f14Szrj if ((ctlr->chip->chipid == ATA_ALI_5288) &&
85a1917f14Szrj (ata_ahci_chipinit(dev) != ENXIO))
86a1917f14Szrj return 0;
87a1917f14Szrj
88a1917f14Szrj /* enable PCI interrupt */
89a1917f14Szrj pci_write_config(dev, PCIR_COMMAND,
90a1917f14Szrj pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
91a1917f14Szrj break;
92a1917f14Szrj
93853eb30dSzrj case ALI_NEW:
94a1917f14Szrj /* use device interrupt as byte count end */
95a1917f14Szrj pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1);
96a1917f14Szrj
97a1917f14Szrj /* enable cable detection and UDMA support on newer chips */
98a1917f14Szrj pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1);
99a1917f14Szrj
100a1917f14Szrj /* enable ATAPI UDMA mode */
101a1917f14Szrj pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x01, 1);
102a1917f14Szrj
103a1917f14Szrj /* only chips with revision > 0xc4 can do 48bit DMA */
104a1917f14Szrj if (ctlr->chip->chiprev <= 0xc4)
105a1917f14Szrj device_printf(dev,
106a1917f14Szrj "using PIO transfers above 137GB as workaround for "
107a1917f14Szrj "48bit DMA access bug, expect reduced performance\n");
108a1917f14Szrj ctlr->allocate = ata_ali_allocate;
109a1917f14Szrj ctlr->reset = ata_ali_reset;
110a1917f14Szrj ctlr->setmode = ata_ali_setmode;
111a1917f14Szrj break;
112a1917f14Szrj
113853eb30dSzrj case ALI_OLD:
114a1917f14Szrj /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
115a1917f14Szrj pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
116a1917f14Szrj ctlr->setmode = ata_ali_setmode;
117a1917f14Szrj break;
118a1917f14Szrj }
119a1917f14Szrj return 0;
120a1917f14Szrj }
121a1917f14Szrj
122a1917f14Szrj static int
ata_ali_allocate(device_t dev)123a1917f14Szrj ata_ali_allocate(device_t dev)
124a1917f14Szrj {
125a1917f14Szrj struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
126a1917f14Szrj struct ata_channel *ch = device_get_softc(dev);
127a1917f14Szrj
128a1917f14Szrj /* setup the usual register normal pci style */
129a1917f14Szrj if (ata_pci_allocate(dev))
130a1917f14Szrj return ENXIO;
131a1917f14Szrj
132a1917f14Szrj /* older chips can't do 48bit DMA transfers */
133a1917f14Szrj if (ctlr->chip->chiprev <= 0xc4) {
134a1917f14Szrj ch->flags |= ATA_NO_48BIT_DMA;
135a1917f14Szrj if (ch->dma->max_iosize > 256 * 512)
136a1917f14Szrj ch->dma->max_iosize = 256 * 512;
137a1917f14Szrj }
138a1917f14Szrj
139a1917f14Szrj return 0;
140a1917f14Szrj }
141a1917f14Szrj
142a1917f14Szrj static int
ata_ali_sata_allocate(device_t dev)143a1917f14Szrj ata_ali_sata_allocate(device_t dev)
144a1917f14Szrj {
145a1917f14Szrj device_t parent = device_get_parent(dev);
146a1917f14Szrj struct ata_pci_controller *ctlr = device_get_softc(parent);
147a1917f14Szrj struct ata_channel *ch = device_get_softc(dev);
148a1917f14Szrj struct resource *io = NULL, *ctlio = NULL;
149a1917f14Szrj int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
150a1917f14Szrj int i, rid;
151a1917f14Szrj
152a1917f14Szrj rid = PCIR_BAR(0) + (unit01 ? 8 : 0);
153a1917f14Szrj io = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
154a1917f14Szrj if (!io)
155a1917f14Szrj return ENXIO;
156a1917f14Szrj
157a1917f14Szrj rid = PCIR_BAR(1) + (unit01 ? 8 : 0);
158a1917f14Szrj ctlio = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
159a1917f14Szrj if (!ctlio) {
160a1917f14Szrj bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io);
161a1917f14Szrj return ENXIO;
162a1917f14Szrj }
163a1917f14Szrj
164a1917f14Szrj for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
165a1917f14Szrj ch->r_io[i].res = io;
166a1917f14Szrj ch->r_io[i].offset = i + (unit10 ? 8 : 0);
167a1917f14Szrj }
168a1917f14Szrj ch->r_io[ATA_CONTROL].res = ctlio;
169a1917f14Szrj ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0);
170a1917f14Szrj ch->r_io[ATA_IDX_ADDR].res = io;
171a1917f14Szrj ata_default_registers(dev);
172a1917f14Szrj if (ctlr->r_res1) {
173a1917f14Szrj for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
174a1917f14Szrj ch->r_io[i].res = ctlr->r_res1;
175a1917f14Szrj ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
176a1917f14Szrj }
177a1917f14Szrj }
178a1917f14Szrj ch->flags |= ATA_NO_SLAVE;
179a1917f14Szrj
180a1917f14Szrj /* XXX SOS PHY handling awkward in ALI chip not supported yet */
181a1917f14Szrj ata_pci_hw(dev);
182a1917f14Szrj return 0;
183a1917f14Szrj }
184a1917f14Szrj
185a1917f14Szrj static void
ata_ali_reset(device_t dev)186a1917f14Szrj ata_ali_reset(device_t dev)
187a1917f14Szrj {
188a1917f14Szrj struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
189a1917f14Szrj struct ata_channel *ch = device_get_softc(dev);
190a1917f14Szrj device_t *children;
191a1917f14Szrj int nchildren, i;
192a1917f14Szrj
193a1917f14Szrj ata_generic_reset(dev);
194a1917f14Szrj
195a1917f14Szrj /*
196a1917f14Szrj * workaround for datacorruption bug found on at least SUN Blade-100
197a1917f14Szrj * find the ISA function on the southbridge and disable then enable
198a1917f14Szrj * the ATA channel tristate buffer
199a1917f14Szrj */
200a1917f14Szrj if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) {
201a1917f14Szrj if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) {
202a1917f14Szrj for (i = 0; i < nchildren; i++) {
203a1917f14Szrj if (pci_get_devid(children[i]) == ATA_ALI_1533) {
204a1917f14Szrj pci_write_config(children[i], 0x58,
205a1917f14Szrj pci_read_config(children[i], 0x58, 1) &
206a1917f14Szrj ~(0x04 << ch->unit), 1);
207a1917f14Szrj pci_write_config(children[i], 0x58,
208a1917f14Szrj pci_read_config(children[i], 0x58, 1) |
209a1917f14Szrj (0x04 << ch->unit), 1);
210a1917f14Szrj break;
211a1917f14Szrj }
212a1917f14Szrj }
213a1917f14Szrj kfree(children, M_TEMP);
214a1917f14Szrj }
215a1917f14Szrj }
216a1917f14Szrj }
217a1917f14Szrj
218a1917f14Szrj static void
ata_ali_setmode(device_t dev,int mode)219a1917f14Szrj ata_ali_setmode(device_t dev, int mode)
220a1917f14Szrj {
221a1917f14Szrj device_t gparent = GRANDPARENT(dev);
222a1917f14Szrj struct ata_pci_controller *ctlr = device_get_softc(gparent);
223a1917f14Szrj struct ata_channel *ch = device_get_softc(device_get_parent(dev));
224a1917f14Szrj struct ata_device *atadev = device_get_softc(dev);
225*2458a87aSzrj int devno = (ch->unit << 1) + atadev->unit;
226a1917f14Szrj int error;
22759503772Szrj static const uint32_t piotimings[] =
22859503772Szrj { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
22959503772Szrj 0x00310001, 0x00440001, 0x00330001, 0x00310001};
23059503772Szrj static const uint8_t udma[] =
23159503772Szrj {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d};
23259503772Szrj uint32_t word54;
233a1917f14Szrj
234a1917f14Szrj mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
235a1917f14Szrj
236853eb30dSzrj if (ctlr->chip->cfg2 & ALI_NEW) {
237a1917f14Szrj if (mode > ATA_UDMA2 &&
238a1917f14Szrj pci_read_config(gparent, 0x4a, 1) & (1 << ch->unit)) {
239a1917f14Szrj ata_print_cable(dev, "controller");
240a1917f14Szrj mode = ATA_UDMA2;
241a1917f14Szrj }
242a1917f14Szrj }
243a1917f14Szrj else
244a1917f14Szrj mode = ata_check_80pin(dev, mode);
245a1917f14Szrj
246853eb30dSzrj if (ctlr->chip->cfg2 & ALI_OLD) {
247a1917f14Szrj /* doesn't support ATAPI DMA on write */
248a1917f14Szrj ch->flags |= ATA_ATAPI_DMA_RO;
249a1917f14Szrj if (ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) {
250a1917f14Szrj /* doesn't support ATAPI DMA on two ATAPI devices */
251a1917f14Szrj device_printf(dev, "two atapi devices on this channel, no DMA\n");
252a1917f14Szrj mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
253a1917f14Szrj }
254a1917f14Szrj }
255a1917f14Szrj
256a1917f14Szrj error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
257a1917f14Szrj
258a1917f14Szrj if (bootverbose)
259a1917f14Szrj device_printf(dev, "%ssetting %s on %s chip\n",
260a1917f14Szrj (error) ? "FAILURE " : "",
261a1917f14Szrj ata_mode2str(mode), ctlr->chip->text);
262a1917f14Szrj if (!error) {
263a1917f14Szrj if (mode >= ATA_UDMA0) {
26459503772Szrj word54 = pci_read_config(gparent, 0x54, 4);
265a1917f14Szrj
266a1917f14Szrj word54 &= ~(0x000f000f << (devno << 2));
267a1917f14Szrj word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
268a1917f14Szrj pci_write_config(gparent, 0x54, word54, 4);
269a1917f14Szrj pci_write_config(gparent, 0x58 + (ch->unit << 2),
270a1917f14Szrj 0x00310001, 4);
271a1917f14Szrj }
272a1917f14Szrj else {
273a1917f14Szrj pci_write_config(gparent, 0x54, pci_read_config(gparent, 0x54, 4) &
274a1917f14Szrj ~(0x0008000f << (devno << 2)), 4);
275a1917f14Szrj pci_write_config(gparent, 0x58 + (ch->unit << 2),
276a1917f14Szrj piotimings[ata_mode2idx(mode)], 4);
277a1917f14Szrj }
278a1917f14Szrj atadev->mode = mode;
279a1917f14Szrj }
280a1917f14Szrj }
281