1 /*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* local prototypes */ 28 static int ata_ali_chipinit(device_t dev); 29 static int ata_ali_allocate(device_t dev); 30 static int ata_ali_sata_allocate(device_t dev); 31 static void ata_ali_reset(device_t dev); 32 static void ata_ali_setmode(device_t dev, int mode); 33 34 /* misc defines */ 35 #define ALI_OLD 0x01 36 #define ALI_NEW 0x02 37 #define ALI_SATA 0x04 38 39 /* 40 * Acer Labs Inc (ALI) chipset support functions 41 */ 42 int 43 ata_ali_ident(device_t dev) 44 { 45 struct ata_pci_controller *ctlr = device_get_softc(dev); 46 static const struct ata_chip_id ids[] = 47 {{ ATA_ALI_5289, 0x00, 2, ALI_SATA, ATA_SA150, "M5289" }, 48 { ATA_ALI_5288, 0x00, 4, ALI_SATA, ATA_SA300, "M5288" }, 49 { ATA_ALI_5287, 0x00, 4, ALI_SATA, ATA_SA150, "M5287" }, 50 { ATA_ALI_5281, 0x00, 2, ALI_SATA, ATA_SA150, "M5281" }, 51 { ATA_ALI_5229, 0xc5, 0, ALI_NEW, ATA_UDMA6, "M5229" }, 52 { ATA_ALI_5229, 0xc4, 0, ALI_NEW, ATA_UDMA5, "M5229" }, 53 { ATA_ALI_5229, 0xc2, 0, ALI_NEW, ATA_UDMA4, "M5229" }, 54 { ATA_ALI_5229, 0x20, 0, ALI_OLD, ATA_UDMA2, "M5229" }, 55 { ATA_ALI_5229, 0x00, 0, ALI_OLD, ATA_WDMA2, "M5229" }, 56 { 0, 0, 0, 0, 0, 0}}; 57 58 if (pci_get_vendor(dev) != ATA_ACER_LABS_ID) 59 return ENXIO; 60 61 if (!(ctlr->chip = ata_match_chip(dev, ids))) 62 return ENXIO; 63 64 ata_set_desc(dev); 65 ctlr->chipinit = ata_ali_chipinit; 66 return 0; 67 } 68 69 static int 70 ata_ali_chipinit(device_t dev) 71 { 72 struct ata_pci_controller *ctlr = device_get_softc(dev); 73 74 if (ata_setup_interrupt(dev, ata_generic_intr)) 75 return ENXIO; 76 77 switch (ctlr->chip->cfg2) { 78 case ALI_SATA: 79 ctlr->channels = ctlr->chip->cfg1; 80 ctlr->allocate = ata_ali_sata_allocate; 81 ctlr->setmode = ata_sata_setmode; 82 83 /* AHCI mode is correctly supported only on the ALi 5288. */ 84 if ((ctlr->chip->chipid == ATA_ALI_5288) && 85 (ata_ahci_chipinit(dev) != ENXIO)) 86 return 0; 87 88 /* enable PCI interrupt */ 89 pci_write_config(dev, PCIR_COMMAND, 90 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 91 break; 92 93 case ALI_NEW: 94 /* use device interrupt as byte count end */ 95 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1); 96 97 /* enable cable detection and UDMA support on newer chips */ 98 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1); 99 100 /* enable ATAPI UDMA mode */ 101 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x01, 1); 102 103 /* only chips with revision > 0xc4 can do 48bit DMA */ 104 if (ctlr->chip->chiprev <= 0xc4) 105 device_printf(dev, 106 "using PIO transfers above 137GB as workaround for " 107 "48bit DMA access bug, expect reduced performance\n"); 108 ctlr->allocate = ata_ali_allocate; 109 ctlr->reset = ata_ali_reset; 110 ctlr->setmode = ata_ali_setmode; 111 break; 112 113 case ALI_OLD: 114 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */ 115 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1); 116 ctlr->setmode = ata_ali_setmode; 117 break; 118 } 119 return 0; 120 } 121 122 static int 123 ata_ali_allocate(device_t dev) 124 { 125 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 126 struct ata_channel *ch = device_get_softc(dev); 127 128 /* setup the usual register normal pci style */ 129 if (ata_pci_allocate(dev)) 130 return ENXIO; 131 132 /* older chips can't do 48bit DMA transfers */ 133 if (ctlr->chip->chiprev <= 0xc4) { 134 ch->flags |= ATA_NO_48BIT_DMA; 135 if (ch->dma->max_iosize > 256 * 512) 136 ch->dma->max_iosize = 256 * 512; 137 } 138 139 return 0; 140 } 141 142 static int 143 ata_ali_sata_allocate(device_t dev) 144 { 145 device_t parent = device_get_parent(dev); 146 struct ata_pci_controller *ctlr = device_get_softc(parent); 147 struct ata_channel *ch = device_get_softc(dev); 148 struct resource *io = NULL, *ctlio = NULL; 149 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 150 int i, rid; 151 152 rid = PCIR_BAR(0) + (unit01 ? 8 : 0); 153 io = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE); 154 if (!io) 155 return ENXIO; 156 157 rid = PCIR_BAR(1) + (unit01 ? 8 : 0); 158 ctlio = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE); 159 if (!ctlio) { 160 bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io); 161 return ENXIO; 162 } 163 164 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 165 ch->r_io[i].res = io; 166 ch->r_io[i].offset = i + (unit10 ? 8 : 0); 167 } 168 ch->r_io[ATA_CONTROL].res = ctlio; 169 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0); 170 ch->r_io[ATA_IDX_ADDR].res = io; 171 ata_default_registers(dev); 172 if (ctlr->r_res1) { 173 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 174 ch->r_io[i].res = ctlr->r_res1; 175 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 176 } 177 } 178 ch->flags |= ATA_NO_SLAVE; 179 180 /* XXX SOS PHY handling awkward in ALI chip not supported yet */ 181 ata_pci_hw(dev); 182 return 0; 183 } 184 185 static void 186 ata_ali_reset(device_t dev) 187 { 188 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 189 struct ata_channel *ch = device_get_softc(dev); 190 device_t *children; 191 int nchildren, i; 192 193 ata_generic_reset(dev); 194 195 /* 196 * workaround for datacorruption bug found on at least SUN Blade-100 197 * find the ISA function on the southbridge and disable then enable 198 * the ATA channel tristate buffer 199 */ 200 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) { 201 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) { 202 for (i = 0; i < nchildren; i++) { 203 if (pci_get_devid(children[i]) == ATA_ALI_1533) { 204 pci_write_config(children[i], 0x58, 205 pci_read_config(children[i], 0x58, 1) & 206 ~(0x04 << ch->unit), 1); 207 pci_write_config(children[i], 0x58, 208 pci_read_config(children[i], 0x58, 1) | 209 (0x04 << ch->unit), 1); 210 break; 211 } 212 } 213 kfree(children, M_TEMP); 214 } 215 } 216 } 217 218 static void 219 ata_ali_setmode(device_t dev, int mode) 220 { 221 device_t gparent = GRANDPARENT(dev); 222 struct ata_pci_controller *ctlr = device_get_softc(gparent); 223 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 224 struct ata_device *atadev = device_get_softc(dev); 225 int devno = (ch->unit << 1) + atadev->unit; 226 int error; 227 static const uint32_t piotimings[] = 228 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001, 229 0x00310001, 0x00440001, 0x00330001, 0x00310001}; 230 static const uint8_t udma[] = 231 {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d}; 232 uint32_t word54; 233 234 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 235 236 if (ctlr->chip->cfg2 & ALI_NEW) { 237 if (mode > ATA_UDMA2 && 238 pci_read_config(gparent, 0x4a, 1) & (1 << ch->unit)) { 239 ata_print_cable(dev, "controller"); 240 mode = ATA_UDMA2; 241 } 242 } 243 else 244 mode = ata_check_80pin(dev, mode); 245 246 if (ctlr->chip->cfg2 & ALI_OLD) { 247 /* doesn't support ATAPI DMA on write */ 248 ch->flags |= ATA_ATAPI_DMA_RO; 249 if (ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) { 250 /* doesn't support ATAPI DMA on two ATAPI devices */ 251 device_printf(dev, "two atapi devices on this channel, no DMA\n"); 252 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 253 } 254 } 255 256 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 257 258 if (bootverbose) 259 device_printf(dev, "%ssetting %s on %s chip\n", 260 (error) ? "FAILURE " : "", 261 ata_mode2str(mode), ctlr->chip->text); 262 if (!error) { 263 if (mode >= ATA_UDMA0) { 264 word54 = pci_read_config(gparent, 0x54, 4); 265 266 word54 &= ~(0x000f000f << (devno << 2)); 267 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2)); 268 pci_write_config(gparent, 0x54, word54, 4); 269 pci_write_config(gparent, 0x58 + (ch->unit << 2), 270 0x00310001, 4); 271 } 272 else { 273 pci_write_config(gparent, 0x54, pci_read_config(gparent, 0x54, 4) & 274 ~(0x0008000f << (devno << 2)), 4); 275 pci_write_config(gparent, 0x58 + (ch->unit << 2), 276 piotimings[ata_mode2idx(mode)], 4); 277 } 278 atadev->mode = mode; 279 } 280 } 281