1 /*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* local prototypes */ 28 static int ata_ahci_ctlr_reset(device_t dev); 29 static int ata_ahci_status(device_t dev); 30 static int ata_ahci_begin_transaction(struct ata_request *request); 31 static int ata_ahci_end_transaction(struct ata_request *request); 32 static u_int32_t ata_ahci_softreset(device_t dev, int port); 33 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 34 static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request); 35 36 /* 37 * AHCI v1.x compliant SATA chipset support functions 38 */ 39 int 40 ata_ahci_ident(device_t dev) 41 { 42 struct ata_pci_controller *ctlr = device_get_softc(dev); 43 static const struct ata_chip_id id = {0, 0, 0, 0x00, ATA_SA300, "AHCI"}; 44 char buffer[64]; 45 46 /* is this a possible AHCI candidate ? */ 47 if (pci_get_class(dev) != PCIC_STORAGE || 48 pci_get_subclass(dev) != PCIS_STORAGE_SATA) 49 return ENXIO; 50 51 /* is this PCI device flagged as an AHCI compliant chip ? */ 52 if (pci_read_config(dev, PCIR_PROGIF, 1) != PCIP_STORAGE_SATA_AHCI_1_0) 53 return ENXIO; 54 55 if (bootverbose) 56 ksnprintf(buffer, sizeof(buffer), "%s (ID=%08x) AHCI controller", 57 ata_pcivendor2str(dev), pci_get_devid(dev)); 58 else 59 ksnprintf(buffer, sizeof(buffer), "%s AHCI controller", 60 ata_pcivendor2str(dev)); 61 device_set_desc_copy(dev, buffer); 62 ctlr->chip = &id; 63 ctlr->chipinit = ata_ahci_chipinit; 64 return 0; 65 } 66 67 /* 68 * AHCI v1.x compliant SATA chipset support functions 69 */ 70 static int 71 ata_ahci_chipinit(device_t dev) 72 { 73 struct ata_pci_controller *ctlr = device_get_softc(dev); 74 int error; 75 u_int32_t version; 76 77 /* if we have a memory BAR(5) we are likely on an AHCI part */ 78 ctlr->r_type2 = SYS_RES_MEMORY; 79 ctlr->r_rid2 = PCIR_BAR(5); 80 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 81 &ctlr->r_rid2, RF_ACTIVE))) 82 return ENXIO; 83 84 /* setup interrupt delivery if not done allready by a vendor driver */ 85 if (!ctlr->r_irq) { 86 if (ata_setup_interrupt(dev, ata_generic_intr)) { 87 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 88 return ENXIO; 89 } 90 } 91 else 92 device_printf(dev, "AHCI called from vendor specific driver\n"); 93 94 /* reset controller */ 95 if ((error = ata_ahci_ctlr_reset(dev)) != 0) { 96 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 97 return (error); 98 } 99 100 /* get the number of HW channels */ 101 ctlr->channels = 102 MAX(flsl(ATA_INL(ctlr->r_res2, ATA_AHCI_PI)), 103 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1); 104 105 ctlr->reset = ata_ahci_reset; 106 ctlr->dmainit = ata_ahci_dmainit; 107 ctlr->allocate = ata_ahci_allocate; 108 ctlr->setmode = ata_sata_setmode; 109 110 /* enable PCI interrupt */ 111 pci_write_config(dev, PCIR_COMMAND, 112 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 113 114 /* announce we support the HW */ 115 version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS); 116 device_printf(dev, 117 "AHCI Version %x%x.%x%x controller with %d ports detected\n", 118 (version >> 24) & 0xff, (version >> 16) & 0xff, 119 (version >> 8) & 0xff, version & 0xff, 120 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1); 121 return 0; 122 } 123 124 static int 125 ata_ahci_ctlr_reset(device_t dev) 126 { 127 struct ata_pci_controller *ctlr = device_get_softc(dev); 128 int timeout; 129 130 /* enable AHCI mode */ 131 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE); 132 133 /* reset AHCI controller */ 134 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE|ATA_AHCI_GHC_HR); 135 for (timeout = 1000; timeout > 0; timeout--) { 136 DELAY(1000); 137 if ((ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) == 0) 138 break; 139 } 140 if (timeout == 0) { 141 device_printf(dev, "AHCI controller reset failure\n"); 142 return ENXIO; 143 } 144 145 /* reenable AHCI mode */ 146 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE); 147 148 /* clear interrupts */ 149 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS)); 150 151 /* enable AHCI interrupts */ 152 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, 153 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE); 154 155 return 0; 156 } 157 158 static int 159 ata_ahci_allocate(device_t dev) 160 { 161 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 162 struct ata_channel *ch = device_get_softc(dev); 163 int offset = ch->unit << 7; 164 165 /* set the SATA resources */ 166 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 167 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset; 168 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 169 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset; 170 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 171 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset; 172 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 173 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset; 174 175 ch->hw.status = ata_ahci_status; 176 ch->hw.begin_transaction = ata_ahci_begin_transaction; 177 ch->hw.end_transaction = ata_ahci_end_transaction; 178 ch->hw.command = NULL; /* not used here */ 179 ch->hw.softreset = ata_ahci_softreset; 180 181 return 0; 182 } 183 184 static int 185 ata_ahci_status(device_t dev) 186 { 187 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 188 struct ata_channel *ch = device_get_softc(dev); 189 u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS); 190 int offset = ch->unit << 7; 191 192 #define ATA_AHCI_STATBITS \ 193 (ATA_AHCI_P_IX_IF|ATA_AHCI_P_IX_HBD|ATA_AHCI_P_IX_HBF|ATA_AHCI_P_IX_TFE) 194 195 if (action & (1 << ch->unit)) { 196 u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset); 197 u_int32_t cstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset); 198 199 /* clear interrupt(s) */ 200 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus); 201 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, 1 << ch->unit); 202 203 /* do we have any PHY events ? */ 204 if (istatus & (ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC)) 205 ata_sata_phy_check_events(dev); 206 207 /* do we have a potentially hanging engine to take care of? */ 208 if ((istatus & ATA_AHCI_STATBITS) && (cstatus & 1)) { 209 210 u_int32_t cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 211 int timeout = 0; 212 213 /* kill off all activity on this channel */ 214 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 215 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 216 217 /* XXX SOS this is not entirely wrong */ 218 do { 219 DELAY(1000); 220 if (timeout++ > 1000) { 221 device_printf(dev, "stopping AHCI engine failed\n"); 222 break; 223 } 224 } while (ATA_INL(ctlr->r_res2, 225 ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR); 226 227 /* start operations on this channel */ 228 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 229 cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 230 231 return 1; 232 } 233 else 234 return (!(cstatus & 1)); 235 } 236 return 0; 237 } 238 239 /* must be called with ATA channel locked and state_mtx held */ 240 static int 241 ata_ahci_begin_transaction(struct ata_request *request) 242 { 243 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 244 struct ata_channel *ch = device_get_softc(request->parent); 245 struct ata_device *atadev = device_get_softc(request->dev); 246 struct ata_ahci_cmd_tab *ctp; 247 struct ata_ahci_cmd_list *clp; 248 int offset = ch->unit << 7; 249 int port = atadev->unit & 0x0f; 250 int tag = 0, entries = 0; 251 int fis_size; 252 253 /* get a piece of the workspace for this request */ 254 ctp = (struct ata_ahci_cmd_tab *) 255 (ch->dma->work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE * tag)); 256 257 /* setup the FIS for this request */ 258 if (!(fis_size = ata_ahci_setup_fis(ctp, request))) { 259 device_printf(request->dev, "setting up SATA FIS failed\n"); 260 request->result = EIO; 261 return ATA_OP_FINISHED; 262 } 263 264 /* if request moves data setup and load SG list */ 265 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 266 if (ch->dma->load(ch->dev, request->data, request->bytecount, 267 request->flags & ATA_R_READ, 268 ctp->prd_tab, &entries)) { 269 device_printf(request->dev, "setting up DMA failed\n"); 270 request->result = EIO; 271 return ATA_OP_FINISHED; 272 } 273 } 274 275 /* setup the command list entry */ 276 clp = (struct ata_ahci_cmd_list *) 277 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag)); 278 279 clp->prd_length = entries; 280 clp->cmd_flags = (request->flags & ATA_R_WRITE ? ATA_AHCI_CMD_WRITE : 0) | 281 (request->flags & ATA_R_ATAPI ? 282 (ATA_AHCI_CMD_ATAPI | ATA_AHCI_CMD_PREFETCH) : 0) | 283 (fis_size / sizeof(u_int32_t)) | 284 (port << 12); 285 clp->bytecount = 0; 286 clp->cmd_table_phys = htole64(ch->dma->work_bus + ATA_AHCI_CT_OFFSET + 287 (ATA_AHCI_CT_SIZE * tag)); 288 289 /* clear eventual ACTIVE bit */ 290 ATA_IDX_OUTL(ch, ATA_SACTIVE, ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << tag)); 291 292 /* set command type bit */ 293 if (request->flags & ATA_R_ATAPI) 294 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 295 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) | 296 ATA_AHCI_P_CMD_ATAPI); 297 else 298 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 299 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & 300 ~ATA_AHCI_P_CMD_ATAPI); 301 302 /* set PM port to address */ 303 //ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBS + offset, (port << 8) | 0x00000001); 304 305 /* issue command to controller */ 306 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, (1 << tag)); 307 308 if (!(request->flags & ATA_R_ATAPI)) { 309 /* device reset doesn't interrupt */ 310 if (request->u.ata.command == ATA_DEVICE_RESET) { 311 u_int32_t tf_data; 312 int timeout = 1000000; 313 314 do { 315 DELAY(10); 316 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit<<7)); 317 } while ((tf_data & ATA_S_BUSY) && timeout--); 318 if (bootverbose) 319 device_printf(ch->dev, "device_reset timeout=%dus\n", 320 (1000000-timeout)*10); 321 request->status = tf_data; 322 if (request->status & ATA_S_ERROR) 323 request->error = tf_data >> 8; 324 return ATA_OP_FINISHED; 325 } 326 } 327 328 /* start the timeout */ 329 callout_reset(&request->callout, request->timeout * hz, 330 (timeout_t*)ata_timeout, request); 331 return ATA_OP_CONTINUES; 332 } 333 334 /* must be called with ATA channel locked and state_mtx held */ 335 static int 336 ata_ahci_end_transaction(struct ata_request *request) 337 { 338 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 339 struct ata_channel *ch = device_get_softc(request->parent); 340 struct ata_ahci_cmd_list *clp; 341 u_int32_t tf_data; 342 int offset = ch->unit << 7; 343 int tag = 0; 344 345 /* kill the timeout */ 346 callout_cancel(&request->callout); 347 348 /* get status */ 349 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset); 350 request->status = tf_data; 351 352 /* if error status get details */ 353 if (request->status & ATA_S_ERROR) 354 request->error = tf_data >> 8; 355 356 /* record how much data we actually moved */ 357 clp = (struct ata_ahci_cmd_list *) 358 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag)); 359 request->donecount = clp->bytecount; 360 361 /* release SG list etc */ 362 ch->dma->unload(ch->dev); 363 364 return ATA_OP_FINISHED; 365 } 366 367 static void 368 ata_ahci_restart(device_t dev) 369 { 370 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 371 struct ata_channel *ch = device_get_softc(dev); 372 u_int32_t cmd; 373 int offset = ch->unit << 7; 374 int timeout; 375 376 /* kill off all activity on this channel */ 377 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 378 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 379 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 380 381 /* XXX SOS this is not entirely wrong */ 382 timeout = 0; 383 do { 384 DELAY(1000); 385 if (timeout++ > 1000) { 386 device_printf(dev, "stopping AHCI engine failed\n"); 387 break; 388 } 389 } 390 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR); 391 392 /* issue Command List Override if supported */ 393 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_CLO) { 394 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 395 cmd |= ATA_AHCI_P_CMD_CLO; 396 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd); 397 timeout = 0; 398 do { 399 DELAY(1000); 400 if (timeout++ > 1000) { 401 device_printf(dev, "executing CLO failed\n"); 402 break; 403 } 404 } 405 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO); 406 } 407 408 /* clear SATA error register */ 409 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 410 411 /* clear any interrupts pending on this channel */ 412 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, 413 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset)); 414 415 /* start operations on this channel */ 416 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 417 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 418 cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 419 } 420 421 static u_int32_t 422 ata_ahci_softreset(device_t dev, int port __unused) 423 { 424 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 425 struct ata_channel *ch = device_get_softc(dev); 426 int offset = ch->unit << 7; 427 int timeout = 0; 428 uint32_t val; 429 430 #ifdef AHCI_PM 431 #endif 432 while ((val = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset)) & 433 (ATA_S_BUSY | ATA_S_DRQ)) { 434 DELAY(1000); 435 if (timeout++ > 1000) { 436 device_printf(dev, "port is not ready (timeout 1s) tfd = %08x\n", val); 437 break; 438 } 439 } 440 if (bootverbose) 441 device_printf(dev, "ready wait time=%dms\n", timeout); 442 443 return ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset); 444 } 445 446 static void 447 ata_ahci_reset(device_t dev) 448 { 449 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 450 struct ata_channel *ch = device_get_softc(dev); 451 u_int64_t work; 452 u_int32_t cmd, signature; 453 int offset = ch->unit << 7; 454 455 if (bootverbose) 456 device_printf(dev, "AHCI reset...\n"); 457 458 /* Disable port interrupts */ 459 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0); 460 461 if (!(ATA_INL(ctlr->r_res2, ATA_AHCI_PI) & (1 << ch->unit))) { 462 device_printf(dev, "port not implemented\n"); 463 return; 464 } 465 466 /* setup work areas */ 467 work = ch->dma->work_bus + ATA_AHCI_CL_OFFSET; 468 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff); 469 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32); 470 471 work = ch->dma->work_bus + ATA_AHCI_FB_OFFSET; 472 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff); 473 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32); 474 475 /* enable wanted port interrupts */ 476 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 477 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF | 478 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF | 479 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP | 480 ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS | 481 ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR)); 482 483 /* activate the channel and power/spin up device */ 484 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 485 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD)); 486 487 ata_ahci_restart(dev); 488 489 /* enable FIS based switching */ 490 //ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBS + offset, 0x00000003); 491 492 /* reset PHY and decide what is present */ 493 if (!ata_sata_phy_reset(dev)) { 494 if (bootverbose) 495 device_printf(dev, "AHCI reset done: phy reset found no device\n"); 496 ch->devices = 0; 497 498 /* kill off all activity on this channel */ 499 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 500 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 501 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 502 return; 503 } 504 505 signature = ata_ahci_softreset(dev, 0); 506 if (bootverbose) 507 device_printf(ch->dev, "SIGNATURE: %08x\n", signature); 508 509 switch (signature >> 16) { 510 case 0x0000: 511 ch->devices = ATA_ATA_MASTER; 512 break; 513 case 0x9669: 514 ch->devices = ATA_PORTMULTIPLIER; 515 device_printf(ch->dev, "Portmultipliers not supported yet\n"); 516 ch->devices = 0; 517 break; 518 case 0xeb14: 519 ch->devices = ATA_ATAPI_MASTER; 520 break; 521 default: /* SOS XXX */ 522 if (bootverbose) 523 device_printf(ch->dev, "Unknown signature, assuming disk device\n"); 524 ch->devices = ATA_ATA_MASTER; 525 } 526 if (bootverbose) 527 device_printf(dev, "AHCI reset done: devices=%08x\n", ch->devices); 528 } 529 530 static void 531 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 532 { 533 struct ata_dmasetprd_args *args = xsc; 534 struct ata_ahci_dma_prd *prd = args->dmatab; 535 int i; 536 537 if (!(args->error = error)) { 538 for (i = 0; i < nsegs; i++) { 539 prd[i].dba = htole64(segs[i].ds_addr); 540 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK); 541 } 542 } 543 544 KASSERT(nsegs <= ATA_AHCI_DMA_ENTRIES, ("too many DMA segment entries\n")); 545 args->nsegs = nsegs; 546 } 547 548 static void 549 ata_ahci_dmainit(device_t dev) 550 { 551 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 552 struct ata_channel *ch = device_get_softc(dev); 553 554 ata_dmainit(dev); 555 if (ch->dma) { 556 /* note start and stop are not used here */ 557 ch->dma->setprd = ata_ahci_dmasetprd; 558 ch->dma->max_iosize = (ATA_AHCI_DMA_ENTRIES - 1) * PAGE_SIZE; 559 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT) 560 ch->dma->max_address = BUS_SPACE_MAXADDR; 561 } 562 } 563 564 static int 565 ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request) 566 { 567 bzero(ctp->cfis, 64); 568 if (request->flags & ATA_R_ATAPI) { 569 bzero(ctp->acmd, 32); 570 bcopy(request->u.atapi.ccb, ctp->acmd, 16); 571 } 572 return ata_request2fis_h2d(request, &ctp->cfis[0]); 573 } 574