1a1917f14Szrj /*-
2a1917f14Szrj * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
3a1917f14Szrj * All rights reserved.
4a1917f14Szrj *
5a1917f14Szrj * Redistribution and use in source and binary forms, with or without
6a1917f14Szrj * modification, are permitted provided that the following conditions
7a1917f14Szrj * are met:
8a1917f14Szrj * 1. Redistributions of source code must retain the above copyright
9a1917f14Szrj * notice, this list of conditions and the following disclaimer,
10a1917f14Szrj * without modification, immediately at the beginning of the file.
11a1917f14Szrj * 2. Redistributions in binary form must reproduce the above copyright
12a1917f14Szrj * notice, this list of conditions and the following disclaimer in the
13a1917f14Szrj * documentation and/or other materials provided with the distribution.
14a1917f14Szrj *
15a1917f14Szrj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16a1917f14Szrj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17a1917f14Szrj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18a1917f14Szrj * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19a1917f14Szrj * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20a1917f14Szrj * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21a1917f14Szrj * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22a1917f14Szrj * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23a1917f14Szrj * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24a1917f14Szrj * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25a1917f14Szrj */
26a1917f14Szrj
27a1917f14Szrj /* local prototypes */
28a1917f14Szrj static int ata_amd_chipinit(device_t dev);
294b582042Szrj static void ata_amd_setmode(device_t dev, int mode);
30a1917f14Szrj
31853eb30dSzrj /* misc defines */
32853eb30dSzrj #define AMD_BUG 0x01
33853eb30dSzrj #define AMD_CABLE 0x02
34853eb30dSzrj
35a1917f14Szrj /*
36a1917f14Szrj * Advanced Micro Devices (AMD) chipset support functions
37a1917f14Szrj */
38a1917f14Szrj int
ata_amd_ident(device_t dev)39a1917f14Szrj ata_amd_ident(device_t dev)
40a1917f14Szrj {
41a1917f14Szrj struct ata_pci_controller *ctlr = device_get_softc(dev);
4259503772Szrj static const struct ata_chip_id ids[] =
43d0fd322fSzrj {{ ATA_AMD756, 0x00, 0x00, 0, ATA_UDMA4, "756" },
44853eb30dSzrj { ATA_AMD766, 0x00, AMD_CABLE|AMD_BUG, 0, ATA_UDMA5, "766" },
45853eb30dSzrj { ATA_AMD768, 0x00, AMD_CABLE, 0, ATA_UDMA5, "768" },
46853eb30dSzrj { ATA_AMD8111, 0x00, AMD_CABLE, 0, ATA_UDMA6, "8111" },
47*560012aaSzrj { ATA_AMD5536, 0x00, 0x00, 0, ATA_UDMA5, "CS5536" },
48a1917f14Szrj { 0, 0, 0, 0, 0, 0}};
49a1917f14Szrj
5059503772Szrj if (pci_get_vendor(dev) != ATA_AMD_ID)
51a1917f14Szrj return ENXIO;
52a1917f14Szrj
5359503772Szrj if (!(ctlr->chip = ata_match_chip(dev, ids)))
5459503772Szrj return ENXIO;
5559503772Szrj
5659503772Szrj ata_set_desc(dev);
57a1917f14Szrj ctlr->chipinit = ata_amd_chipinit;
58a1917f14Szrj return 0;
59a1917f14Szrj }
60a1917f14Szrj
61a1917f14Szrj static int
ata_amd_chipinit(device_t dev)62a1917f14Szrj ata_amd_chipinit(device_t dev)
63a1917f14Szrj {
64a1917f14Szrj struct ata_pci_controller *ctlr = device_get_softc(dev);
65a1917f14Szrj
6643156ad7Szrj if (ata_setup_interrupt(dev, ata_generic_intr))
67a1917f14Szrj return ENXIO;
68a1917f14Szrj
69a1917f14Szrj /* disable/set prefetch, postwrite */
70853eb30dSzrj if (ctlr->chip->cfg1 & AMD_BUG)
71a1917f14Szrj pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1);
72a1917f14Szrj else
73a1917f14Szrj pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
74a1917f14Szrj
754b582042Szrj ctlr->setmode = ata_amd_setmode;
76a1917f14Szrj return 0;
77a1917f14Szrj }
784b582042Szrj
794b582042Szrj static void
ata_amd_setmode(device_t dev,int mode)804b582042Szrj ata_amd_setmode(device_t dev, int mode)
814b582042Szrj {
824b582042Szrj device_t gparent = GRANDPARENT(dev);
834b582042Szrj struct ata_pci_controller *ctlr = device_get_softc(gparent);
844b582042Szrj struct ata_channel *ch = device_get_softc(device_get_parent(dev));
854b582042Szrj struct ata_device *atadev = device_get_softc(dev);
862458a87aSzrj int devno = (ch->unit << 1) + atadev->unit;
8759503772Szrj static const uint8_t timings[] =
8859503772Szrj { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
8959503772Szrj 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
9059503772Szrj static const uint8_t modes[] =
9159503772Szrj { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 };
924b582042Szrj int reg = 0x53 - devno;
934b582042Szrj int error;
944b582042Szrj
954b582042Szrj mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
964b582042Szrj
97853eb30dSzrj if (ctlr->chip->cfg1 & AMD_CABLE) {
984b582042Szrj if (mode > ATA_UDMA2 &&
994b582042Szrj !(pci_read_config(gparent, 0x42, 1) & (1 << devno))) {
1004b582042Szrj ata_print_cable(dev, "controller");
1014b582042Szrj mode = ATA_UDMA2;
1024b582042Szrj }
1034b582042Szrj }
1044b582042Szrj else
1054b582042Szrj mode = ata_check_80pin(dev, mode);
1064b582042Szrj
1074b582042Szrj error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1084b582042Szrj if (bootverbose)
1094b582042Szrj device_printf(dev, "%ssetting %s on %s chip\n",
1104b582042Szrj (error) ? "FAILURE " : "", ata_mode2str(mode),
1114b582042Szrj ctlr->chip->text);
1124b582042Szrj if (!error) {
1134b582042Szrj pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1);
1144b582042Szrj if (mode >= ATA_UDMA0)
1154b582042Szrj pci_write_config(gparent, reg, modes[mode & ATA_MODE_MASK], 1);
1164b582042Szrj else
1174b582042Szrj pci_write_config(gparent, reg, 0x8b, 1);
1184b582042Szrj atadev->mode = mode;
1194b582042Szrj }
1204b582042Szrj }
121