1 /*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* local prototypes */ 28 static int ata_ite_chipinit(device_t dev); 29 static void ata_ite_821x_setmode(device_t dev, int mode); 30 static void ata_ite_8213_setmode(device_t dev, int mode); 31 32 /* 33 * Integrated Technology Express Inc. (ITE) chipset support functions 34 */ 35 int 36 ata_ite_ident(device_t dev) 37 { 38 struct ata_pci_controller *ctlr = device_get_softc(dev); 39 static const struct ata_chip_id ids[] = 40 {{ ATA_IT8213F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8213F" }, 41 { ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" }, 42 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" }, 43 { 0, 0, 0, 0, 0, 0}}; 44 45 if (pci_get_vendor(dev) != ATA_ITE_ID) 46 return ENXIO; 47 48 if (!(ctlr->chip = ata_match_chip(dev, ids))) 49 return ENXIO; 50 51 ata_set_desc(dev); 52 ctlr->chipinit = ata_ite_chipinit; 53 return 0; 54 } 55 56 static int 57 ata_ite_chipinit(device_t dev) 58 { 59 struct ata_pci_controller *ctlr = device_get_softc(dev); 60 61 if (ata_setup_interrupt(dev, ata_generic_intr)) 62 return ENXIO; 63 64 if (ctlr->chip->chipid == ATA_IT8213F) { 65 /* the ITE 8213F only has one channel */ 66 ctlr->channels = 1; 67 68 ctlr->setmode = ata_ite_8213_setmode; 69 } 70 else { 71 /* set PCI mode and 66Mhz reference clock */ 72 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1); 73 74 /* set default active & recover timings */ 75 pci_write_config(dev, 0x54, 0x31, 1); 76 pci_write_config(dev, 0x56, 0x31, 1); 77 78 ctlr->setmode = ata_ite_821x_setmode; 79 } 80 81 return 0; 82 } 83 84 static void 85 ata_ite_821x_setmode(device_t dev, int mode) 86 { 87 device_t gparent = GRANDPARENT(dev); 88 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 89 struct ata_device *atadev = device_get_softc(dev); 90 int devno = (ch->unit << 1) + atadev->unit; 91 int error; 92 static const uint8_t udmatiming[] = 93 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 }; 94 static const uint8_t chtiming[] = 95 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 }; 96 97 /* correct the mode for what the HW supports */ 98 mode = ata_limit_mode(dev, mode, ATA_UDMA6); 99 100 /* check the CBLID bits for 80 conductor cable detection */ 101 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x40, 2) & 102 (ch->unit ? (1<<3) : (1<<2)))) { 103 ata_print_cable(dev, "controller"); 104 mode = ATA_UDMA2; 105 } 106 107 /* set the wanted mode on the device */ 108 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 109 110 if (bootverbose) 111 device_printf(dev, "%s setting %s on ITE8212F chip\n", 112 (error) ? "failed" : "success", ata_mode2str(mode)); 113 114 /* if the device accepted the mode change, setup the HW accordingly */ 115 if (!error) { 116 if (mode >= ATA_UDMA0) { 117 /* enable UDMA mode */ 118 pci_write_config(gparent, 0x50, 119 pci_read_config(gparent, 0x50, 1) & 120 ~(1 << (devno + 3)), 1); 121 122 /* set UDMA timing */ 123 pci_write_config(gparent, 124 0x56 + (ch->unit << 2) + atadev->unit, 125 udmatiming[mode & ATA_MODE_MASK], 1); 126 } 127 else { 128 /* disable UDMA mode */ 129 pci_write_config(gparent, 0x50, 130 pci_read_config(gparent, 0x50, 1) | 131 (1 << (devno + 3)), 1); 132 133 /* set active and recover timing (shared between master & slave) */ 134 if (pci_read_config(gparent, 0x54 + (ch->unit << 2), 1) < 135 chtiming[ata_mode2idx(mode)]) 136 pci_write_config(gparent, 0x54 + (ch->unit << 2), 137 chtiming[ata_mode2idx(mode)], 1); 138 } 139 atadev->mode = mode; 140 } 141 } 142 143 static void 144 ata_ite_8213_setmode(device_t dev, int mode) 145 { 146 device_t gparent = GRANDPARENT(dev); 147 struct ata_pci_controller *ctlr = device_get_softc(gparent); 148 struct ata_device *atadev = device_get_softc(dev); 149 u_int16_t reg40 = pci_read_config(gparent, 0x40, 2); 150 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1); 151 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1); 152 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2); 153 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2); 154 u_int16_t mask40 = 0, new40 = 0; 155 u_int8_t mask44 = 0, new44 = 0; 156 int devno = atadev->unit; 157 int error; 158 static const uint8_t timings[] = 159 { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23, 160 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 }; 161 static const uint8_t utimings[] = 162 { 0x00, 0x01, 0x10, 0x01, 0x10, 0x01, 0x10 }; 163 164 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 165 166 if (mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) { 167 ata_print_cable(dev, "controller"); 168 mode = ATA_UDMA2; 169 } 170 171 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 172 173 if (bootverbose) 174 device_printf(dev, "%s setting %s on %s chip\n", 175 (error) ? "FAILURE" : "", 176 ata_mode2str(mode), ctlr->chip->text); 177 if (!error) { 178 if (mode >= ATA_UDMA0) { 179 pci_write_config(gparent, 0x48, reg48 | (0x0001 << devno), 2); 180 pci_write_config(gparent, 0x4a, 181 (reg4a & ~(0x3 << (devno << 2))) | 182 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2); 183 } 184 else { 185 pci_write_config(gparent, 0x48, reg48 & ~(0x0001 << devno), 2); 186 pci_write_config(gparent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2); 187 } 188 if (mode >= ATA_UDMA2) 189 reg54 |= (0x1 << devno); 190 else 191 reg54 &= ~(0x1 << devno); 192 if (mode >= ATA_UDMA5) 193 reg54 |= (0x1000 << devno); 194 else 195 reg54 &= ~(0x1000 << devno); 196 pci_write_config(gparent, 0x54, reg54, 2); 197 198 reg40 &= 0xff00; 199 reg40 |= 0x4033; 200 if (atadev->unit == ATA_MASTER) { 201 reg40 |= (ata_atapi(dev) ? 0x04 : 0x00); 202 mask40 = 0x3300; 203 new40 = timings[ata_mode2idx(mode)] << 8; 204 } 205 else { 206 reg40 |= (ata_atapi(dev) ? 0x40 : 0x00); 207 mask44 = 0x0f; 208 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) | 209 (timings[ata_mode2idx(mode)] & 0x03); 210 } 211 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4); 212 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1); 213 214 atadev->mode = mode; 215 } 216 } 217