1a1917f14Szrj /*- 2a1917f14Szrj * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3a1917f14Szrj * All rights reserved. 4a1917f14Szrj * 5a1917f14Szrj * Redistribution and use in source and binary forms, with or without 6a1917f14Szrj * modification, are permitted provided that the following conditions 7a1917f14Szrj * are met: 8a1917f14Szrj * 1. Redistributions of source code must retain the above copyright 9a1917f14Szrj * notice, this list of conditions and the following disclaimer, 10a1917f14Szrj * without modification, immediately at the beginning of the file. 11a1917f14Szrj * 2. Redistributions in binary form must reproduce the above copyright 12a1917f14Szrj * notice, this list of conditions and the following disclaimer in the 13a1917f14Szrj * documentation and/or other materials provided with the distribution. 14a1917f14Szrj * 15a1917f14Szrj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16a1917f14Szrj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17a1917f14Szrj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18a1917f14Szrj * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19a1917f14Szrj * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20a1917f14Szrj * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21a1917f14Szrj * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22a1917f14Szrj * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23a1917f14Szrj * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24a1917f14Szrj * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25a1917f14Szrj */ 26a1917f14Szrj 27a1917f14Szrj /* local prototypes */ 28a1917f14Szrj static int ata_marvell_pata_chipinit(device_t dev); 29a1917f14Szrj static int ata_marvell_pata_allocate(device_t dev); 30a1917f14Szrj static void ata_marvell_pata_setmode(device_t dev, int mode); 31a1917f14Szrj static int ata_marvell_edma_chipinit(device_t dev); 32a1917f14Szrj static int ata_marvell_edma_allocate(device_t dev); 33a1917f14Szrj static int ata_marvell_edma_status(device_t dev); 34a1917f14Szrj static int ata_marvell_edma_begin_transaction(struct ata_request *request); 35a1917f14Szrj static int ata_marvell_edma_end_transaction(struct ata_request *request); 36a1917f14Szrj static void ata_marvell_edma_reset(device_t dev); 37a1917f14Szrj static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 38a1917f14Szrj static void ata_marvell_edma_dmainit(device_t dev); 39a1917f14Szrj 40*853eb30dSzrj /* misc defines */ 41*853eb30dSzrj #define MV_50XX 50 42*853eb30dSzrj #define MV_60XX 60 43*853eb30dSzrj #define MV_61XX 61 44*853eb30dSzrj 45a1917f14Szrj #define ATA_MV_HOST_BASE(ch) \ 46a1917f14Szrj ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000) 47a1917f14Szrj #define ATA_MV_EDMA_BASE(ch) \ 48a1917f14Szrj ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000) 49a1917f14Szrj 50a1917f14Szrj struct ata_marvell_response { 51a1917f14Szrj u_int16_t tag; 52a1917f14Szrj u_int8_t edma_status; 53a1917f14Szrj u_int8_t dev_status; 54a1917f14Szrj u_int32_t timestamp; 55a1917f14Szrj }; 56a1917f14Szrj 57a1917f14Szrj struct ata_marvell_dma_prdentry { 58a1917f14Szrj u_int32_t addrlo; 59a1917f14Szrj u_int32_t count; 60a1917f14Szrj u_int32_t addrhi; 61a1917f14Szrj u_int32_t reserved; 62a1917f14Szrj }; 63a1917f14Szrj 64a1917f14Szrj /* 65a1917f14Szrj * Marvell chipset support functions 66a1917f14Szrj */ 67a1917f14Szrj int 68a1917f14Szrj ata_marvell_ident(device_t dev) 69a1917f14Szrj { 70a1917f14Szrj struct ata_pci_controller *ctlr = device_get_softc(dev); 71a1917f14Szrj struct ata_chip_id *idx; 72a1917f14Szrj static struct ata_chip_id ids[] = 73*853eb30dSzrj {{ ATA_M88SX5040, 0, 4, MV_50XX, ATA_SA150, "88SX5040" }, 74*853eb30dSzrj { ATA_M88SX5041, 0, 4, MV_50XX, ATA_SA150, "88SX5041" }, 75*853eb30dSzrj { ATA_M88SX5080, 0, 8, MV_50XX, ATA_SA150, "88SX5080" }, 76*853eb30dSzrj { ATA_M88SX5081, 0, 8, MV_50XX, ATA_SA150, "88SX5081" }, 77*853eb30dSzrj { ATA_M88SX6041, 0, 4, MV_60XX, ATA_SA300, "88SX6041" }, 78*853eb30dSzrj { ATA_M88SX6081, 0, 8, MV_60XX, ATA_SA300, "88SX6081" }, 79*853eb30dSzrj { ATA_M88SX6101, 0, 1, MV_61XX, ATA_UDMA6, "88SX6101" }, 80*853eb30dSzrj { ATA_M88SX6145, 0, 2, MV_61XX, ATA_UDMA6, "88SX6145" }, 81a1917f14Szrj { 0, 0, 0, 0, 0, 0}}; 82a1917f14Szrj char buffer[64]; 83a1917f14Szrj 84a1917f14Szrj if (!(idx = ata_match_chip(dev, ids))) 85a1917f14Szrj return ENXIO; 86a1917f14Szrj 87a1917f14Szrj ksprintf(buffer, "Marvell %s %s controller", 88a1917f14Szrj idx->text, ata_mode2str(idx->max_dma)); 89a1917f14Szrj device_set_desc_copy(dev, buffer); 90a1917f14Szrj ctlr->chip = idx; 91a1917f14Szrj switch (ctlr->chip->cfg2) { 92*853eb30dSzrj case MV_50XX: 93*853eb30dSzrj case MV_60XX: 94a1917f14Szrj ctlr->chipinit = ata_marvell_edma_chipinit; 95a1917f14Szrj break; 96*853eb30dSzrj case MV_61XX: 97a1917f14Szrj ctlr->chipinit = ata_marvell_pata_chipinit; 98a1917f14Szrj break; 99a1917f14Szrj } 100a1917f14Szrj return 0; 101a1917f14Szrj } 102a1917f14Szrj 103a1917f14Szrj static int 104a1917f14Szrj ata_marvell_pata_chipinit(device_t dev) 105a1917f14Szrj { 106a1917f14Szrj struct ata_pci_controller *ctlr = device_get_softc(dev); 107a1917f14Szrj 108a1917f14Szrj if (ata_setup_interrupt(dev)) 109a1917f14Szrj return ENXIO; 110a1917f14Szrj 111a1917f14Szrj ctlr->allocate = ata_marvell_pata_allocate; 112a1917f14Szrj ctlr->setmode = ata_marvell_pata_setmode; 113a1917f14Szrj ctlr->channels = ctlr->chip->cfg1; 114a1917f14Szrj return 0; 115a1917f14Szrj } 116a1917f14Szrj 117a1917f14Szrj static int 118a1917f14Szrj ata_marvell_pata_allocate(device_t dev) 119a1917f14Szrj { 120a1917f14Szrj struct ata_channel *ch = device_get_softc(dev); 121a1917f14Szrj 122a1917f14Szrj /* setup the usual register normal pci style */ 123a1917f14Szrj if (ata_pci_allocate(dev)) 124a1917f14Szrj return ENXIO; 125a1917f14Szrj 126a1917f14Szrj /* dont use 32 bit PIO transfers */ 127a1917f14Szrj ch->flags |= ATA_USE_16BIT; 128a1917f14Szrj 129a1917f14Szrj return 0; 130a1917f14Szrj } 131a1917f14Szrj 132a1917f14Szrj static void 133a1917f14Szrj ata_marvell_pata_setmode(device_t dev, int mode) 134a1917f14Szrj { 135a1917f14Szrj device_t gparent = GRANDPARENT(dev); 136a1917f14Szrj struct ata_pci_controller *ctlr = device_get_softc(gparent); 137a1917f14Szrj struct ata_device *atadev = device_get_softc(dev); 138a1917f14Szrj 139a1917f14Szrj mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 140a1917f14Szrj mode = ata_check_80pin(dev, mode); 141a1917f14Szrj if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 142a1917f14Szrj atadev->mode = mode; 143a1917f14Szrj } 144a1917f14Szrj 145a1917f14Szrj static int 146a1917f14Szrj ata_marvell_edma_chipinit(device_t dev) 147a1917f14Szrj { 148a1917f14Szrj struct ata_pci_controller *ctlr = device_get_softc(dev); 149a1917f14Szrj 150a1917f14Szrj if (ata_setup_interrupt(dev)) 151a1917f14Szrj return ENXIO; 152a1917f14Szrj 153a1917f14Szrj ctlr->r_type1 = SYS_RES_MEMORY; 154a1917f14Szrj ctlr->r_rid1 = PCIR_BAR(0); 155a1917f14Szrj if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 156a1917f14Szrj &ctlr->r_rid1, RF_ACTIVE))) { 157a1917f14Szrj ata_teardown_interrupt(dev); 158a1917f14Szrj return ENXIO; 159a1917f14Szrj } 160a1917f14Szrj 161a1917f14Szrj /* mask all host controller interrupts */ 162a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000); 163a1917f14Szrj 164a1917f14Szrj /* mask all PCI interrupts */ 165a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000); 166a1917f14Szrj 167a1917f14Szrj ctlr->allocate = ata_marvell_edma_allocate; 168a1917f14Szrj ctlr->reset = ata_marvell_edma_reset; 169a1917f14Szrj ctlr->dmainit = ata_marvell_edma_dmainit; 170a1917f14Szrj ctlr->setmode = ata_sata_setmode; 171a1917f14Szrj ctlr->channels = ctlr->chip->cfg1; 172a1917f14Szrj 173a1917f14Szrj /* clear host controller interrupts */ 174a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000); 175a1917f14Szrj if (ctlr->chip->cfg1 > 4) 176a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000); 177a1917f14Szrj 178a1917f14Szrj /* clear PCI interrupts */ 179a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000); 180a1917f14Szrj 181a1917f14Szrj /* unmask PCI interrupts we want */ 182a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff); 183a1917f14Szrj 184a1917f14Szrj /* unmask host controller interrupts we want */ 185a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ | 186a1917f14Szrj /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25)); 187a1917f14Szrj 188a1917f14Szrj /* enable PCI interrupt */ 189a1917f14Szrj pci_write_config(dev, PCIR_COMMAND, 190a1917f14Szrj pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 191a1917f14Szrj return 0; 192a1917f14Szrj } 193a1917f14Szrj 194a1917f14Szrj static int 195a1917f14Szrj ata_marvell_edma_allocate(device_t dev) 196a1917f14Szrj { 197a1917f14Szrj struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 198a1917f14Szrj struct ata_channel *ch = device_get_softc(dev); 199a1917f14Szrj u_int64_t work = ch->dma->work_bus; 200a1917f14Szrj int i; 201a1917f14Szrj 202a1917f14Szrj /* clear work area */ 203a1917f14Szrj bzero(ch->dma->work, 1024+256); 204a1917f14Szrj 205a1917f14Szrj /* set legacy ATA resources */ 206a1917f14Szrj for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 207a1917f14Szrj ch->r_io[i].res = ctlr->r_res1; 208a1917f14Szrj ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch); 209a1917f14Szrj } 210a1917f14Szrj ch->r_io[ATA_CONTROL].res = ctlr->r_res1; 211a1917f14Szrj ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch); 212a1917f14Szrj ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1; 213a1917f14Szrj ata_default_registers(dev); 214a1917f14Szrj 215a1917f14Szrj /* set SATA resources */ 216a1917f14Szrj switch (ctlr->chip->cfg2) { 217*853eb30dSzrj case MV_50XX: 218a1917f14Szrj ch->r_io[ATA_SSTATUS].res = ctlr->r_res1; 219a1917f14Szrj ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch); 220a1917f14Szrj ch->r_io[ATA_SERROR].res = ctlr->r_res1; 221a1917f14Szrj ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch); 222a1917f14Szrj ch->r_io[ATA_SCONTROL].res = ctlr->r_res1; 223a1917f14Szrj ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch); 224a1917f14Szrj break; 225*853eb30dSzrj case MV_60XX: 226a1917f14Szrj ch->r_io[ATA_SSTATUS].res = ctlr->r_res1; 227a1917f14Szrj ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch); 228a1917f14Szrj ch->r_io[ATA_SERROR].res = ctlr->r_res1; 229a1917f14Szrj ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch); 230a1917f14Szrj ch->r_io[ATA_SCONTROL].res = ctlr->r_res1; 231a1917f14Szrj ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch); 232a1917f14Szrj ch->r_io[ATA_SACTIVE].res = ctlr->r_res1; 233a1917f14Szrj ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch); 234a1917f14Szrj break; 235a1917f14Szrj } 236a1917f14Szrj 237a1917f14Szrj ch->flags |= ATA_NO_SLAVE; 238a1917f14Szrj ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */ 239a1917f14Szrj ata_generic_hw(dev); 240a1917f14Szrj ch->hw.begin_transaction = ata_marvell_edma_begin_transaction; 241a1917f14Szrj ch->hw.end_transaction = ata_marvell_edma_end_transaction; 242a1917f14Szrj ch->hw.status = ata_marvell_edma_status; 243a1917f14Szrj 244a1917f14Szrj /* disable the EDMA machinery */ 245a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 246a1917f14Szrj DELAY(100000); /* SOS should poll for disabled */ 247a1917f14Szrj 248a1917f14Szrj /* set configuration to non-queued 128b read transfers stop on error */ 249a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13)); 250a1917f14Szrj 251a1917f14Szrj /* request queue base high */ 252a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32); 253a1917f14Szrj 254a1917f14Szrj /* request queue in ptr */ 255a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff); 256a1917f14Szrj 257a1917f14Szrj /* request queue out ptr */ 258a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0); 259a1917f14Szrj 260a1917f14Szrj /* response queue base high */ 261a1917f14Szrj work += 1024; 262a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32); 263a1917f14Szrj 264a1917f14Szrj /* response queue in ptr */ 265a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0); 266a1917f14Szrj 267a1917f14Szrj /* response queue out ptr */ 268a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff); 269a1917f14Szrj 270a1917f14Szrj /* clear SATA error register */ 271a1917f14Szrj ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 272a1917f14Szrj 273a1917f14Szrj /* clear any outstanding error interrupts */ 274a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 275a1917f14Szrj 276a1917f14Szrj /* unmask all error interrupts */ 277a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0); 278a1917f14Szrj 279a1917f14Szrj /* enable EDMA machinery */ 280a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 281a1917f14Szrj return 0; 282a1917f14Szrj } 283a1917f14Szrj 284a1917f14Szrj static int 285a1917f14Szrj ata_marvell_edma_status(device_t dev) 286a1917f14Szrj { 287a1917f14Szrj struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 288a1917f14Szrj struct ata_channel *ch = device_get_softc(dev); 289a1917f14Szrj u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60); 290a1917f14Szrj int shift = (ch->unit << 1) + (ch->unit > 3); 291a1917f14Szrj 292a1917f14Szrj if (cause & (1 << shift)) { 293a1917f14Szrj 294a1917f14Szrj /* clear interrupt(s) */ 295a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 296a1917f14Szrj 297a1917f14Szrj /* do we have any PHY events ? */ 298a1917f14Szrj ata_sata_phy_check_events(dev); 299a1917f14Szrj } 300a1917f14Szrj 301a1917f14Szrj /* do we have any device action ? */ 302a1917f14Szrj return (cause & (2 << shift)); 303a1917f14Szrj } 304a1917f14Szrj 305a1917f14Szrj /* must be called with ATA channel locked and state_mtx held */ 306a1917f14Szrj static int 307a1917f14Szrj ata_marvell_edma_begin_transaction(struct ata_request *request) 308a1917f14Szrj { 309a1917f14Szrj struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 310a1917f14Szrj struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 311a1917f14Szrj u_int32_t req_in; 312a1917f14Szrj u_int8_t *bytep; 313a1917f14Szrj u_int16_t *wordp; 314a1917f14Szrj u_int32_t *quadp; 315a1917f14Szrj int i, tag = 0x07; 316a1917f14Szrj int dummy, error, slot; 317a1917f14Szrj 318a1917f14Szrj /* only DMA R/W goes through the EMDA machine */ 319a1917f14Szrj if (request->u.ata.command != ATA_READ_DMA && 320a1917f14Szrj request->u.ata.command != ATA_WRITE_DMA) { 321a1917f14Szrj 322a1917f14Szrj /* disable the EDMA machinery */ 323a1917f14Szrj if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001) 324a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 325a1917f14Szrj return ata_begin_transaction(request); 326a1917f14Szrj } 327a1917f14Szrj 328a1917f14Szrj /* check for 48 bit access and convert if needed */ 329a1917f14Szrj ata_modify_if_48bit(request); 330a1917f14Szrj 331a1917f14Szrj /* check sanity, setup SG list and DMA engine */ 332a1917f14Szrj if ((error = ch->dma->load(ch->dev, request->data, request->bytecount, 333a1917f14Szrj request->flags & ATA_R_READ, ch->dma->sg, 334a1917f14Szrj &dummy))) { 335a1917f14Szrj device_printf(request->dev, "setting up DMA failed\n"); 336a1917f14Szrj request->result = error; 337a1917f14Szrj return ATA_OP_FINISHED; 338a1917f14Szrj } 339a1917f14Szrj 340a1917f14Szrj /* get next free request queue slot */ 341a1917f14Szrj req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch)); 342a1917f14Szrj slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f; 343a1917f14Szrj bytep = (u_int8_t *)(ch->dma->work); 344a1917f14Szrj bytep += (slot << 5); 345a1917f14Szrj wordp = (u_int16_t *)bytep; 346a1917f14Szrj quadp = (u_int32_t *)bytep; 347a1917f14Szrj 348a1917f14Szrj /* fill in this request */ 349a1917f14Szrj quadp[0] = (long)ch->dma->sg_bus & 0xffffffff; 350a1917f14Szrj quadp[1] = (u_int64_t)ch->dma->sg_bus >> 32; 351a1917f14Szrj wordp[4] = (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag<<1); 352a1917f14Szrj 353a1917f14Szrj i = 10; 354a1917f14Szrj bytep[i++] = (request->u.ata.count >> 8) & 0xff; 355a1917f14Szrj bytep[i++] = 0x10 | ATA_COUNT; 356a1917f14Szrj bytep[i++] = request->u.ata.count & 0xff; 357a1917f14Szrj bytep[i++] = 0x10 | ATA_COUNT; 358a1917f14Szrj 359a1917f14Szrj bytep[i++] = (request->u.ata.lba >> 24) & 0xff; 360a1917f14Szrj bytep[i++] = 0x10 | ATA_SECTOR; 361a1917f14Szrj bytep[i++] = request->u.ata.lba & 0xff; 362a1917f14Szrj bytep[i++] = 0x10 | ATA_SECTOR; 363a1917f14Szrj 364a1917f14Szrj bytep[i++] = (request->u.ata.lba >> 32) & 0xff; 365a1917f14Szrj bytep[i++] = 0x10 | ATA_CYL_LSB; 366a1917f14Szrj bytep[i++] = (request->u.ata.lba >> 8) & 0xff; 367a1917f14Szrj bytep[i++] = 0x10 | ATA_CYL_LSB; 368a1917f14Szrj 369a1917f14Szrj bytep[i++] = (request->u.ata.lba >> 40) & 0xff; 370a1917f14Szrj bytep[i++] = 0x10 | ATA_CYL_MSB; 371a1917f14Szrj bytep[i++] = (request->u.ata.lba >> 16) & 0xff; 372a1917f14Szrj bytep[i++] = 0x10 | ATA_CYL_MSB; 373a1917f14Szrj 374a1917f14Szrj bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf); 375a1917f14Szrj bytep[i++] = 0x10 | ATA_DRIVE; 376a1917f14Szrj 377a1917f14Szrj bytep[i++] = request->u.ata.command; 378a1917f14Szrj bytep[i++] = 0x90 | ATA_COMMAND; 379a1917f14Szrj 380a1917f14Szrj /* enable EDMA machinery if needed */ 381a1917f14Szrj if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) { 382a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 383a1917f14Szrj while (!(ATA_INL(ctlr->r_res1, 384a1917f14Szrj 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) 385a1917f14Szrj DELAY(10); 386a1917f14Szrj } 387a1917f14Szrj 388a1917f14Szrj /* tell EDMA it has a new request */ 389a1917f14Szrj slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f; 390a1917f14Szrj req_in &= 0xfffffc00; 391a1917f14Szrj req_in += (slot << 5); 392a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in); 393a1917f14Szrj 394a1917f14Szrj return ATA_OP_CONTINUES; 395a1917f14Szrj } 396a1917f14Szrj 397a1917f14Szrj /* must be called with ATA channel locked and state_mtx held */ 398a1917f14Szrj static int 399a1917f14Szrj ata_marvell_edma_end_transaction(struct ata_request *request) 400a1917f14Szrj { 401a1917f14Szrj struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 402a1917f14Szrj struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 403a1917f14Szrj int offset = (ch->unit > 3 ? 0x30014 : 0x20014); 404a1917f14Szrj u_int32_t icr = ATA_INL(ctlr->r_res1, offset); 405a1917f14Szrj int res; 406a1917f14Szrj 407a1917f14Szrj /* EDMA interrupt */ 408a1917f14Szrj if ((icr & (0x0001 << (ch->unit & 3)))) { 409a1917f14Szrj struct ata_marvell_response *response; 410a1917f14Szrj u_int32_t rsp_in, rsp_out; 411a1917f14Szrj int slot; 412a1917f14Szrj 413a1917f14Szrj /* stop timeout */ 414a1917f14Szrj callout_stop_sync(&request->callout); 415a1917f14Szrj 416a1917f14Szrj /* get response ptr's */ 417a1917f14Szrj rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch)); 418a1917f14Szrj rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch)); 419a1917f14Szrj slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f; 420a1917f14Szrj rsp_out &= 0xffffff00; 421a1917f14Szrj rsp_out += (slot << 3); 422a1917f14Szrj response = (struct ata_marvell_response *) 423a1917f14Szrj (ch->dma->work + 1024 + (slot << 3)); 424a1917f14Szrj 425a1917f14Szrj /* record status for this request */ 426a1917f14Szrj request->status = response->dev_status; 427a1917f14Szrj request->error = 0; 428a1917f14Szrj 429a1917f14Szrj /* ack response */ 430a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out); 431a1917f14Szrj 432a1917f14Szrj /* update progress */ 433a1917f14Szrj if (!(request->status & ATA_S_ERROR) && 434a1917f14Szrj !(request->flags & ATA_R_TIMEOUT)) 435a1917f14Szrj request->donecount = request->bytecount; 436a1917f14Szrj 437a1917f14Szrj /* unload SG list */ 438a1917f14Szrj ch->dma->unload(ch->dev); 439a1917f14Szrj 440a1917f14Szrj res = ATA_OP_FINISHED; 441a1917f14Szrj } 442a1917f14Szrj 443a1917f14Szrj /* legacy ATA interrupt */ 444a1917f14Szrj else { 445a1917f14Szrj res = ata_end_transaction(request); 446a1917f14Szrj } 447a1917f14Szrj 448a1917f14Szrj /* ack interrupt */ 449a1917f14Szrj ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3)))); 450a1917f14Szrj return res; 451a1917f14Szrj } 452a1917f14Szrj 453a1917f14Szrj static void 454a1917f14Szrj ata_marvell_edma_reset(device_t dev) 455a1917f14Szrj { 456a1917f14Szrj struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 457a1917f14Szrj struct ata_channel *ch = device_get_softc(dev); 458a1917f14Szrj 459a1917f14Szrj /* disable the EDMA machinery */ 460a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 461a1917f14Szrj while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) 462a1917f14Szrj DELAY(10); 463a1917f14Szrj 464a1917f14Szrj /* clear SATA error register */ 465a1917f14Szrj ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 466a1917f14Szrj 467a1917f14Szrj /* clear any outstanding error interrupts */ 468a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 469a1917f14Szrj 470a1917f14Szrj /* unmask all error interrupts */ 471a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0); 472a1917f14Szrj 473a1917f14Szrj /* enable channel and test for devices */ 474a1917f14Szrj if (ata_sata_phy_reset(dev)) 475a1917f14Szrj ata_generic_reset(dev); 476a1917f14Szrj 477a1917f14Szrj /* enable EDMA machinery */ 478a1917f14Szrj ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 479a1917f14Szrj } 480a1917f14Szrj 481a1917f14Szrj static void 482a1917f14Szrj ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, 483a1917f14Szrj int error) 484a1917f14Szrj { 485a1917f14Szrj struct ata_dmasetprd_args *args = xsc; 486a1917f14Szrj struct ata_marvell_dma_prdentry *prd = args->dmatab; 487a1917f14Szrj int i; 488a1917f14Szrj 489a1917f14Szrj if ((args->error = error)) 490a1917f14Szrj return; 491a1917f14Szrj 492a1917f14Szrj for (i = 0; i < nsegs; i++) { 493a1917f14Szrj prd[i].addrlo = htole32(segs[i].ds_addr); 494a1917f14Szrj prd[i].count = htole32(segs[i].ds_len); 495a1917f14Szrj prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32); 496a1917f14Szrj } 497a1917f14Szrj prd[i - 1].count |= htole32(ATA_DMA_EOT); 498a1917f14Szrj } 499a1917f14Szrj 500a1917f14Szrj static void 501a1917f14Szrj ata_marvell_edma_dmainit(device_t dev) 502a1917f14Szrj { 503a1917f14Szrj struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 504a1917f14Szrj struct ata_channel *ch = device_get_softc(dev); 505a1917f14Szrj 506a1917f14Szrj ata_dmainit(dev); 507a1917f14Szrj if (ch->dma) { 508a1917f14Szrj /* note start and stop are not used here */ 509a1917f14Szrj ch->dma->setprd = ata_marvell_edma_dmasetprd; 510a1917f14Szrj 511a1917f14Szrj if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004) 512a1917f14Szrj ch->dma->max_address = BUS_SPACE_MAXADDR; 513a1917f14Szrj 514a1917f14Szrj /* chip does not reliably do 64K DMA transfers */ 515a1917f14Szrj ch->dma->max_iosize = 126 * DEV_BSIZE; 516a1917f14Szrj } 517a1917f14Szrj } 518