1 /*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* local prototypes */ 28 static int ata_nvidia_chipinit(device_t dev); 29 static int ata_nvidia_allocate(device_t dev); 30 static int ata_nvidia_status(device_t dev); 31 static void ata_nvidia_reset(device_t dev); 32 static void ata_nvidia_setmode(device_t dev, int mode); 33 34 /* misc defines */ 35 #define NV4 0x01 36 #define NVQ 0x02 37 #define NVAHCI 0x04 38 39 /* 40 * nVidia chipset support functions 41 */ 42 int 43 ata_nvidia_ident(device_t dev) 44 { 45 struct ata_pci_controller *ctlr = device_get_softc(dev); 46 static const struct ata_chip_id ids[] = 47 {{ ATA_NFORCE1, 0, 0, 0, ATA_UDMA5, "nForce" }, 48 { ATA_NFORCE2, 0, 0, 0, ATA_UDMA6, "nForce2" }, 49 { ATA_NFORCE2_PRO, 0, 0, 0, ATA_UDMA6, "nForce2 Pro" }, 50 { ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" }, 51 { ATA_NFORCE3, 0, 0, 0, ATA_UDMA6, "nForce3" }, 52 { ATA_NFORCE3_PRO, 0, 0, 0, ATA_UDMA6, "nForce3 Pro" }, 53 { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 54 { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 55 { ATA_NFORCE_MCP04, 0, 0, 0, ATA_UDMA6, "nForce MCP" }, 56 { ATA_NFORCE_MCP04_S1, 0, NV4, 0, ATA_SA150, "nForce MCP" }, 57 { ATA_NFORCE_MCP04_S2, 0, NV4, 0, ATA_SA150, "nForce MCP" }, 58 { ATA_NFORCE_CK804, 0, 0, 0, ATA_UDMA6, "nForce CK804" }, 59 { ATA_NFORCE_CK804_S1, 0, NV4, 0, ATA_SA300, "nForce CK804" }, 60 { ATA_NFORCE_CK804_S2, 0, NV4, 0, ATA_SA300, "nForce CK804" }, 61 { ATA_NFORCE_MCP51, 0, 0, 0, ATA_UDMA6, "nForce MCP51" }, 62 { ATA_NFORCE_MCP51_S1, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP51" }, 63 { ATA_NFORCE_MCP51_S2, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP51" }, 64 { ATA_NFORCE_MCP55, 0, 0, 0, ATA_UDMA6, "nForce MCP55" }, 65 { ATA_NFORCE_MCP55_S1, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP55" }, 66 { ATA_NFORCE_MCP55_S2, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP55" }, 67 { ATA_NFORCE_MCP61, 0, 0, 0, ATA_UDMA6, "nForce MCP61" }, 68 { ATA_NFORCE_MCP61_S1, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP61" }, 69 { ATA_NFORCE_MCP61_S2, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP61" }, 70 { ATA_NFORCE_MCP61_S3, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP61" }, 71 { ATA_NFORCE_MCP65, 0, 0, 0, ATA_UDMA6, "nForce MCP65" }, 72 { ATA_NFORCE_MCP65_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 73 { ATA_NFORCE_MCP65_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 74 { ATA_NFORCE_MCP65_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 75 { ATA_NFORCE_MCP65_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 76 { ATA_NFORCE_MCP65_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 77 { ATA_NFORCE_MCP65_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 78 { ATA_NFORCE_MCP65_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 79 { ATA_NFORCE_MCP65_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP65" }, 80 { ATA_NFORCE_MCP67, 0, 0, 0, ATA_UDMA6, "nForce MCP67" }, 81 { ATA_NFORCE_MCP67_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 82 { ATA_NFORCE_MCP67_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 83 { ATA_NFORCE_MCP67_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 84 { ATA_NFORCE_MCP67_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 85 { ATA_NFORCE_MCP67_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 86 { ATA_NFORCE_MCP67_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 87 { ATA_NFORCE_MCP67_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 88 { ATA_NFORCE_MCP67_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 89 { ATA_NFORCE_MCP67_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 90 { ATA_NFORCE_MCP67_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 91 { ATA_NFORCE_MCP67_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 92 { ATA_NFORCE_MCP67_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 93 { ATA_NFORCE_MCP67_AC, 0, NVAHCI, 0, ATA_SA300, "nForce MCP67" }, 94 { ATA_NFORCE_MCP73, 0, 0, 0, ATA_UDMA6, "nForce MCP73" }, 95 { ATA_NFORCE_MCP73_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 96 { ATA_NFORCE_MCP73_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 97 { ATA_NFORCE_MCP73_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 98 { ATA_NFORCE_MCP73_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 99 { ATA_NFORCE_MCP73_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 100 { ATA_NFORCE_MCP73_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 101 { ATA_NFORCE_MCP73_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 102 { ATA_NFORCE_MCP73_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 103 { ATA_NFORCE_MCP73_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 104 { ATA_NFORCE_MCP73_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 105 { ATA_NFORCE_MCP73_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 106 { ATA_NFORCE_MCP73_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP73" }, 107 { ATA_NFORCE_MCP77, 0, 0, 0, ATA_UDMA6, "nForce MCP77" }, 108 { ATA_NFORCE_MCP77_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 109 { ATA_NFORCE_MCP77_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 110 { ATA_NFORCE_MCP77_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 111 { ATA_NFORCE_MCP77_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 112 { ATA_NFORCE_MCP77_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 113 { ATA_NFORCE_MCP77_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 114 { ATA_NFORCE_MCP77_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 115 { ATA_NFORCE_MCP77_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 116 { ATA_NFORCE_MCP77_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 117 { ATA_NFORCE_MCP77_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 118 { ATA_NFORCE_MCP77_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 119 { ATA_NFORCE_MCP77_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP77" }, 120 { ATA_NFORCE_MCP79_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 121 { ATA_NFORCE_MCP79_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 122 { ATA_NFORCE_MCP79_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 123 { ATA_NFORCE_MCP79_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 124 { ATA_NFORCE_MCP79_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 125 { ATA_NFORCE_MCP79_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 126 { ATA_NFORCE_MCP79_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 127 { ATA_NFORCE_MCP79_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 128 { ATA_NFORCE_MCP79_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 129 { ATA_NFORCE_MCP79_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 130 { ATA_NFORCE_MCP79_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 131 { ATA_NFORCE_MCP79_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP79" }, 132 { ATA_NFORCE_MCP89_A0, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 133 { ATA_NFORCE_MCP89_A1, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 134 { ATA_NFORCE_MCP89_A2, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 135 { ATA_NFORCE_MCP89_A3, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 136 { ATA_NFORCE_MCP89_A4, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 137 { ATA_NFORCE_MCP89_A5, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 138 { ATA_NFORCE_MCP89_A6, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 139 { ATA_NFORCE_MCP89_A7, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 140 { ATA_NFORCE_MCP89_A8, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 141 { ATA_NFORCE_MCP89_A9, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 142 { ATA_NFORCE_MCP89_AA, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 143 { ATA_NFORCE_MCP89_AB, 0, NVAHCI, 0, ATA_SA300, "nForce MCP89" }, 144 { 0, 0, 0, 0, 0, 0}} ; 145 146 if (pci_get_vendor(dev) != ATA_NVIDIA_ID) 147 return ENXIO; 148 149 if (!(ctlr->chip = ata_match_chip(dev, ids))) 150 return ENXIO; 151 152 ata_set_desc(dev); 153 if (ctlr->chip->cfg1 & NVAHCI) 154 ctlr->chipinit = ata_ahci_chipinit; 155 else 156 ctlr->chipinit = ata_nvidia_chipinit; 157 return 0; 158 } 159 160 static int 161 ata_nvidia_chipinit(device_t dev) 162 { 163 struct ata_pci_controller *ctlr = device_get_softc(dev); 164 165 if (ata_setup_interrupt(dev, ata_generic_intr)) 166 return ENXIO; 167 168 if (ctlr->chip->max_dma >= ATA_SA150) { 169 if (pci_read_config(dev, PCIR_BAR(5), 1) & 1) 170 ctlr->r_type2 = SYS_RES_IOPORT; 171 else 172 ctlr->r_type2 = SYS_RES_MEMORY; 173 ctlr->r_rid2 = PCIR_BAR(5); 174 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 175 &ctlr->r_rid2, RF_ACTIVE))) { 176 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010; 177 178 ctlr->allocate = ata_nvidia_allocate; 179 ctlr->reset = ata_nvidia_reset; 180 181 /* enable control access */ 182 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1); 183 /* MCP55 seems to need some time to allow r_res2 read. */ 184 DELAY(10); 185 if (ctlr->chip->cfg1 & NVQ) { 186 /* clear interrupt status */ 187 ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff); 188 189 /* enable device and PHY state change interrupts */ 190 ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d); 191 192 /* disable NCQ support */ 193 ATA_OUTL(ctlr->r_res2, 0x0400, 194 ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9); 195 } 196 else { 197 /* clear interrupt status */ 198 ATA_OUTB(ctlr->r_res2, offset, 0xff); 199 200 /* enable device and PHY state change interrupts */ 201 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd); 202 } 203 204 /* enable PCI interrupt */ 205 pci_write_config(dev, PCIR_COMMAND, 206 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 207 208 } 209 ctlr->setmode = ata_sata_setmode; 210 } 211 else { 212 /* disable prefetch, postwrite */ 213 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1); 214 ctlr->setmode = ata_nvidia_setmode; 215 } 216 return 0; 217 } 218 219 static int 220 ata_nvidia_allocate(device_t dev) 221 { 222 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 223 struct ata_channel *ch = device_get_softc(dev); 224 225 /* setup the usual register normal pci style */ 226 if (ata_pci_allocate(dev)) 227 return ENXIO; 228 229 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 230 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6); 231 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 232 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6); 233 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 234 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6); 235 236 ch->hw.status = ata_nvidia_status; 237 ch->flags |= ATA_NO_SLAVE; 238 239 return 0; 240 } 241 242 static int 243 ata_nvidia_status(device_t dev) 244 { 245 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 246 struct ata_channel *ch = device_get_softc(dev); 247 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010; 248 int shift = ch->unit << (ctlr->chip->cfg1 & NVQ ? 4 : 2); 249 u_int32_t istatus; 250 251 /* get interrupt status */ 252 if (ctlr->chip->cfg1 & NVQ) 253 istatus = ATA_INL(ctlr->r_res2, offset); 254 else 255 istatus = ATA_INB(ctlr->r_res2, offset); 256 257 /* do we have any PHY events ? */ 258 if (istatus & (0x0c << shift)) 259 ata_sata_phy_check_events(dev); 260 261 /* clear interrupt(s) */ 262 if (ctlr->chip->cfg1 & NVQ) 263 ATA_OUTL(ctlr->r_res2, offset, (0x0f << shift) | 0x00f000f0); 264 else 265 ATA_OUTB(ctlr->r_res2, offset, (0x0f << shift)); 266 267 /* do we have any device action ? */ 268 return (istatus & (0x01 << shift)); 269 } 270 271 static void 272 ata_nvidia_reset(device_t dev) 273 { 274 if (ata_sata_phy_reset(dev)) 275 ata_generic_reset(dev); 276 } 277 278 static void 279 ata_nvidia_setmode(device_t dev, int mode) 280 { 281 device_t gparent = GRANDPARENT(dev); 282 struct ata_pci_controller *ctlr = device_get_softc(gparent); 283 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 284 struct ata_device *atadev = device_get_softc(dev); 285 int devno = (ch->unit << 1) + atadev->unit; 286 int error; 287 static const uint8_t timings[] = 288 { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20, 289 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 290 static const uint8_t modes[] = 291 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }; 292 int reg = 0x63 - devno; 293 294 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 295 mode = ata_check_80pin(dev, mode); 296 297 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 298 if (bootverbose) 299 device_printf(dev, "%ssetting %s on %s chip\n", 300 (error) ? "FAILURE " : "", ata_mode2str(mode), 301 ctlr->chip->text); 302 if (!error) { 303 pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1); 304 if (mode >= ATA_UDMA0) 305 pci_write_config(gparent, reg, modes[mode & ATA_MODE_MASK], 1); 306 else 307 pci_write_config(gparent, reg, 0x8b, 1); 308 atadev->mode = mode; 309 } 310 } 311