1 /*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* local prototypes */ 28 static int ata_sis_chipinit(device_t dev); 29 static int ata_sis_allocate(device_t dev); 30 static void ata_sis_reset(device_t dev); 31 static void ata_sis_setmode(device_t dev, int mode); 32 33 /* misc defines */ 34 #define SIS_33 1 35 #define SIS_66 2 36 #define SIS_100NEW 3 37 #define SIS_100OLD 4 38 #define SIS_133NEW 5 39 #define SIS_133OLD 6 40 #define SIS_SATA 7 41 42 /* 43 * Silicon Integrated Systems Corp. (SiS) chipset support functions 44 */ 45 int 46 ata_sis_ident(device_t dev) 47 { 48 struct ata_pci_controller *ctlr = device_get_softc(dev); 49 const struct ata_chip_id *idx; 50 static const struct ata_chip_id ids[] = 51 {{ ATA_SIS182, 0x00, SIS_SATA, 0, ATA_SA150, "182" }, /* south */ 52 { ATA_SIS181, 0x00, SIS_SATA, 0, ATA_SA150, "181" }, /* south */ 53 { ATA_SIS180, 0x00, SIS_SATA, 0, ATA_SA150, "180" }, /* south */ 54 { ATA_SIS965, 0x00, SIS_133NEW, 0, ATA_UDMA6, "965" }, /* south */ 55 { ATA_SIS964, 0x00, SIS_133NEW, 0, ATA_UDMA6, "964" }, /* south */ 56 { ATA_SIS963, 0x00, SIS_133NEW, 0, ATA_UDMA6, "963" }, /* south */ 57 { ATA_SIS962, 0x00, SIS_133NEW, 0, ATA_UDMA6, "962" }, /* south */ 58 59 { ATA_SIS745, 0x00, SIS_100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */ 60 { ATA_SIS735, 0x00, SIS_100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */ 61 { ATA_SIS733, 0x00, SIS_100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */ 62 { ATA_SIS730, 0x00, SIS_100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */ 63 64 { ATA_SIS635, 0x00, SIS_100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */ 65 { ATA_SIS633, 0x00, SIS_100NEW, 0, ATA_UDMA5, "633" }, /* unknown */ 66 { ATA_SIS630, 0x30, SIS_100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */ 67 { ATA_SIS630, 0x00, SIS_66, 0, ATA_UDMA4, "630" }, /* 1chip */ 68 { ATA_SIS620, 0x00, SIS_66, 0, ATA_UDMA4, "620" }, /* 1chip */ 69 70 { ATA_SIS550, 0x00, SIS_66, 0, ATA_UDMA5, "550" }, 71 { ATA_SIS540, 0x00, SIS_66, 0, ATA_UDMA4, "540" }, 72 { ATA_SIS530, 0x00, SIS_66, 0, ATA_UDMA4, "530" }, 73 74 { ATA_SIS5513, 0xc2, SIS_33, 1, ATA_UDMA2, "5513" }, 75 { ATA_SIS5513, 0x00, SIS_33, 1, ATA_WDMA2, "5513" }, 76 { 0, 0, 0, 0, 0, 0 }}; 77 static struct ata_chip_id id[] = 78 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }}; 79 char buffer[64]; 80 int found = 0; 81 82 if (pci_get_class(dev) != PCIC_STORAGE) 83 return (ENXIO); 84 85 if (pci_get_vendor(dev) != ATA_SIS_ID) 86 return ENXIO; 87 88 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev)))) 89 return ENXIO; 90 91 if (idx->cfg2 && !found) { 92 u_int8_t reg57 = pci_read_config(dev, 0x57, 1); 93 94 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1); 95 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) { 96 found = 1; 97 memcpy(&id[0], idx, sizeof(id[0])); 98 id[0].cfg1 = SIS_133NEW; 99 id[0].max_dma = ATA_UDMA6; 100 ksprintf(buffer, "SiS 962/963 %s controller", 101 ata_mode2str(idx->max_dma)); 102 } 103 pci_write_config(dev, 0x57, reg57, 1); 104 } 105 if (idx->cfg2 && !found) { 106 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1); 107 108 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1); 109 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) { 110 found = 1; 111 if (ata_find_chip(dev, id, pci_get_slot(dev))) { 112 id[0].cfg1 = SIS_133OLD; 113 id[0].max_dma = ATA_UDMA6; 114 } else { 115 id[0].cfg1 = SIS_100NEW; 116 id[0].max_dma = ATA_UDMA5; 117 } 118 ksprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma)); 119 } 120 pci_write_config(dev, 0x4a, reg4a, 1); 121 } 122 if (!found) 123 ksprintf(buffer,"SiS %s %s controller", 124 idx->text, ata_mode2str(idx->max_dma)); 125 else 126 idx = &id[0]; 127 128 device_set_desc_copy(dev, buffer); 129 ctlr->chip = idx; 130 ctlr->chipinit = ata_sis_chipinit; 131 return 0; 132 } 133 134 static int 135 ata_sis_chipinit(device_t dev) 136 { 137 struct ata_pci_controller *ctlr = device_get_softc(dev); 138 139 if (ata_setup_interrupt(dev, ata_generic_intr)) 140 return ENXIO; 141 142 switch (ctlr->chip->cfg1) { 143 case SIS_33: 144 break; 145 case SIS_66: 146 case SIS_100OLD: 147 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1); 148 break; 149 case SIS_100NEW: 150 case SIS_133OLD: 151 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1); 152 break; 153 case SIS_133NEW: 154 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2); 155 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2); 156 break; 157 case SIS_SATA: 158 ctlr->r_type2 = SYS_RES_IOPORT; 159 ctlr->r_rid2 = PCIR_BAR(5); 160 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 161 &ctlr->r_rid2, RF_ACTIVE))) { 162 ctlr->allocate = ata_sis_allocate; 163 ctlr->reset = ata_sis_reset; 164 165 /* enable PCI interrupt */ 166 pci_write_config(dev, PCIR_COMMAND, 167 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 168 } 169 ctlr->setmode = ata_sata_setmode; 170 return 0; 171 default: 172 ata_teardown_interrupt(dev); 173 return ENXIO; 174 } 175 ctlr->setmode = ata_sis_setmode; 176 return 0; 177 } 178 179 static int 180 ata_sis_allocate(device_t dev) 181 { 182 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 183 struct ata_channel *ch = device_get_softc(dev); 184 int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6); 185 186 /* setup the usual register normal pci style */ 187 if (ata_pci_allocate(dev)) 188 return ENXIO; 189 190 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 191 ch->r_io[ATA_SSTATUS].offset = 0x00 + offset; 192 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 193 ch->r_io[ATA_SERROR].offset = 0x04 + offset; 194 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 195 ch->r_io[ATA_SCONTROL].offset = 0x08 + offset; 196 ch->flags |= ATA_NO_SLAVE; 197 198 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */ 199 /* XXX SOS unknown how to enable PHY state change interrupt */ 200 return 0; 201 } 202 203 static void 204 ata_sis_reset(device_t dev) 205 { 206 if (ata_sata_phy_reset(dev)) 207 ata_generic_reset(dev); 208 } 209 210 static void 211 ata_sis_setmode(device_t dev, int mode) 212 { 213 device_t gparent = GRANDPARENT(dev); 214 struct ata_pci_controller *ctlr = device_get_softc(gparent); 215 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 216 struct ata_device *atadev = device_get_softc(dev); 217 int devno = (ch->unit << 1) + atadev->unit; 218 int error; 219 220 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 221 222 if (ctlr->chip->cfg1 == SIS_133NEW) { 223 if (mode > ATA_UDMA2 && 224 pci_read_config(gparent, ch->unit ? 0x52 : 0x50,2) & 0x8000) { 225 ata_print_cable(dev, "controller"); 226 mode = ATA_UDMA2; 227 } 228 } 229 else { 230 if (mode > ATA_UDMA2 && 231 pci_read_config(gparent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) { 232 ata_print_cable(dev, "controller"); 233 mode = ATA_UDMA2; 234 } 235 } 236 237 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 238 239 if (bootverbose) 240 device_printf(dev, "%ssetting %s on %s chip\n", 241 (error) ? "FAILURE " : "", 242 ata_mode2str(mode), ctlr->chip->text); 243 if (!error) { 244 switch (ctlr->chip->cfg1) { 245 case SIS_133NEW: { 246 static const uint32_t timings[] = 247 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008, 248 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac, 249 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c}; 250 u_int32_t reg; 251 252 reg = (pci_read_config(gparent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2); 253 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4); 254 break; 255 } 256 case SIS_133OLD: { 257 static const uint16_t timings[] = 258 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031, 259 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 }; 260 261 u_int16_t reg = 0x40 + (devno << 1); 262 263 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 264 break; 265 } 266 case SIS_100NEW: { 267 static const uint16_t timings[] = 268 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 269 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 }; 270 u_int16_t reg = 0x40 + (devno << 1); 271 272 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 273 break; 274 } 275 case SIS_100OLD: 276 case SIS_66: 277 case SIS_33: { 278 static const uint16_t timings[] = 279 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303, 280 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 }; 281 u_int16_t reg = 0x40 + (devno << 1); 282 283 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 284 break; 285 } 286 } 287 atadev->mode = mode; 288 } 289 } 290