1a1917f14Szrj /*-
2a1917f14Szrj * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
3a1917f14Szrj * All rights reserved.
4a1917f14Szrj *
5a1917f14Szrj * Redistribution and use in source and binary forms, with or without
6a1917f14Szrj * modification, are permitted provided that the following conditions
7a1917f14Szrj * are met:
8a1917f14Szrj * 1. Redistributions of source code must retain the above copyright
9a1917f14Szrj * notice, this list of conditions and the following disclaimer,
10a1917f14Szrj * without modification, immediately at the beginning of the file.
11a1917f14Szrj * 2. Redistributions in binary form must reproduce the above copyright
12a1917f14Szrj * notice, this list of conditions and the following disclaimer in the
13a1917f14Szrj * documentation and/or other materials provided with the distribution.
14a1917f14Szrj *
15a1917f14Szrj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16a1917f14Szrj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17a1917f14Szrj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18a1917f14Szrj * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19a1917f14Szrj * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20a1917f14Szrj * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21a1917f14Szrj * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22a1917f14Szrj * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23a1917f14Szrj * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24a1917f14Szrj * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25a1917f14Szrj */
26a1917f14Szrj
27a1917f14Szrj /* local prototypes */
28a1917f14Szrj static int ata_via_chipinit(device_t dev);
29a1917f14Szrj static int ata_via_allocate(device_t dev);
30a1917f14Szrj static void ata_via_reset(device_t dev);
314b582042Szrj static void ata_via_old_setmode(device_t dev, int mode);
32a1917f14Szrj static void ata_via_southbridge_fixup(device_t dev);
334b582042Szrj static void ata_via_new_setmode(device_t dev, int mode);
34a1917f14Szrj
35853eb30dSzrj /* misc defines */
36853eb30dSzrj #define VIA33 0
37853eb30dSzrj #define VIA66 1
38853eb30dSzrj #define VIA100 2
39853eb30dSzrj #define VIA133 3
40853eb30dSzrj
41853eb30dSzrj #define VIACLK 0x01
42853eb30dSzrj #define VIABUG 0x02
43853eb30dSzrj #define VIABAR 0x04
44853eb30dSzrj #define VIAAHCI 0x08
45853eb30dSzrj
46a1917f14Szrj /*
47a1917f14Szrj * VIA Technologies Inc. chipset support functions
48a1917f14Szrj */
49a1917f14Szrj int
ata_via_ident(device_t dev)50a1917f14Szrj ata_via_ident(device_t dev)
51a1917f14Szrj {
52a1917f14Szrj struct ata_pci_controller *ctlr = device_get_softc(dev);
5359503772Szrj static const struct ata_chip_id ids[] =
54a1917f14Szrj {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" },
55a1917f14Szrj { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" },
56a1917f14Szrj { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" },
57a1917f14Szrj { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" },
58a1917f14Szrj { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"},
59a1917f14Szrj { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" },
60a1917f14Szrj { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" },
61a1917f14Szrj { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" },
62a1917f14Szrj { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" },
63a1917f14Szrj { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" },
64a1917f14Szrj { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" },
65a1917f14Szrj { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" },
66a1917f14Szrj { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
67a1917f14Szrj { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" },
68*560012aaSzrj { ATA_VIA8237S, 0x00, VIA133, 0x00, ATA_UDMA6, "8237S" },
69*560012aaSzrj { ATA_VIA8237_5372, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
70*560012aaSzrj { ATA_VIA8237_7372, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
71a1917f14Szrj { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" },
72a1917f14Szrj { 0, 0, 0, 0, 0, 0 }};
7359503772Szrj static const struct ata_chip_id new_ids[] =
74a1917f14Szrj {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" },
75a1917f14Szrj { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" },
76a1917f14Szrj { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" },
77a1917f14Szrj { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" },
78a1917f14Szrj { ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" },
79a1917f14Szrj { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" },
80a1917f14Szrj { 0, 0, 0, 0, 0, 0 }};
8159503772Szrj
8259503772Szrj if (pci_get_vendor(dev) != ATA_VIA_ID)
8359503772Szrj return ENXIO;
84a1917f14Szrj
85a1917f14Szrj if (pci_get_devid(dev) == ATA_VIA82C571) {
8659503772Szrj if (!(ctlr->chip = ata_find_chip(dev, ids, -99)))
87a1917f14Szrj return ENXIO;
88a1917f14Szrj }
89a1917f14Szrj else {
9059503772Szrj if (!(ctlr->chip = ata_match_chip(dev, new_ids)))
91a1917f14Szrj return ENXIO;
92a1917f14Szrj }
93a1917f14Szrj
9459503772Szrj ata_set_desc(dev);
95a1917f14Szrj ctlr->chipinit = ata_via_chipinit;
96a1917f14Szrj return 0;
97a1917f14Szrj }
98a1917f14Szrj
99a1917f14Szrj static int
ata_via_chipinit(device_t dev)100a1917f14Szrj ata_via_chipinit(device_t dev)
101a1917f14Szrj {
102a1917f14Szrj struct ata_pci_controller *ctlr = device_get_softc(dev);
103a1917f14Szrj
10443156ad7Szrj if (ata_setup_interrupt(dev, ata_generic_intr))
105a1917f14Szrj return ENXIO;
106a1917f14Szrj
107a1917f14Szrj if (ctlr->chip->max_dma >= ATA_SA150) {
108a1917f14Szrj /* do we have AHCI capability ? */
109a1917f14Szrj if ((ctlr->chip->cfg2 == VIAAHCI) && ata_ahci_chipinit(dev) != ENXIO)
110a1917f14Szrj return 0;
111a1917f14Szrj
112a1917f14Szrj ctlr->r_type2 = SYS_RES_IOPORT;
113a1917f14Szrj ctlr->r_rid2 = PCIR_BAR(5);
114a1917f14Szrj if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
115a1917f14Szrj &ctlr->r_rid2, RF_ACTIVE))) {
116a1917f14Szrj ctlr->allocate = ata_via_allocate;
117a1917f14Szrj ctlr->reset = ata_via_reset;
118a1917f14Szrj
119a1917f14Szrj /* enable PCI interrupt */
120a1917f14Szrj pci_write_config(dev, PCIR_COMMAND,
121a1917f14Szrj pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
122a1917f14Szrj }
123a1917f14Szrj
124a1917f14Szrj if (ctlr->chip->cfg2 & VIABAR) {
125a1917f14Szrj ctlr->channels = 3;
1264b582042Szrj ctlr->setmode = ata_via_new_setmode;
127a1917f14Szrj }
128a1917f14Szrj else
129a1917f14Szrj ctlr->setmode = ata_sata_setmode;
130a1917f14Szrj return 0;
131a1917f14Szrj }
132a1917f14Szrj
133a1917f14Szrj /* prepare for ATA-66 on the 82C686a and 82C596b */
134a1917f14Szrj if (ctlr->chip->cfg2 & VIACLK)
135a1917f14Szrj pci_write_config(dev, 0x50, 0x030b030b, 4);
136a1917f14Szrj
137a1917f14Szrj /* the southbridge might need the data corruption fix */
138a1917f14Szrj if (ctlr->chip->cfg2 & VIABUG)
139a1917f14Szrj ata_via_southbridge_fixup(dev);
140a1917f14Szrj
141a1917f14Szrj /* set fifo configuration half'n'half */
142a1917f14Szrj pci_write_config(dev, 0x43,
143a1917f14Szrj (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
144a1917f14Szrj
145a1917f14Szrj /* set status register read retry */
146a1917f14Szrj pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
147a1917f14Szrj
148a1917f14Szrj /* set DMA read & end-of-sector fifo flush */
149a1917f14Szrj pci_write_config(dev, 0x46,
150a1917f14Szrj (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
151a1917f14Szrj
152a1917f14Szrj /* set sector size */
153a1917f14Szrj pci_write_config(dev, 0x60, DEV_BSIZE, 2);
154a1917f14Szrj pci_write_config(dev, 0x68, DEV_BSIZE, 2);
155a1917f14Szrj
1564b582042Szrj ctlr->setmode = ata_via_old_setmode;
157a1917f14Szrj return 0;
158a1917f14Szrj }
159a1917f14Szrj
160a1917f14Szrj static int
ata_via_allocate(device_t dev)161a1917f14Szrj ata_via_allocate(device_t dev)
162a1917f14Szrj {
163a1917f14Szrj struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
164a1917f14Szrj struct ata_channel *ch = device_get_softc(dev);
165a1917f14Szrj
166a1917f14Szrj /* newer SATA chips has resources in one BAR for each channel */
167a1917f14Szrj if (ctlr->chip->cfg2 & VIABAR) {
168a1917f14Szrj struct resource *r_io;
169a1917f14Szrj int i, rid;
170a1917f14Szrj
171a1917f14Szrj rid = PCIR_BAR(ch->unit);
172a1917f14Szrj if (!(r_io = bus_alloc_resource_any(device_get_parent(dev),
173a1917f14Szrj SYS_RES_IOPORT,
174a1917f14Szrj &rid, RF_ACTIVE)))
175a1917f14Szrj return ENXIO;
176a1917f14Szrj
177a1917f14Szrj for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
178a1917f14Szrj ch->r_io[i].res = r_io;
179a1917f14Szrj ch->r_io[i].offset = i;
180a1917f14Szrj }
181a1917f14Szrj ch->r_io[ATA_CONTROL].res = r_io;
182a1917f14Szrj ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE;
183a1917f14Szrj ch->r_io[ATA_IDX_ADDR].res = r_io;
184a1917f14Szrj ata_default_registers(dev);
185a1917f14Szrj for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
186a1917f14Szrj ch->r_io[i].res = ctlr->r_res1;
187a1917f14Szrj ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
188a1917f14Szrj }
189a1917f14Szrj ata_pci_hw(dev);
190a1917f14Szrj if (ch->unit >= 2)
191a1917f14Szrj return 0;
192a1917f14Szrj }
193a1917f14Szrj else {
194a1917f14Szrj /* setup the usual register normal pci style */
195a1917f14Szrj if (ata_pci_allocate(dev))
196a1917f14Szrj return ENXIO;
197a1917f14Szrj }
198a1917f14Szrj
199a1917f14Szrj ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
200a1917f14Szrj ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1);
201a1917f14Szrj ch->r_io[ATA_SERROR].res = ctlr->r_res2;
202a1917f14Szrj ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1);
203a1917f14Szrj ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
204a1917f14Szrj ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1);
205a1917f14Szrj ch->flags |= ATA_NO_SLAVE;
206a1917f14Szrj
207a1917f14Szrj /* XXX SOS PHY hotplug handling missing in VIA chip ?? */
208a1917f14Szrj /* XXX SOS unknown how to enable PHY state change interrupt */
209a1917f14Szrj return 0;
210a1917f14Szrj }
211a1917f14Szrj
212a1917f14Szrj static void
ata_via_reset(device_t dev)213a1917f14Szrj ata_via_reset(device_t dev)
214a1917f14Szrj {
215a1917f14Szrj struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
216a1917f14Szrj struct ata_channel *ch = device_get_softc(dev);
217a1917f14Szrj
218a1917f14Szrj if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1))
219a1917f14Szrj ata_generic_reset(dev);
220a1917f14Szrj else
221a1917f14Szrj if (ata_sata_phy_reset(dev))
222a1917f14Szrj ata_generic_reset(dev);
223a1917f14Szrj }
224a1917f14Szrj
225a1917f14Szrj static void
ata_via_new_setmode(device_t dev,int mode)2264b582042Szrj ata_via_new_setmode(device_t dev, int mode)
227a1917f14Szrj {
228a1917f14Szrj device_t gparent = GRANDPARENT(dev);
229a1917f14Szrj struct ata_pci_controller *ctlr = device_get_softc(gparent);
230a1917f14Szrj struct ata_channel *ch = device_get_softc(device_get_parent(dev));
231a1917f14Szrj struct ata_device *atadev = device_get_softc(dev);
232a1917f14Szrj int error;
233a1917f14Szrj
234a1917f14Szrj if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) {
23559503772Szrj static const uint8_t pio_timings[] = { 0xa8, 0x65, 0x65, 0x32, 0x20,
236a1917f14Szrj 0x65, 0x32, 0x20,
237a1917f14Szrj 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
23859503772Szrj static const uint8_t dma_timings[] = { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 };
239a1917f14Szrj
240a1917f14Szrj mode = ata_check_80pin(dev, ata_limit_mode(dev, mode, ATA_UDMA6));
241a1917f14Szrj error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
242a1917f14Szrj if (bootverbose)
243a1917f14Szrj device_printf(dev, "%ssetting %s on %s chip\n",
244a1917f14Szrj (error) ? "FAILURE " : "", ata_mode2str(mode),
245a1917f14Szrj ctlr->chip->text);
246a1917f14Szrj if (!error) {
247a1917f14Szrj pci_write_config(gparent, 0xab, pio_timings[ata_mode2idx(mode)], 1);
248a1917f14Szrj if (mode >= ATA_UDMA0)
249a1917f14Szrj pci_write_config(gparent, 0xb3,
250a1917f14Szrj dma_timings[mode & ATA_MODE_MASK], 1);
251a1917f14Szrj atadev->mode = mode;
252a1917f14Szrj }
253a1917f14Szrj }
254a1917f14Szrj else
255a1917f14Szrj ata_sata_setmode(dev, mode);
256a1917f14Szrj }
257a1917f14Szrj
258a1917f14Szrj static void
ata_via_old_setmode(device_t dev,int mode)2594b582042Szrj ata_via_old_setmode(device_t dev, int mode)
2604b582042Szrj {
2614b582042Szrj device_t gparent = GRANDPARENT(dev);
2624b582042Szrj struct ata_pci_controller *ctlr = device_get_softc(gparent);
2634b582042Szrj struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2644b582042Szrj struct ata_device *atadev = device_get_softc(dev);
2652458a87aSzrj int devno = (ch->unit << 1) + atadev->unit;
26659503772Szrj int reg = 0x53 - devno;
26759503772Szrj int error;
26859503772Szrj static const uint8_t timings[] =
26959503772Szrj { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
2704b582042Szrj 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
27159503772Szrj static const uint8_t modes[][7] = {
2724b582042Szrj { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
2734b582042Szrj { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
2744b582042Szrj { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
2754b582042Szrj { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 } }; /* VIA ATA133 */
2764b582042Szrj
2774b582042Szrj mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
2784b582042Szrj mode = ata_check_80pin(dev, mode);
2794b582042Szrj
2804b582042Szrj error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2814b582042Szrj if (bootverbose)
2824b582042Szrj device_printf(dev, "%ssetting %s on %s chip\n",
2834b582042Szrj (error) ? "FAILURE " : "", ata_mode2str(mode),
2844b582042Szrj ctlr->chip->text);
2854b582042Szrj if (!error) {
2864b582042Szrj if (ctlr->chip->cfg1 != VIA133)
2874b582042Szrj pci_write_config(gparent, reg - 0x08,timings[ata_mode2idx(mode)],1);
2884b582042Szrj if (mode >= ATA_UDMA0)
2894b582042Szrj pci_write_config(gparent, reg,
2904b582042Szrj modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1);
2914b582042Szrj else
2924b582042Szrj pci_write_config(gparent, reg, 0x8b, 1);
2934b582042Szrj atadev->mode = mode;
2944b582042Szrj }
2954b582042Szrj }
2964b582042Szrj
2974b582042Szrj static void
ata_via_southbridge_fixup(device_t dev)298a1917f14Szrj ata_via_southbridge_fixup(device_t dev)
299a1917f14Szrj {
300a1917f14Szrj device_t *children;
301a1917f14Szrj int nchildren, i;
302a1917f14Szrj
303a1917f14Szrj if (device_get_children(device_get_parent(dev), &children, &nchildren))
304a1917f14Szrj return;
305a1917f14Szrj
306a1917f14Szrj for (i = 0; i < nchildren; i++) {
307a1917f14Szrj if (pci_get_devid(children[i]) == ATA_VIA8363 ||
308a1917f14Szrj pci_get_devid(children[i]) == ATA_VIA8371 ||
309a1917f14Szrj pci_get_devid(children[i]) == ATA_VIA8662 ||
310a1917f14Szrj pci_get_devid(children[i]) == ATA_VIA8361) {
311a1917f14Szrj u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
312a1917f14Szrj
313a1917f14Szrj if ((reg76 & 0xf0) != 0xd0) {
314a1917f14Szrj device_printf(dev,
315a1917f14Szrj "Correcting VIA config for southbridge data corruption bug\n");
316a1917f14Szrj pci_write_config(children[i], 0x75, 0x80, 1);
317a1917f14Szrj pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
318a1917f14Szrj }
319a1917f14Szrj break;
320a1917f14Szrj }
321a1917f14Szrj }
322a1917f14Szrj kfree(children, M_TEMP);
323a1917f14Szrj }
324