1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * $FreeBSD: src/sys/dev/sdhci/sdhci.c,v 1.8 2009/02/17 19:12:15 mav Exp $ 26 */ 27 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/bus.h> 31 #include <sys/callout.h> 32 #include <sys/conf.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/module.h> 36 #include <sys/spinlock.h> 37 #include <sys/resource.h> 38 #include <sys/rman.h> 39 #include <sys/sysctl.h> 40 #include <sys/taskqueue.h> 41 42 #include <bus/mmc/bridge.h> 43 #include <bus/mmc/mmcreg.h> 44 #include <bus/mmc/mmcbrvar.h> 45 46 #include "mmcbr_if.h" 47 #include "sdhci.h" 48 #include "sdhci_if.h" 49 50 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 51 52 int sdhci_debug = 0; 53 TUNABLE_INT("hw.sdhci.debug", &sdhci_debug); 54 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level"); 55 56 static int sdhci_sdma_disable = 0; 57 TUNABLE_INT("hw.sdhci.sdma_disable", &sdhci_sdma_disable); 58 59 static int sdhci_adma2_disable = 0; 60 TUNABLE_INT("hw.sdhci.adma2_disable", &sdhci_adma2_disable); 61 62 static int sdhci_adma2_test = 0; 63 TUNABLE_INT("hw.sdhci.adma2_test", &sdhci_adma2_test); 64 65 u_int sdhci_quirk_clear = 0; 66 TUNABLE_INT("hw.sdhci.quirk_clear", &sdhci_quirk_clear); 67 u_int sdhci_quirk_set = 0; 68 TUNABLE_INT("hw.sdhci.quirk_set", &sdhci_quirk_set); 69 70 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 71 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 72 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 73 #define RD_MULTI_4(slot, off, ptr, count) \ 74 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 75 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 76 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 77 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 78 #define WR_MULTI_4(slot, off, ptr, count) \ 79 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 80 81 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 82 static void sdhci_start(struct sdhci_slot *slot); 83 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 84 85 static void sdhci_card_task(void *, int); 86 87 static int sdhci_dma_alloc(struct sdhci_slot *slot); 88 static void sdhci_dmamem_free(bus_dmamem_t *mem); 89 static void sdhci_dma_free(struct sdhci_slot *slot); 90 static void sdhci_adma2_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, 91 int error); 92 93 /* helper routines */ 94 static void sdhci_dumpregs(struct sdhci_slot *slot); 95 static int slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 96 __printflike(2, 3); 97 98 #define SDHCI_LOCK(_slot) lockmgr(&(_slot)->lock, LK_EXCLUSIVE) 99 #define SDHCI_UNLOCK(_slot) lockmgr(&(_slot)->lock, LK_RELEASE) 100 #define SDHCI_LOCK_INIT(_slot) lockinit(&(_slot)->lock, "sdhci", 0, LK_CANRECURSE) 101 #define SDHCI_LOCK_DESTROY(_slot) lockuninit(&(_slot)->lock); 102 #define SDHCI_ASSERT_LOCKED(_slot) KKASSERT(lockstatus(&(_slot)->lock, curthread) != 0); 103 #define SDHCI_ASSERT_UNLOCKED(_slot) KKASSERT(lockstatus(&(_slot)->lock, curthread) == 0); 104 105 #define SDHCI_DEFAULT_MAX_FREQ 50 106 107 #define SDHCI_200_MAX_DIVIDER 256 108 #define SDHCI_300_MAX_DIVIDER 2046 109 110 /* 111 * Broadcom BCM577xx Controller Constants 112 */ 113 #define BCM577XX_DEFAULT_MAX_DIVIDER 256 /* Maximum divider supported by the default clock source. */ 114 #define BCM577XX_ALT_CLOCK_BASE 63000000 /* Alternative clock's base frequency. */ 115 116 #define BCM577XX_HOST_CONTROL 0x198 117 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF 118 #define BCM577XX_CTRL_CLKSEL_SHIFT 12 119 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0 120 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3 121 122 static int 123 slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 124 { 125 __va_list ap; 126 int retval; 127 128 retval = kprintf("%s-slot%d: ", 129 device_get_nameunit(slot->bus), slot->num); 130 131 __va_start(ap, fmt); 132 retval += kvprintf(fmt, ap); 133 __va_end(ap); 134 return (retval); 135 } 136 137 static void 138 sdhci_dumpregs(struct sdhci_slot *slot) 139 { 140 slot_printf(slot, 141 "============== REGISTER DUMP ==============\n"); 142 143 slot_printf(slot, "SDMA addr: 0x%08x | Version: 0x%08x\n", 144 RD4(slot, SDHCI_SDMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 145 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 146 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 147 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 148 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 149 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 150 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 151 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 152 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 153 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 154 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 155 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 156 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 157 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 158 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 159 slot_printf(slot, "AC12 err: 0x%08x | Host ctl2: 0x%08x\n", 160 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2)); 161 slot_printf(slot, "Caps: 0x%08x | Caps2: 0x%08x\n", 162 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2)); 163 slot_printf(slot, "Max curr: 0x%08x | ADMA err: 0x%08x\n", 164 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR)); 165 slot_printf(slot, "ADMA addr: 0x%08x | Slot int: 0x%08x\n", 166 RD4(slot, SDHCI_ADMA_ADDRESS_LOW), RD2(slot, SDHCI_SLOT_INT_STATUS)); 167 168 slot_printf(slot, 169 "===========================================\n"); 170 } 171 172 static void 173 sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 174 { 175 int timeout; 176 uint32_t clock; 177 178 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 179 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot)) 180 return; 181 } 182 183 /* Some controllers need this kick or reset won't work. */ 184 if ((mask & SDHCI_RESET_ALL) == 0 && 185 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 186 /* This is to force an update */ 187 clock = slot->clock; 188 slot->clock = 0; 189 sdhci_set_clock(slot, clock); 190 } 191 192 if (mask & SDHCI_RESET_ALL) { 193 slot->clock = 0; 194 slot->power = 0; 195 } 196 197 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 198 199 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) { 200 /* 201 * Resets on TI OMAPs and AM335x are incompatible with SDHCI 202 * specification. The reset bit has internal propagation delay, 203 * so a fast read after write returns 0 even if reset process is 204 * in progress. The workaround is to poll for 1 before polling 205 * for 0. In the worst case, if we miss seeing it asserted the 206 * time we spent waiting is enough to ensure the reset finishes. 207 */ 208 timeout = 10000; 209 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) { 210 if (timeout <= 0) 211 break; 212 timeout--; 213 DELAY(1); 214 } 215 } 216 217 /* Wait max 100 ms */ 218 timeout = 10000; 219 /* Controller clears the bits when it's done */ 220 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) { 221 if (timeout <= 0) { 222 slot_printf(slot, "Reset 0x%x never completed.\n", 223 mask); 224 sdhci_dumpregs(slot); 225 return; 226 } 227 timeout--; 228 DELAY(10); 229 } 230 } 231 232 static void 233 sdhci_init(struct sdhci_slot *slot) 234 { 235 236 sdhci_reset(slot, SDHCI_RESET_ALL); 237 238 /* Enable interrupts. */ 239 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 240 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 241 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 242 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 243 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 244 SDHCI_INT_ACMD12ERR | SDHCI_INT_ADMAERR; 245 if (!(slot->opt & SDHCI_SLOT_EMBEDDED)) 246 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT; 247 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 248 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 249 } 250 251 static void 252 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 253 { 254 uint32_t clk_base; 255 uint32_t clk_sel; 256 uint32_t res; 257 uint16_t clk; 258 uint16_t div; 259 int timeout; 260 261 if (clock == slot->clock) 262 return; 263 slot->clock = clock; 264 265 /* Turn off the clock. */ 266 clk = RD2(slot, SDHCI_CLOCK_CONTROL); 267 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); 268 /* If no clock requested - leave it so. */ 269 if (clock == 0) 270 return; 271 272 /* Determine the clock base frequency */ 273 clk_base = slot->max_clk; 274 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) { 275 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & BCM577XX_CTRL_CLKSEL_MASK; 276 277 /* Select clock source appropriate for the requested frequency. */ 278 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) { 279 clk_base = BCM577XX_ALT_CLOCK_BASE; 280 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ << BCM577XX_CTRL_CLKSEL_SHIFT); 281 } else { 282 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT << BCM577XX_CTRL_CLKSEL_SHIFT); 283 } 284 285 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel); 286 } 287 288 /* Recalculate timeout clock frequency based on the new sd clock. */ 289 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 290 slot->timeout_clk = slot->clock / 1000; 291 292 if (slot->version < SDHCI_SPEC_300) { 293 /* Looking for highest freq <= clock. */ 294 res = clk_base; 295 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { 296 if (res <= clock) 297 break; 298 res >>= 1; 299 } 300 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 301 div >>= 1; 302 } else { 303 /* Version 3.0 divisors are multiples of two up to 1023 * 2 */ 304 if (clock >= clk_base) 305 div = 0; 306 else { 307 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { 308 if ((clk_base / div) <= clock) 309 break; 310 } 311 } 312 div >>= 1; 313 } 314 315 if (bootverbose || sdhci_debug) 316 slot_printf(slot, "Divider %d for freq %d (base %d)\n", 317 div, clock, clk_base); 318 319 /* Now we have got divider, set it. */ 320 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 321 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 322 << SDHCI_DIVIDER_HI_SHIFT; 323 324 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 325 /* Enable clock. */ 326 clk |= SDHCI_CLOCK_INT_EN; 327 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 328 /* Wait up to 10 ms until it stabilize. */ 329 timeout = 10; 330 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 331 & SDHCI_CLOCK_INT_STABLE)) { 332 if (timeout == 0) { 333 slot_printf(slot, 334 "Internal clock never stabilised.\n"); 335 sdhci_dumpregs(slot); 336 return; 337 } 338 timeout--; 339 DELAY(1000); 340 } 341 /* Pass clock signal to the bus. */ 342 clk |= SDHCI_CLOCK_CARD_EN; 343 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 344 } 345 346 static void 347 sdhci_set_power(struct sdhci_slot *slot, u_char power) 348 { 349 uint8_t pwr; 350 351 if (slot->power == power) 352 return; 353 354 slot->power = power; 355 356 /* Turn off the power. */ 357 pwr = 0; 358 WR1(slot, SDHCI_POWER_CONTROL, pwr); 359 /* If power down requested - leave it so. */ 360 if (power == 0) 361 return; 362 /* Set voltage. */ 363 switch (1 << power) { 364 case MMC_OCR_LOW_VOLTAGE: 365 pwr |= SDHCI_POWER_180; 366 break; 367 case MMC_OCR_290_300: 368 case MMC_OCR_300_310: 369 pwr |= SDHCI_POWER_300; 370 break; 371 case MMC_OCR_320_330: 372 case MMC_OCR_330_340: 373 pwr |= SDHCI_POWER_330; 374 break; 375 } 376 WR1(slot, SDHCI_POWER_CONTROL, pwr); 377 /* Turn on the power. */ 378 pwr |= SDHCI_POWER_ON; 379 WR1(slot, SDHCI_POWER_CONTROL, pwr); 380 } 381 382 static void 383 sdhci_read_block_pio(struct sdhci_slot *slot) 384 { 385 uint32_t data; 386 char *buffer; 387 size_t left; 388 389 buffer = slot->curcmd->data->data; 390 buffer += slot->offset; 391 /* Transfer one block at a time. */ 392 left = min(512, slot->curcmd->data->len - slot->offset); 393 slot->offset += left; 394 395 /* If we are too fast, broken controllers return zeroes. */ 396 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 397 DELAY(10); 398 /* Handle unaligned and aligned buffer cases. */ 399 if ((intptr_t)buffer & 3) { 400 while (left > 3) { 401 data = RD4(slot, SDHCI_BUFFER); 402 buffer[0] = data; 403 buffer[1] = (data >> 8); 404 buffer[2] = (data >> 16); 405 buffer[3] = (data >> 24); 406 buffer += 4; 407 left -= 4; 408 } 409 } else { 410 RD_MULTI_4(slot, SDHCI_BUFFER, 411 (uint32_t *)buffer, left >> 2); 412 left &= 3; 413 } 414 /* Handle uneven size case. */ 415 if (left > 0) { 416 data = RD4(slot, SDHCI_BUFFER); 417 while (left > 0) { 418 *(buffer++) = data; 419 data >>= 8; 420 left--; 421 } 422 } 423 } 424 425 static void 426 sdhci_write_block_pio(struct sdhci_slot *slot) 427 { 428 uint32_t data = 0; 429 char *buffer; 430 size_t left; 431 432 buffer = slot->curcmd->data->data; 433 buffer += slot->offset; 434 /* Transfer one block at a time. */ 435 left = min(512, slot->curcmd->data->len - slot->offset); 436 slot->offset += left; 437 438 /* Handle unaligned and aligned buffer cases. */ 439 if ((intptr_t)buffer & 3) { 440 while (left > 3) { 441 data = buffer[0] + 442 (buffer[1] << 8) + 443 (buffer[2] << 16) + 444 (buffer[3] << 24); 445 left -= 4; 446 buffer += 4; 447 WR4(slot, SDHCI_BUFFER, data); 448 } 449 } else { 450 WR_MULTI_4(slot, SDHCI_BUFFER, 451 (uint32_t *)buffer, left >> 2); 452 left &= 3; 453 } 454 /* Handle uneven size case. */ 455 if (left > 0) { 456 while (left > 0) { 457 data <<= 8; 458 data += *(buffer++); 459 left--; 460 } 461 WR4(slot, SDHCI_BUFFER, data); 462 } 463 } 464 465 static void 466 sdhci_transfer_pio(struct sdhci_slot *slot) 467 { 468 469 /* Read as many blocks as possible. */ 470 if (slot->curcmd->data->flags & MMC_DATA_READ) { 471 while (RD4(slot, SDHCI_PRESENT_STATE) & 472 SDHCI_DATA_AVAILABLE) { 473 sdhci_read_block_pio(slot); 474 if (slot->offset >= slot->curcmd->data->len) 475 break; 476 } 477 } else { 478 while (RD4(slot, SDHCI_PRESENT_STATE) & 479 SDHCI_SPACE_AVAILABLE) { 480 sdhci_write_block_pio(slot); 481 if (slot->offset >= slot->curcmd->data->len) 482 break; 483 } 484 } 485 } 486 487 static void 488 sdhci_card_delay(void *arg) 489 { 490 struct sdhci_slot *slot = arg; 491 492 taskqueue_enqueue(taskqueue_swi_mp, &slot->card_task); 493 } 494 495 static void 496 sdhci_card_task(void *arg, int pending) 497 { 498 struct sdhci_slot *slot = arg; 499 500 SDHCI_LOCK(slot); 501 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) { 502 if (slot->dev == NULL) { 503 /* If card is present - attach mmc bus. */ 504 slot->dev = device_add_child(slot->bus, "mmc", -1); 505 device_set_ivars(slot->dev, slot); 506 SDHCI_UNLOCK(slot); 507 device_probe_and_attach(slot->dev); 508 } else 509 SDHCI_UNLOCK(slot); 510 } else { 511 if (slot->dev != NULL) { 512 /* If no card present - detach mmc bus. */ 513 device_t d = slot->dev; 514 slot->dev = NULL; 515 SDHCI_UNLOCK(slot); 516 device_delete_child(slot->bus, d); 517 } else 518 SDHCI_UNLOCK(slot); 519 } 520 } 521 522 static int 523 sdhci_dma_alloc(struct sdhci_slot *slot) 524 { 525 int err; 526 527 /* Allocate DMA memory for SDMA. */ 528 err = bus_dmamem_coherent(bus_get_dma_tag(slot->bus), 529 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 530 BUS_SPACE_MAXADDR, DMA_BLOCK_SIZE, BUS_DMA_NOWAIT, 531 &slot->sdma_mem); 532 if (err != 0) { 533 device_printf(slot->bus, "Can't alloc DMA memory for SDMA\n"); 534 goto done; 535 } 536 537 /* Allocate DMA memory for 32bit ADMA2 descriptors. */ 538 err = bus_dmamem_coherent(bus_get_dma_tag(slot->bus), 539 4, 0, BUS_SPACE_MAXADDR_32BIT, 540 BUS_SPACE_MAXADDR, SDHCI_ADMA2_DESCBUF_SIZE, BUS_DMA_NOWAIT, 541 &slot->adma2_descs); 542 if (err != 0) { 543 device_printf(slot->bus, 544 "Can't alloc DMA memory for ADMA2 descriptors\n"); 545 goto error1; 546 } 547 548 /* Allocate DMA tag for 32bit ADMA2 data buffer */ 549 err = bus_dma_tag_create(bus_get_dma_tag(slot->bus), 550 4, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 551 MAXPHYS, SDHCI_ADMA2_DESC_COUNT, 552 MIN(MAXPHYS, SDHCI_ADMA2_MAX_SEGSIZE), 553 BUS_DMA_ALLOCNOW | BUS_DMA_ALLOCALL, 554 &slot->adma2_tag); 555 if (err != 0) { 556 device_printf(slot->bus, "Can't create DMA tag for ADMA2\n"); 557 goto error2; 558 } 559 560 /* Allocate DMA map for ADMA2 data buffer */ 561 err = bus_dmamap_create(slot->adma2_tag, BUS_DMA_NOWAIT, 562 &slot->adma2_map); 563 if (err != 0) { 564 device_printf(slot->bus, "Can't create DMA map for ADMA2\n"); 565 goto error3; 566 } 567 568 return (0); 569 570 error3: 571 bus_dma_tag_destroy(slot->adma2_tag); 572 error2: 573 sdhci_dmamem_free(&slot->adma2_descs); 574 error1: 575 sdhci_dmamem_free(&slot->sdma_mem); 576 done: 577 return (err); 578 } 579 580 static void 581 sdhci_dmamem_free(bus_dmamem_t *dma) 582 { 583 bus_dmamap_unload(dma->dmem_tag, dma->dmem_map); 584 bus_dmamem_free(dma->dmem_tag, dma->dmem_addr, dma->dmem_map); 585 bus_dma_tag_destroy(dma->dmem_tag); 586 } 587 588 static void 589 sdhci_dma_free(struct sdhci_slot *slot) 590 { 591 bus_dmamap_destroy(slot->adma2_tag, slot->adma2_map); 592 bus_dma_tag_destroy(slot->adma2_tag); 593 sdhci_dmamem_free(&slot->sdma_mem); 594 sdhci_dmamem_free(&slot->adma2_descs); 595 } 596 597 static void 598 sdhci_adma2_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 599 { 600 struct sdhci_slot *slot = arg; 601 bus_dmamem_t *descmem = &slot->adma2_descs; 602 struct sdhci_adma2_desc32 *descs = (void *)descmem->dmem_addr; 603 int i; 604 605 if (error != 0) { 606 /* This signals, that loading was unsuccessful */ 607 memset(&descs[0], 0, sizeof(*descs)); 608 return; 609 } 610 611 for (i = 0; i < nsegs; i++) { 612 descs[i].address = segs[i].ds_addr; 613 /* 614 * The 65536 segment length case is broken in some sdhc host 615 * controllers, so we actually use a maximum segment length 616 * of 32768 for the DMA mapping and ds_len should be at most 617 * 32768 here. 618 */ 619 if (segs[i].ds_len == 65536) 620 descs[i].length = 0; 621 else 622 descs[i].length = segs[i].ds_len; 623 descs[i].attribute = 624 SDHCI_ADMA2_ATTR_VALID | SDHCI_ADMA2_ATTR_OP_TRAN; 625 } 626 descs[nsegs-1].attribute |= SDHCI_ADMA2_ATTR_END; 627 /* If there is room left, explicitly add an invalid descriptor. */ 628 if (nsegs < SDHCI_ADMA2_DESC_COUNT) 629 memset(&descs[nsegs], 0, sizeof(*descs)); 630 } 631 632 int 633 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 634 { 635 uint32_t caps, caps2, freq, host_caps; 636 int err; 637 638 SDHCI_LOCK_INIT(slot); 639 slot->num = num; 640 slot->bus = dev; 641 642 err = sdhci_dma_alloc(slot); 643 if (err != 0) { 644 SDHCI_LOCK_DESTROY(slot); 645 return (err); 646 } 647 648 /* Initialize slot. */ 649 sdhci_init(slot); 650 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 651 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 652 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) { 653 caps = slot->caps; 654 caps2 = slot->caps2; 655 } else { 656 caps = RD4(slot, SDHCI_CAPABILITIES); 657 if (slot->version >= SDHCI_SPEC_300) 658 caps2 = RD4(slot, SDHCI_CAPABILITIES2); 659 else 660 caps2 = 0; 661 } 662 if (slot->version >= SDHCI_SPEC_300) { 663 if ((caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_REMOVABLE && 664 (caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_EMBEDDED) { 665 device_printf(dev, 666 "Driver doesn't support shared bus slots\n"); 667 sdhci_dma_free(slot); 668 SDHCI_LOCK_DESTROY(slot); 669 return (1); 670 } else if ((caps & SDHCI_SLOTTYPE_MASK) == 671 SDHCI_SLOTTYPE_EMBEDDED) { 672 slot->opt |= SDHCI_SLOT_EMBEDDED; 673 } 674 } 675 /* Calculate base clock frequency. */ 676 if (slot->version >= SDHCI_SPEC_300) 677 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 678 SDHCI_CLOCK_BASE_SHIFT; 679 else 680 freq = (caps & SDHCI_CLOCK_BASE_MASK) >> 681 SDHCI_CLOCK_BASE_SHIFT; 682 if (freq != 0) 683 slot->max_clk = freq * 1000000; 684 /* 685 * If the frequency wasn't in the capabilities and the hardware driver 686 * hasn't already set max_clk we're probably not going to work right 687 * with an assumption, so complain about it. 688 */ 689 if (slot->max_clk == 0) { 690 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000; 691 device_printf(dev, "Hardware doesn't specify base clock " 692 "frequency, using %dMHz as default.\n", SDHCI_DEFAULT_MAX_FREQ); 693 } 694 /* Calculate timeout clock frequency. */ 695 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 696 slot->timeout_clk = slot->max_clk / 1000; 697 } else { 698 slot->timeout_clk = 699 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 700 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 701 slot->timeout_clk *= 1000; 702 } 703 /* 704 * If the frequency wasn't in the capabilities and the hardware driver 705 * hasn't already set timeout_clk we'll probably work okay using the 706 * max timeout, but still mention it. 707 */ 708 if (slot->timeout_clk == 0) { 709 device_printf(dev, "Hardware doesn't specify timeout clock " 710 "frequency, setting BROKEN_TIMEOUT quirk.\n"); 711 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 712 } 713 714 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); 715 slot->host.f_max = slot->max_clk; 716 slot->host.host_ocr = 0; 717 if (caps & SDHCI_CAN_VDD_330) 718 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 719 if (caps & SDHCI_CAN_VDD_300) 720 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 721 /* 1.8V VDD is not supposed to be used for removable cards */ 722 if ((caps & SDHCI_CAN_VDD_180) && (slot->opt & SDHCI_SLOT_EMBEDDED)) 723 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 724 if (slot->host.host_ocr == 0) { 725 device_printf(dev, "Hardware doesn't report any " 726 "support voltages.\n"); 727 } 728 host_caps = MMC_CAP_4_BIT_DATA; 729 if (caps & SDHCI_CAN_DO_8BITBUS) 730 host_caps |= MMC_CAP_8_BIT_DATA; 731 if (caps & SDHCI_CAN_DO_HISPD) 732 host_caps |= MMC_CAP_HSPEED; 733 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY) 734 host_caps |= MMC_CAP_WAIT_WHILE_BUSY; 735 if (caps2 & (SDHCI_CAN_SDR50 | SDHCI_CAN_SDR104 | SDHCI_CAN_DDR50)) 736 host_caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 737 if (caps2 & SDHCI_CAN_SDR104) { 738 host_caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 739 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200)) 740 host_caps |= MMC_CAP_MMC_HS200; 741 } else if (caps2 & SDHCI_CAN_SDR50) { 742 host_caps |= MMC_CAP_UHS_SDR50; 743 } 744 if ((caps2 & SDHCI_CAN_DDR50) && 745 !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50)) 746 host_caps |= MMC_CAP_UHS_DDR50; 747 if (slot->quirks & SDHCI_QUIRK_MMC_DDR52) 748 host_caps |= MMC_CAP_MMC_DDR52; 749 if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 && 750 caps2 & SDHCI_CAN_MMC_HS400) 751 host_caps |= MMC_CAP_MMC_HS400; 752 host_caps |= MMC_CAP_SIGNALING_330; 753 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 754 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_DDR50 | 755 MMC_CAP_MMC_DDR52_180 | MMC_CAP_MMC_HS200_180 | 756 MMC_CAP_MMC_HS400_180)) 757 host_caps |= MMC_CAP_SIGNALING_180; 758 if (caps2 & SDHCI_CAN_DRIVE_TYPE_A) 759 host_caps |= MMC_CAP_DRIVER_TYPE_A; 760 if (caps2 & SDHCI_CAN_DRIVE_TYPE_C) 761 host_caps |= MMC_CAP_DRIVER_TYPE_C; 762 if (caps2 & SDHCI_CAN_DRIVE_TYPE_D) 763 host_caps |= MMC_CAP_DRIVER_TYPE_D; 764 slot->host.caps = host_caps; 765 766 /* Decide if we have usable DMA. */ 767 if (caps & SDHCI_CAN_DO_DMA) 768 slot->opt |= SDHCI_HAVE_SDMA; 769 if (caps & SDHCI_CAN_DO_ADMA2) 770 slot->opt |= SDHCI_HAVE_ADMA2; 771 772 /* Use ADMA2 only on whitelisted models, or when explicitly enabled. */ 773 if (sdhci_adma2_test == 0 && 774 (slot->quirks & SDHCI_QUIRK_WHITELIST_ADMA2) == 0) { 775 slot->opt &= ~SDHCI_HAVE_ADMA2; 776 } 777 778 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) { 779 slot->opt &= ~SDHCI_HAVE_SDMA; 780 slot->opt &= ~SDHCI_HAVE_ADMA2; 781 } 782 if (slot->quirks & SDHCI_QUIRK_FORCE_SDMA) 783 slot->opt |= SDHCI_HAVE_SDMA; 784 785 if (sdhci_sdma_disable) 786 slot->opt &= ~SDHCI_HAVE_SDMA; 787 if (sdhci_adma2_disable) 788 slot->opt &= ~SDHCI_HAVE_ADMA2; 789 790 /* 791 * Use platform-provided transfer backend 792 * with PIO as a fallback mechanism 793 */ 794 if (slot->opt & SDHCI_PLATFORM_TRANSFER) { 795 slot->opt &= ~SDHCI_HAVE_SDMA; 796 slot->opt &= ~SDHCI_HAVE_ADMA2; 797 } 798 799 if (bootverbose || sdhci_debug) { 800 slot_printf(slot, 801 "%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s%s\n", 802 slot->max_clk / 1000000, 803 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 804 (host_caps & MMC_CAP_8_BIT_DATA) ? "8bits" : 805 ((host_caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"), 806 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 807 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 808 ((caps & SDHCI_CAN_VDD_180) && 809 (slot->opt & SDHCI_SLOT_EMBEDDED)) ? " 1.8V" : "", 810 (host_caps & MMC_CAP_SIGNALING_180) ? " 1.8V" : "", 811 (host_caps & MMC_CAP_SIGNALING_120) ? " 1.2V" : "", 812 (caps2 & SDHCI_CAN_DRIVE_TYPE_A) ? "A" : "", 813 (caps2 & SDHCI_CAN_DRIVE_TYPE_C) ? "C" : "", 814 (caps2 & SDHCI_CAN_DRIVE_TYPE_D) ? "D" : "", 815 (slot->opt & SDHCI_HAVE_ADMA2) ? "ADMA2" : 816 (slot->opt & SDHCI_HAVE_SDMA) ? "SDMA" : "PIO", 817 (slot->version < SDHCI_SPEC_300) ? "" : 818 (slot->opt & SDHCI_SLOT_EMBEDDED) ? " (embedded)" : 819 " (removable)"); 820 if (host_caps & (MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | 821 MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) 822 slot_printf(slot, "eMMC:%s%s%s%s\n", 823 (host_caps & MMC_CAP_MMC_DDR52) ? " DDR52" : "", 824 (host_caps & MMC_CAP_MMC_HS200) ? " HS200" : "", 825 (host_caps & MMC_CAP_MMC_HS400) ? " HS400" : "", 826 ((host_caps & 827 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) == 828 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ? 829 " HS400ES" : ""); 830 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 831 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104)) 832 slot_printf(slot, "UHS-I:%s%s%s%s%s\n", 833 (host_caps & MMC_CAP_UHS_SDR12) ? " SDR12" : "", 834 (host_caps & MMC_CAP_UHS_SDR25) ? " SDR25" : "", 835 (host_caps & MMC_CAP_UHS_SDR50) ? " SDR50" : "", 836 (host_caps & MMC_CAP_UHS_SDR104) ? " SDR104" : "", 837 (host_caps & MMC_CAP_UHS_DDR50) ? " DDR50" : ""); 838 sdhci_dumpregs(slot); 839 } 840 841 slot->timeout = 10; 842 slot->failures = 0; 843 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus), 844 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO, 845 "timeout", CTLFLAG_RW, &slot->timeout, 0, 846 "Maximum timeout for SDHCI transfers (in secs)"); 847 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 848 callout_init_mp(&slot->card_callout); 849 callout_init_lk(&slot->timeout_callout, &slot->lock); 850 return (0); 851 } 852 853 void 854 sdhci_start_slot(struct sdhci_slot *slot) 855 { 856 sdhci_card_task(slot, 0); 857 } 858 859 int 860 sdhci_cleanup_slot(struct sdhci_slot *slot) 861 { 862 device_t d; 863 864 callout_drain(&slot->timeout_callout); 865 callout_drain(&slot->card_callout); 866 taskqueue_drain(taskqueue_swi_mp, &slot->card_task); 867 868 SDHCI_LOCK(slot); 869 d = slot->dev; 870 slot->dev = NULL; 871 SDHCI_UNLOCK(slot); 872 if (d != NULL) 873 device_delete_child(slot->bus, d); 874 875 SDHCI_LOCK(slot); 876 sdhci_reset(slot, SDHCI_RESET_ALL); 877 SDHCI_UNLOCK(slot); 878 879 sdhci_dma_free(slot); 880 881 SDHCI_LOCK_DESTROY(slot); 882 883 return (0); 884 } 885 886 int 887 sdhci_generic_suspend(struct sdhci_slot *slot) 888 { 889 sdhci_reset(slot, SDHCI_RESET_ALL); 890 891 return (0); 892 } 893 894 int 895 sdhci_generic_resume(struct sdhci_slot *slot) 896 { 897 sdhci_init(slot); 898 899 return (0); 900 } 901 902 uint32_t 903 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot) 904 { 905 if (slot->version >= SDHCI_SPEC_300) 906 return (slot->max_clk / SDHCI_300_MAX_DIVIDER); 907 else 908 return (slot->max_clk / SDHCI_200_MAX_DIVIDER); 909 } 910 911 boolean_t 912 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot) 913 { 914 if (slot->opt & SDHCI_SLOT_EMBEDDED) 915 return 1; 916 917 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 918 } 919 920 void 921 sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot) 922 { 923 struct mmc_ios *ios; 924 uint16_t hostctrl2; 925 926 if (slot->version < SDHCI_SPEC_300) 927 return; 928 929 ios = &slot->host.ios; 930 sdhci_set_clock(slot, 0); 931 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 932 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK; 933 if (ios->timing == bus_timing_mmc_hs400 || 934 ios->timing == bus_timing_mmc_hs400es) 935 hostctrl2 |= SDHCI_CTRL2_MMC_HS400; 936 else if (ios->clock > SD_SDR50_MAX) 937 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104; 938 else if (ios->clock > SD_SDR25_MAX) 939 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50; 940 else if (ios->clock > SD_SDR12_MAX) { 941 if (ios->timing == bus_timing_uhs_ddr50 || 942 ios->timing == bus_timing_mmc_ddr52) 943 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50; 944 else 945 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25; 946 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) 947 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12; 948 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 949 sdhci_set_clock(slot, ios->clock); 950 } 951 952 int 953 sdhci_generic_update_ios(device_t brdev, device_t reqdev) 954 { 955 struct sdhci_slot *slot = device_get_ivars(reqdev); 956 struct mmc_ios *ios = &slot->host.ios; 957 958 SDHCI_LOCK(slot); 959 /* Do full reset on bus power down to clear from any state. */ 960 if (ios->power_mode == power_off) { 961 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 962 sdhci_init(slot); 963 } 964 /* Configure the bus. */ 965 sdhci_set_clock(slot, ios->clock); 966 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 967 if (ios->bus_width == bus_width_8) { 968 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 969 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 970 } else if (ios->bus_width == bus_width_4) { 971 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 972 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 973 } else if (ios->bus_width == bus_width_1) { 974 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 975 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 976 } else { 977 panic("Invalid bus width: %d", ios->bus_width); 978 } 979 if (ios->clock > SD_SDR12_MAX && 980 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 981 slot->hostctrl |= SDHCI_CTRL_HISPD; 982 else 983 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 984 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 985 SDHCI_SET_UHS_TIMING(brdev, slot); 986 /* Some controllers like reset after bus changes. */ 987 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 988 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 989 990 SDHCI_UNLOCK(slot); 991 return (0); 992 } 993 994 int 995 sdhci_generic_switch_vccq(device_t brdev __unused, device_t reqdev) 996 { 997 struct sdhci_slot *slot = device_get_ivars(reqdev); 998 enum mmc_vccq vccq; 999 int err; 1000 uint16_t hostctrl2; 1001 1002 if (slot->version < SDHCI_SPEC_300) 1003 return (0); 1004 1005 err = 0; 1006 vccq = slot->host.ios.vccq; 1007 SDHCI_LOCK(slot); 1008 sdhci_set_clock(slot, 0); 1009 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1010 switch (vccq) { 1011 case vccq_330: 1012 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 1013 goto done; 1014 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE; 1015 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1016 DELAY(5000); 1017 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1018 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 1019 goto done; 1020 err = EAGAIN; 1021 break; 1022 case vccq_180: 1023 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) { 1024 err = EINVAL; 1025 goto done; 1026 } 1027 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 1028 goto done; 1029 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE; 1030 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1031 DELAY(5000); 1032 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1033 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 1034 goto done; 1035 err = EAGAIN; 1036 break; 1037 default: 1038 slot_printf(slot, 1039 "Attempt to set unsupported signaling voltage\n"); 1040 err = EINVAL; 1041 break; 1042 } 1043 done: 1044 sdhci_set_clock(slot, slot->host.ios.clock); 1045 SDHCI_UNLOCK(slot); 1046 return (err); 1047 } 1048 1049 static void 1050 sdhci_req_done(struct sdhci_slot *slot) 1051 { 1052 struct mmc_request *req; 1053 1054 if (slot->req != NULL && slot->curcmd != NULL) { 1055 callout_stop(&slot->timeout_callout); 1056 if (slot->curcmd->error != MMC_ERR_TIMEOUT) 1057 slot->failures = 0; 1058 req = slot->req; 1059 slot->req = NULL; 1060 slot->curcmd = NULL; 1061 req->done(req); 1062 } 1063 } 1064 1065 static void 1066 sdhci_timeout(void *arg) 1067 { 1068 struct sdhci_slot *slot = arg; 1069 1070 if (slot->curcmd != NULL) { 1071 slot_printf(slot, " Controller timeout\n"); 1072 sdhci_dumpregs(slot); 1073 sdhci_reset(slot, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 1074 slot->curcmd->error = MMC_ERR_TIMEOUT; 1075 sdhci_req_done(slot); 1076 } else { 1077 slot_printf(slot, " Spurious timeout - no active command\n"); 1078 } 1079 } 1080 1081 static void 1082 sdhci_set_transfer_mode(struct sdhci_slot *slot, struct mmc_data *data) 1083 { 1084 uint16_t mode; 1085 1086 if (data == NULL) 1087 return; 1088 1089 mode = SDHCI_TRNS_BLK_CNT_EN; 1090 if (data->len > 512) 1091 mode |= SDHCI_TRNS_MULTI; 1092 if (data->flags & MMC_DATA_READ) 1093 mode |= SDHCI_TRNS_READ; 1094 if (slot->req->stop) 1095 mode |= SDHCI_TRNS_ACMD12; 1096 if (slot->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA2)) 1097 mode |= SDHCI_TRNS_DMA; 1098 1099 WR2(slot, SDHCI_TRANSFER_MODE, mode); 1100 } 1101 1102 static void 1103 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 1104 { 1105 int flags, timeout; 1106 uint32_t mask; 1107 1108 slot->curcmd = cmd; 1109 slot->cmd_done = 0; 1110 1111 cmd->error = MMC_ERR_NONE; 1112 1113 /* This flags combination is not supported by controller. */ 1114 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1115 slot_printf(slot, "Unsupported response type!\n"); 1116 cmd->error = MMC_ERR_FAILED; 1117 sdhci_req_done(slot); 1118 return; 1119 } 1120 1121 /* 1122 * Do not issue command if there is no card, clock or power. 1123 * Controller will not detect timeout without clock active. 1124 */ 1125 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) || 1126 slot->power == 0 || 1127 slot->clock == 0) { 1128 cmd->error = MMC_ERR_FAILED; 1129 sdhci_req_done(slot); 1130 return; 1131 } 1132 /* Always wait for free CMD bus. */ 1133 mask = SDHCI_CMD_INHIBIT; 1134 /* Wait for free DAT if we have data or busy signal. */ 1135 if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) 1136 mask |= SDHCI_DAT_INHIBIT; 1137 /* We shouldn't wait for DAT for stop commands. */ 1138 if (cmd == slot->req->stop) 1139 mask &= ~SDHCI_DAT_INHIBIT; 1140 /* 1141 * Wait for bus no more then 250 ms. Typically there will be no wait 1142 * here at all, but when writing a crash dump we may be bypassing the 1143 * host platform's interrupt handler, and in some cases that handler 1144 * may be working around hardware quirks such as not respecting r1b 1145 * busy indications. In those cases, this wait-loop serves the purpose 1146 * of waiting for the prior command and data transfers to be done, and 1147 * SD cards are allowed to take up to 250ms for write and erase ops. 1148 * (It's usually more like 20-30ms in the real world.) 1149 */ 1150 timeout = 250; 1151 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) { 1152 if (timeout == 0) { 1153 slot_printf(slot, "Controller never released " 1154 "inhibit bit(s).\n"); 1155 sdhci_dumpregs(slot); 1156 cmd->error = MMC_ERR_FAILED; 1157 sdhci_req_done(slot); 1158 return; 1159 } 1160 timeout--; 1161 DELAY(1000); 1162 } 1163 1164 /* Prepare command flags. */ 1165 if (!(cmd->flags & MMC_RSP_PRESENT)) 1166 flags = SDHCI_CMD_RESP_NONE; 1167 else if (cmd->flags & MMC_RSP_136) 1168 flags = SDHCI_CMD_RESP_LONG; 1169 else if (cmd->flags & MMC_RSP_BUSY) 1170 flags = SDHCI_CMD_RESP_SHORT_BUSY; 1171 else 1172 flags = SDHCI_CMD_RESP_SHORT; 1173 if (cmd->flags & MMC_RSP_CRC) 1174 flags |= SDHCI_CMD_CRC; 1175 if (cmd->flags & MMC_RSP_OPCODE) 1176 flags |= SDHCI_CMD_INDEX; 1177 if (cmd->data) 1178 flags |= SDHCI_CMD_DATA; 1179 if (cmd->opcode == MMC_STOP_TRANSMISSION) 1180 flags |= SDHCI_CMD_TYPE_ABORT; 1181 /* Prepare data. */ 1182 sdhci_start_data(slot, cmd->data); 1183 /* 1184 * Interrupt aggregation: To reduce total number of interrupts 1185 * group response interrupt with data interrupt when possible. 1186 * If there is going to be a data interrupt, mask the response one. 1187 */ 1188 if (slot->data_done == 0) { 1189 WR4(slot, SDHCI_SIGNAL_ENABLE, 1190 slot->intmask &= ~SDHCI_INT_RESPONSE); 1191 } 1192 /* Set command argument. */ 1193 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 1194 /* Set data transfer mode. */ 1195 sdhci_set_transfer_mode(slot, cmd->data); 1196 /* Start command. */ 1197 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 1198 1199 /* 1200 * Start timeout callout. Timeout is dropped to 2 seconds with 1201 * repeated controller timeouts. 1202 */ 1203 if (slot->failures) 1204 timeout = slot->timeout / 5; 1205 else 1206 timeout = slot->timeout; 1207 if (timeout < 2) 1208 timeout = 2; 1209 callout_reset(&slot->timeout_callout, timeout * hz, 1210 sdhci_timeout, slot); 1211 } 1212 1213 static void 1214 sdhci_finish_command(struct sdhci_slot *slot) 1215 { 1216 int i; 1217 1218 slot->cmd_done = 1; 1219 /* Interrupt aggregation: Restore command interrupt. 1220 * Main restore point for the case when command interrupt 1221 * happened first. */ 1222 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 1223 /* In case of error - reset host and return. */ 1224 if (slot->curcmd->error) { 1225 sdhci_reset(slot, SDHCI_RESET_CMD); 1226 sdhci_reset(slot, SDHCI_RESET_DATA); 1227 sdhci_start(slot); 1228 return; 1229 } 1230 /* If command has response - fetch it. */ 1231 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 1232 if (slot->curcmd->flags & MMC_RSP_136) { 1233 /* CRC is stripped so we need one byte shift. */ 1234 uint8_t extra = 0; 1235 for (i = 0; i < 4; i++) { 1236 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4); 1237 if (slot->quirks & SDHCI_QUIRK_DONT_SHIFT_RESPONSE) { 1238 slot->curcmd->resp[3 - i] = val; 1239 } else { 1240 slot->curcmd->resp[3 - i] = 1241 (val << 8) | extra; 1242 extra = val >> 24; 1243 } 1244 } 1245 } else { 1246 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 1247 } 1248 } 1249 /* If data ready - finish. */ 1250 if (slot->data_done) 1251 sdhci_start(slot); 1252 } 1253 1254 static void 1255 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 1256 { 1257 uint32_t target_timeout, current_timeout; 1258 uint8_t div; 1259 1260 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1261 slot->data_done = 1; 1262 return; 1263 } 1264 1265 slot->data_done = 0; 1266 1267 /* Calculate and set data timeout.*/ 1268 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 1269 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { 1270 div = 0xe; 1271 } else { 1272 target_timeout = 1000000; 1273 div = 0; 1274 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 1275 while (current_timeout < target_timeout && div < 0xE) { 1276 ++div; 1277 current_timeout <<= 1; 1278 } 1279 /* Compensate for an off-by-one error in the CaFe chip.*/ 1280 if (div < 0xE && 1281 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) { 1282 ++div; 1283 } 1284 } 1285 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 1286 1287 if (data == NULL) 1288 return; 1289 1290 /* Use DMA if possible. Prefer ADMA2 over SDMA. */ 1291 if ((slot->opt & SDHCI_HAVE_ADMA2)) { 1292 slot->flags |= SDHCI_USE_ADMA2; 1293 slot->flags &= ~SDHCI_USE_SDMA; 1294 } else if ((slot->opt & SDHCI_HAVE_SDMA)) { 1295 slot->flags |= SDHCI_USE_SDMA; 1296 slot->flags &= ~SDHCI_USE_ADMA2; 1297 } 1298 /* If data is small, broken DMA may return zeroes instead of data. */ 1299 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 1300 (data->len <= 512)) { 1301 slot->flags &= ~SDHCI_USE_SDMA; 1302 slot->flags &= ~SDHCI_USE_ADMA2; 1303 } 1304 /* Some controllers require even block sizes. */ 1305 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 1306 ((data->len) & 0x3)) { 1307 slot->flags &= ~SDHCI_USE_SDMA; 1308 slot->flags &= ~SDHCI_USE_ADMA2; 1309 } 1310 /* Load DMA buffer. */ 1311 if (slot->flags & SDHCI_USE_ADMA2) { 1312 bus_dmamem_t *descmem = &slot->adma2_descs; 1313 struct sdhci_adma2_desc32 *descs = (void *)descmem->dmem_addr; 1314 int err; 1315 1316 /* It shouldn't really be possible for this to fail */ 1317 err = bus_dmamap_load(slot->adma2_tag, slot->adma2_map, 1318 data->data, data->len, sdhci_adma2_getaddr, slot, 1319 dumping ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 1320 if (err != 0) { 1321 device_printf(slot->bus, 1322 "Dma load for ADMA2 fail: %d\n", err); 1323 } else if (descs[0].address == 0) { 1324 device_printf(slot->bus, 1325 "Dma load for ADMA2 fail, segment constraints\n"); 1326 } 1327 if (err != 0 || descs[0].address == 0) { 1328 /* fallback to PIO for this request */ 1329 slot->flags &= ~SDHCI_USE_ADMA2; 1330 goto pio_fallback; 1331 } 1332 /* sync dma descriptors */ 1333 bus_dmamap_sync(descmem->dmem_tag, descmem->dmem_map, 1334 BUS_DMASYNC_PREWRITE); 1335 /* sync data buffers */ 1336 if (data->flags & MMC_DATA_READ) { 1337 bus_dmamap_sync(slot->adma2_tag, slot->adma2_map, 1338 BUS_DMASYNC_PREREAD); 1339 } else { 1340 bus_dmamap_sync(slot->adma2_tag, slot->adma2_map, 1341 BUS_DMASYNC_PREWRITE); 1342 } 1343 WR4(slot, SDHCI_ADMA_ADDRESS_LOW, descmem->dmem_busaddr); 1344 if ((slot->hostctrl & SDHCI_CTRL_DMA_MASK) != 1345 SDHCI_CTRL_ADMA2) { 1346 slot->hostctrl &= ~SDHCI_CTRL_DMA_MASK; 1347 slot->hostctrl |= SDHCI_CTRL_ADMA2; 1348 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 1349 } 1350 /* We don't expect any DMA_END interrupts with ADMA2 */ 1351 WR4(slot, SDHCI_SIGNAL_ENABLE, 1352 slot->intmask &= ~SDHCI_INT_DMA_END); 1353 } else if (slot->flags & SDHCI_USE_SDMA) { 1354 bus_dmamem_t *sdma = &slot->sdma_mem; 1355 1356 if (data->flags & MMC_DATA_READ) { 1357 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map, 1358 BUS_DMASYNC_PREREAD); 1359 } else { 1360 memcpy(sdma->dmem_addr, data->data, 1361 (data->len < DMA_BLOCK_SIZE) ? 1362 data->len : DMA_BLOCK_SIZE); 1363 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map, 1364 BUS_DMASYNC_PREWRITE); 1365 } 1366 WR4(slot, SDHCI_SDMA_ADDRESS, sdma->dmem_busaddr); 1367 if ((slot->hostctrl & SDHCI_CTRL_DMA_MASK) != 1368 SDHCI_CTRL_SDMA) { 1369 slot->hostctrl &= ~SDHCI_CTRL_DMA_MASK; 1370 slot->hostctrl |= SDHCI_CTRL_SDMA; 1371 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 1372 } 1373 /* Interrupt aggregation: Mask border interrupt 1374 * for the last page and unmask else. */ 1375 if (data->len == DMA_BLOCK_SIZE) 1376 slot->intmask &= ~SDHCI_INT_DMA_END; 1377 else 1378 slot->intmask |= SDHCI_INT_DMA_END; 1379 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1380 } 1381 pio_fallback: 1382 /* Current data offset for both PIO and SDMA. */ 1383 slot->offset = 0; 1384 /* Set block size and for SDMA request IRQ on 4K border. */ 1385 WR2(slot, SDHCI_BLOCK_SIZE, 1386 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512)); 1387 /* Set block count. */ 1388 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 1389 } 1390 1391 void 1392 sdhci_finish_data(struct sdhci_slot *slot) 1393 { 1394 struct mmc_data *data = slot->curcmd->data; 1395 1396 /* Interrupt aggregation: Restore command interrupt. 1397 * Auxiliary restore point for the case when data interrupt 1398 * happened first. */ 1399 if (!slot->cmd_done) { 1400 WR4(slot, SDHCI_SIGNAL_ENABLE, 1401 slot->intmask |= SDHCI_INT_RESPONSE); 1402 } 1403 /* Unload rest of data from DMA buffer. */ 1404 if (!slot->data_done && (slot->flags & SDHCI_USE_ADMA2)) { 1405 bus_dmamem_t *descmem = &slot->adma2_descs; 1406 1407 bus_dmamap_sync(descmem->dmem_tag, descmem->dmem_map, 1408 BUS_DMASYNC_POSTWRITE); 1409 if (data->flags & MMC_DATA_READ) { 1410 bus_dmamap_sync(slot->adma2_tag, slot->adma2_map, 1411 BUS_DMASYNC_POSTREAD); 1412 } else { 1413 bus_dmamap_sync(slot->adma2_tag, slot->adma2_map, 1414 BUS_DMASYNC_POSTWRITE); 1415 } 1416 bus_dmamap_unload(slot->adma2_tag, slot->adma2_map); 1417 } else if (!slot->data_done && (slot->flags & SDHCI_USE_SDMA)) { 1418 bus_dmamem_t *sdma = &slot->sdma_mem; 1419 1420 if (data->flags & MMC_DATA_READ) { 1421 size_t left = data->len - slot->offset; 1422 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map, 1423 BUS_DMASYNC_POSTREAD); 1424 memcpy((u_char*)data->data + slot->offset, 1425 sdma->dmem_addr, 1426 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1427 } else { 1428 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map, 1429 BUS_DMASYNC_POSTWRITE); 1430 } 1431 } 1432 slot->data_done = 1; 1433 /* If there was an error - reset the host. */ 1434 if (slot->curcmd->error) { 1435 sdhci_reset(slot, SDHCI_RESET_CMD); 1436 sdhci_reset(slot, SDHCI_RESET_DATA); 1437 sdhci_start(slot); 1438 return; 1439 } 1440 /* If we already have command response - finish. */ 1441 if (slot->cmd_done) 1442 sdhci_start(slot); 1443 } 1444 1445 static void 1446 sdhci_start(struct sdhci_slot *slot) 1447 { 1448 struct mmc_request *req; 1449 1450 req = slot->req; 1451 if (req == NULL) 1452 return; 1453 1454 if (!(slot->flags & CMD_STARTED)) { 1455 slot->flags |= CMD_STARTED; 1456 sdhci_start_command(slot, req->cmd); 1457 return; 1458 } 1459 /* We don't need this until using Auto-CMD12 feature 1460 if (!(slot->flags & STOP_STARTED) && req->stop) { 1461 slot->flags |= STOP_STARTED; 1462 sdhci_start_command(slot, req->stop); 1463 return; 1464 } 1465 */ 1466 if (sdhci_debug > 1) 1467 slot_printf(slot, "result: %d\n", req->cmd->error); 1468 if (!req->cmd->error && 1469 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 1470 sdhci_reset(slot, SDHCI_RESET_CMD); 1471 sdhci_reset(slot, SDHCI_RESET_DATA); 1472 } 1473 1474 sdhci_req_done(slot); 1475 } 1476 1477 int 1478 sdhci_generic_request(device_t brdev __unused, device_t reqdev, 1479 struct mmc_request *req) 1480 { 1481 struct sdhci_slot *slot = device_get_ivars(reqdev); 1482 1483 SDHCI_LOCK(slot); 1484 if (slot->req != NULL) { 1485 SDHCI_UNLOCK(slot); 1486 return (EBUSY); 1487 } 1488 if (sdhci_debug > 1) { 1489 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1490 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 1491 (req->cmd->data)?(u_int)req->cmd->data->len:0, 1492 (req->cmd->data)?req->cmd->data->flags:0); 1493 } 1494 slot->req = req; 1495 slot->flags = 0; 1496 sdhci_start(slot); 1497 SDHCI_UNLOCK(slot); 1498 if (dumping) { 1499 while (slot->req != NULL) { 1500 sdhci_generic_intr(slot); 1501 DELAY(10); 1502 } 1503 } 1504 return (0); 1505 } 1506 1507 int 1508 sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev) 1509 { 1510 struct sdhci_slot *slot = device_get_ivars(reqdev); 1511 uint32_t val; 1512 1513 SDHCI_LOCK(slot); 1514 val = RD4(slot, SDHCI_PRESENT_STATE); 1515 SDHCI_UNLOCK(slot); 1516 return (!(val & SDHCI_WRITE_PROTECT)); 1517 } 1518 1519 int 1520 sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev) 1521 { 1522 struct sdhci_slot *slot = device_get_ivars(reqdev); 1523 int err = 0; 1524 1525 SDHCI_LOCK(slot); 1526 while (slot->bus_busy) 1527 lksleep(slot, &slot->lock, 0, "sdhciah", 0); 1528 slot->bus_busy++; 1529 /* Activate led. */ 1530 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1531 SDHCI_UNLOCK(slot); 1532 return (err); 1533 } 1534 1535 int 1536 sdhci_generic_release_host(device_t brdev __unused, device_t reqdev) 1537 { 1538 struct sdhci_slot *slot = device_get_ivars(reqdev); 1539 1540 SDHCI_LOCK(slot); 1541 /* Deactivate led. */ 1542 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 1543 slot->bus_busy--; 1544 SDHCI_UNLOCK(slot); 1545 wakeup(slot); 1546 return (0); 1547 } 1548 1549 static void 1550 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1551 { 1552 1553 if (!slot->curcmd) { 1554 slot_printf(slot, "Got command interrupt 0x%08x, but " 1555 "there is no active command.\n", intmask); 1556 sdhci_dumpregs(slot); 1557 return; 1558 } 1559 if (intmask & SDHCI_INT_TIMEOUT) 1560 slot->curcmd->error = MMC_ERR_TIMEOUT; 1561 else if (intmask & SDHCI_INT_CRC) 1562 slot->curcmd->error = MMC_ERR_BADCRC; 1563 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1564 slot->curcmd->error = MMC_ERR_FIFO; 1565 1566 sdhci_finish_command(slot); 1567 } 1568 1569 static void 1570 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1571 { 1572 1573 if (!slot->curcmd) { 1574 slot_printf(slot, "Got data interrupt 0x%08x, but " 1575 "there is no active command.\n", intmask); 1576 sdhci_dumpregs(slot); 1577 return; 1578 } 1579 if (slot->curcmd->data == NULL && 1580 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1581 slot_printf(slot, "Got data interrupt 0x%08x, but " 1582 "there is no active data operation.\n", 1583 intmask); 1584 sdhci_dumpregs(slot); 1585 return; 1586 } 1587 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1588 slot->curcmd->error = MMC_ERR_TIMEOUT; 1589 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1590 slot->curcmd->error = MMC_ERR_BADCRC; 1591 if (slot->curcmd->data == NULL && 1592 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1593 SDHCI_INT_DMA_END))) { 1594 slot_printf(slot, "Got data interrupt 0x%08x, but " 1595 "there is busy-only command.\n", intmask); 1596 sdhci_dumpregs(slot); 1597 slot->curcmd->error = MMC_ERR_INVALID; 1598 } 1599 if (slot->curcmd->error) { 1600 /* No need to continue after any error. */ 1601 goto done; 1602 } 1603 1604 /* Handle PIO interrupt. */ 1605 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { 1606 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) && 1607 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) { 1608 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, &intmask); 1609 slot->flags |= PLATFORM_DATA_STARTED; 1610 } else 1611 sdhci_transfer_pio(slot); 1612 } 1613 /* Handle DMA border. */ 1614 if (intmask & SDHCI_INT_DMA_END) { 1615 struct mmc_data *data = slot->curcmd->data; 1616 bus_dmamem_t *sdma = &slot->sdma_mem; 1617 size_t left; 1618 1619 /* Unload DMA buffer ... */ 1620 left = data->len - slot->offset; 1621 if (data->flags & MMC_DATA_READ) { 1622 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map, 1623 BUS_DMASYNC_POSTREAD); 1624 memcpy((u_char*)data->data + slot->offset, 1625 sdma->dmem_addr, 1626 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1627 } else { 1628 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map, 1629 BUS_DMASYNC_POSTWRITE); 1630 } 1631 /* ... and reload it again. */ 1632 slot->offset += DMA_BLOCK_SIZE; 1633 left = data->len - slot->offset; 1634 if (data->flags & MMC_DATA_READ) { 1635 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map, 1636 BUS_DMASYNC_PREREAD); 1637 } else { 1638 memcpy(sdma->dmem_addr, 1639 (u_char*)data->data + slot->offset, 1640 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1641 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map, 1642 BUS_DMASYNC_PREWRITE); 1643 } 1644 /* Interrupt aggregation: Mask border interrupt 1645 * for the last page. */ 1646 if (left == DMA_BLOCK_SIZE) { 1647 slot->intmask &= ~SDHCI_INT_DMA_END; 1648 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1649 } 1650 /* Restart DMA. */ 1651 WR4(slot, SDHCI_SDMA_ADDRESS, sdma->dmem_busaddr); 1652 } 1653 /* We have got all data. */ 1654 if (intmask & SDHCI_INT_DATA_END) { 1655 if (slot->flags & PLATFORM_DATA_STARTED) { 1656 slot->flags &= ~PLATFORM_DATA_STARTED; 1657 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1658 } else { 1659 sdhci_finish_data(slot); 1660 } 1661 } 1662 done: 1663 if (slot->curcmd != NULL && slot->curcmd->error != 0) { 1664 if (slot->flags & PLATFORM_DATA_STARTED) { 1665 slot->flags &= ~PLATFORM_DATA_STARTED; 1666 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1667 } else { 1668 sdhci_finish_data(slot); 1669 } 1670 return; 1671 } 1672 } 1673 1674 static void 1675 sdhci_acmd_irq(struct sdhci_slot *slot) 1676 { 1677 uint16_t err; 1678 1679 err = RD4(slot, SDHCI_ACMD12_ERR); 1680 if (!slot->curcmd) { 1681 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1682 "there is no active command.\n", err); 1683 sdhci_dumpregs(slot); 1684 return; 1685 } 1686 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1687 sdhci_reset(slot, SDHCI_RESET_CMD); 1688 } 1689 1690 static void 1691 sdhci_adma_irq(struct sdhci_slot *slot) 1692 { 1693 bus_dmamem_t *descmem = &slot->adma2_descs; 1694 struct sdhci_adma2_desc32 *desc; 1695 bus_addr_t addr = 0; 1696 uint8_t err, adma_state; 1697 1698 err = RD1(slot, SDHCI_ADMA_ERR); 1699 if (slot->curcmd && (slot->flags & SDHCI_USE_ADMA2)) { 1700 slot_printf(slot, "Got ADMA2 error 0x%02x\n", err); 1701 } else { 1702 slot_printf(slot, "Got ADMA2 error 0x%02x, but " 1703 "there is no active command.\n", err); 1704 sdhci_dumpregs(slot); 1705 } 1706 1707 /* Try to print the erronous ADMA2 descriptor */ 1708 adma_state = err & SDHCI_ADMA_ERR_STATE_MASK; 1709 if (adma_state == SDHCI_ADMA_ERR_STATE_STOP) { 1710 addr = RD4(slot, SDHCI_ADMA_ADDRESS_LOW); 1711 if (addr > sizeof(*desc)) 1712 addr -= sizeof(*desc); 1713 else 1714 addr = 0; 1715 } else if (adma_state == SDHCI_ADMA_ERR_STATE_FDS) { 1716 addr = RD4(slot, SDHCI_ADMA_ADDRESS_LOW); 1717 } else if (adma_state == SDHCI_ADMA_ERR_STATE_TFR) { 1718 addr = RD4(slot, SDHCI_ADMA_ADDRESS_LOW); 1719 if (addr > sizeof(*desc)) 1720 addr -= sizeof(*desc); 1721 else 1722 addr = 0; 1723 } else { 1724 slot_printf(slot, "Invalid ADMA2 state 0x%02x\n", adma_state); 1725 } 1726 if (addr >= descmem->dmem_busaddr && 1727 addr < descmem->dmem_busaddr + SDHCI_ADMA2_DESCBUF_SIZE) { 1728 desc = (void *) ((char *)descmem->dmem_addr + 1729 (addr - descmem->dmem_busaddr)); 1730 slot_printf(slot, 1731 "Descriptor: Addr=0x%08x Length=0x%04x Attr=0x%04x\n", 1732 desc->address, desc->length, desc->attribute); 1733 } 1734 1735 if (slot->curcmd && (slot->flags & SDHCI_USE_ADMA2)) { 1736 sdhci_reset(slot, SDHCI_RESET_CMD); 1737 } 1738 } 1739 1740 void 1741 sdhci_generic_intr(struct sdhci_slot *slot) 1742 { 1743 uint32_t intmask; 1744 1745 SDHCI_LOCK(slot); 1746 /* Read slot interrupt status. */ 1747 intmask = RD4(slot, SDHCI_INT_STATUS); 1748 if (intmask == 0 || intmask == 0xffffffff) { 1749 SDHCI_UNLOCK(slot); 1750 return; 1751 } 1752 if (sdhci_debug > 2) 1753 slot_printf(slot, "Interrupt %#x\n", intmask); 1754 1755 /* Handle card presence interrupts. */ 1756 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1757 WR4(slot, SDHCI_INT_STATUS, intmask & 1758 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1759 1760 if (intmask & SDHCI_INT_CARD_REMOVE) { 1761 if (bootverbose || sdhci_debug) 1762 slot_printf(slot, "Card removed\n"); 1763 callout_stop(&slot->card_callout); 1764 taskqueue_enqueue(taskqueue_swi_mp, &slot->card_task); 1765 } 1766 if (intmask & SDHCI_INT_CARD_INSERT) { 1767 if (bootverbose || sdhci_debug) 1768 slot_printf(slot, "Card inserted\n"); 1769 callout_reset(&slot->card_callout, hz / 2, 1770 sdhci_card_delay, slot); 1771 } 1772 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1773 } 1774 /* Handle command interrupts. */ 1775 if (intmask & SDHCI_INT_CMD_MASK) { 1776 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1777 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1778 } 1779 /* Handle data interrupts. */ 1780 if (intmask & SDHCI_INT_DATA_MASK) { 1781 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1782 /* Dont call data_irq in case of errored command */ 1783 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0) 1784 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1785 } 1786 /* Handle AutoCMD12 error interrupt. */ 1787 if (intmask & SDHCI_INT_ACMD12ERR) { 1788 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1789 sdhci_acmd_irq(slot); 1790 } 1791 /* Handle ADMA2 error interrupt. */ 1792 if (intmask & SDHCI_INT_ADMAERR) { 1793 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ADMAERR); 1794 sdhci_adma_irq(slot); 1795 } 1796 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1797 intmask &= ~SDHCI_INT_ACMD12ERR; 1798 intmask &= ~SDHCI_INT_ADMAERR; 1799 intmask &= ~SDHCI_INT_ERROR; 1800 /* Handle bus power interrupt. */ 1801 if (intmask & SDHCI_INT_BUS_POWER) { 1802 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1803 slot_printf(slot, 1804 "Card is consuming too much power!\n"); 1805 intmask &= ~SDHCI_INT_BUS_POWER; 1806 } 1807 /* The rest is unknown. */ 1808 if (intmask) { 1809 WR4(slot, SDHCI_INT_STATUS, intmask); 1810 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1811 intmask); 1812 sdhci_dumpregs(slot); 1813 } 1814 1815 SDHCI_UNLOCK(slot); 1816 } 1817 1818 int 1819 sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 1820 { 1821 struct sdhci_slot *slot = device_get_ivars(child); 1822 1823 switch (which) { 1824 default: 1825 return (EINVAL); 1826 case MMCBR_IVAR_BUS_MODE: 1827 *(int *)result = slot->host.ios.bus_mode; 1828 break; 1829 case MMCBR_IVAR_BUS_WIDTH: 1830 *(int *)result = slot->host.ios.bus_width; 1831 break; 1832 case MMCBR_IVAR_CHIP_SELECT: 1833 *(int *)result = slot->host.ios.chip_select; 1834 break; 1835 case MMCBR_IVAR_CLOCK: 1836 *(int *)result = slot->host.ios.clock; 1837 break; 1838 case MMCBR_IVAR_F_MIN: 1839 *(int *)result = slot->host.f_min; 1840 break; 1841 case MMCBR_IVAR_F_MAX: 1842 *(int *)result = slot->host.f_max; 1843 break; 1844 case MMCBR_IVAR_HOST_OCR: 1845 *(int *)result = slot->host.host_ocr; 1846 break; 1847 case MMCBR_IVAR_MODE: 1848 *(int *)result = slot->host.mode; 1849 break; 1850 case MMCBR_IVAR_OCR: 1851 *(int *)result = slot->host.ocr; 1852 break; 1853 case MMCBR_IVAR_POWER_MODE: 1854 *(int *)result = slot->host.ios.power_mode; 1855 break; 1856 case MMCBR_IVAR_VDD: 1857 *(int *)result = slot->host.ios.vdd; 1858 break; 1859 case MMCBR_IVAR_VCCQ: 1860 *result = slot->host.ios.vccq; 1861 break; 1862 case MMCBR_IVAR_CAPS: 1863 *(int *)result = slot->host.caps; 1864 break; 1865 case MMCBR_IVAR_TIMING: 1866 *(int *)result = slot->host.ios.timing; 1867 break; 1868 case MMCBR_IVAR_MAX_DATA: 1869 *(int *)result = 65535; 1870 break; 1871 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: 1872 /* 1873 * Currently, sdhci_start_data() hardcodes 1 s for all CMDs. 1874 */ 1875 *result = 1000000; 1876 break; 1877 } 1878 return (0); 1879 } 1880 1881 int 1882 sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1883 { 1884 struct sdhci_slot *slot = device_get_ivars(child); 1885 uint32_t clock, max_clock; 1886 int i; 1887 1888 switch (which) { 1889 default: 1890 return (EINVAL); 1891 case MMCBR_IVAR_BUS_MODE: 1892 slot->host.ios.bus_mode = value; 1893 break; 1894 case MMCBR_IVAR_BUS_WIDTH: 1895 slot->host.ios.bus_width = value; 1896 break; 1897 case MMCBR_IVAR_CHIP_SELECT: 1898 slot->host.ios.chip_select = value; 1899 break; 1900 case MMCBR_IVAR_CLOCK: 1901 if (value > 0) { 1902 max_clock = slot->max_clk; 1903 clock = max_clock; 1904 1905 if (slot->version < SDHCI_SPEC_300) { 1906 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 1907 i <<= 1) { 1908 if (clock <= value) 1909 break; 1910 clock >>= 1; 1911 } 1912 } else { 1913 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 1914 i += 2) { 1915 if (clock <= value) 1916 break; 1917 clock = max_clock / (i + 2); 1918 } 1919 } 1920 1921 slot->host.ios.clock = clock; 1922 } else 1923 slot->host.ios.clock = 0; 1924 break; 1925 case MMCBR_IVAR_MODE: 1926 slot->host.mode = value; 1927 break; 1928 case MMCBR_IVAR_OCR: 1929 slot->host.ocr = value; 1930 break; 1931 case MMCBR_IVAR_POWER_MODE: 1932 slot->host.ios.power_mode = value; 1933 break; 1934 case MMCBR_IVAR_VDD: 1935 slot->host.ios.vdd = value; 1936 break; 1937 case MMCBR_IVAR_VCCQ: 1938 slot->host.ios.vccq = value; 1939 break; 1940 case MMCBR_IVAR_TIMING: 1941 slot->host.ios.timing = value; 1942 break; 1943 case MMCBR_IVAR_CAPS: 1944 case MMCBR_IVAR_HOST_OCR: 1945 case MMCBR_IVAR_F_MIN: 1946 case MMCBR_IVAR_F_MAX: 1947 case MMCBR_IVAR_MAX_DATA: 1948 return (EINVAL); 1949 } 1950 return (0); 1951 } 1952 1953 MODULE_VERSION(sdhci, 1); 1954