1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * $FreeBSD: src/sys/dev/sdhci/sdhci.c,v 1.8 2009/02/17 19:12:15 mav Exp $ 26 */ 27 28 #include <stdarg.h> 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/callout.h> 34 #include <sys/conf.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/module.h> 38 #include <sys/spinlock.h> 39 #include <sys/resource.h> 40 #include <sys/rman.h> 41 #include <sys/sysctl.h> 42 #include <sys/taskqueue.h> 43 44 #include <bus/mmc/bridge.h> 45 #include <bus/mmc/mmcreg.h> 46 #include <bus/mmc/mmcbrvar.h> 47 48 #include "mmcbr_if.h" 49 #include "sdhci.h" 50 #include "sdhci_if.h" 51 52 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 53 54 int sdhci_debug = 0; 55 TUNABLE_INT("hw.sdhci.debug", &sdhci_debug); 56 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level"); 57 58 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 59 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 60 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 61 #define RD_MULTI_4(slot, off, ptr, count) \ 62 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 63 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 64 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 65 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 66 #define WR_MULTI_4(slot, off, ptr, count) \ 67 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 68 69 static int slot_printf(struct sdhci_slot *, const char *, ...) 70 __printflike(2, 3); 71 72 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 73 static void sdhci_start(struct sdhci_slot *slot); 74 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 75 76 static void sdhci_card_task(void *, int); 77 78 /* helper routines */ 79 #define SDHCI_LOCK(_slot) lockmgr(&(_slot)->lock, LK_EXCLUSIVE) 80 #define SDHCI_UNLOCK(_slot) lockmgr(&(_slot)->lock, LK_RELEASE) 81 #define SDHCI_LOCK_INIT(_slot) lockinit(&(_slot)->lock, "sdhci", 0, LK_CANRECURSE) 82 #define SDHCI_LOCK_DESTROY(_slot) lockuninit(&(_slot)->lock); 83 #define SDHCI_ASSERT_LOCKED(_slot) KKASSERT(lockstatus(&(_slot)->lock, curthread) != 0); 84 #define SDHCI_ASSERT_UNLOCKED(_slot) KKASSERT(lockstatus(&(_slot)->lock, curthread) == 0); 85 86 #define SDHCI_DEFAULT_MAX_FREQ 50 87 88 #define SDHCI_200_MAX_DIVIDER 256 89 #define SDHCI_300_MAX_DIVIDER 2046 90 91 static void 92 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 93 { 94 if (error != 0) { 95 kprintf("getaddr: error %d\n", error); 96 return; 97 } 98 *(bus_addr_t *)arg = segs[0].ds_addr; 99 } 100 101 static int 102 slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 103 { 104 va_list ap; 105 int retval; 106 107 retval = kprintf("%s-slot%d: ", 108 device_get_nameunit(slot->bus), slot->num); 109 110 va_start(ap, fmt); 111 retval += kvprintf(fmt, ap); 112 va_end(ap); 113 return (retval); 114 } 115 116 static void 117 sdhci_dumpregs(struct sdhci_slot *slot) 118 { 119 slot_printf(slot, 120 "============== REGISTER DUMP ==============\n"); 121 122 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 123 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 124 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 125 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 126 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 127 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 128 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 129 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 130 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 131 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 132 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 133 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 134 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 135 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 136 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 137 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 138 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n", 139 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS)); 140 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n", 141 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT)); 142 143 slot_printf(slot, 144 "===========================================\n"); 145 } 146 147 static void 148 sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 149 { 150 int timeout; 151 uint8_t res; 152 153 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 154 if (!(RD4(slot, SDHCI_PRESENT_STATE) & 155 SDHCI_CARD_PRESENT)) 156 return; 157 } 158 159 /* Some controllers need this kick or reset won't work. */ 160 if ((mask & SDHCI_RESET_ALL) == 0 && 161 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 162 uint32_t clock; 163 164 /* This is to force an update */ 165 clock = slot->clock; 166 slot->clock = 0; 167 sdhci_set_clock(slot, clock); 168 } 169 170 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 171 172 if (mask & SDHCI_RESET_ALL) { 173 slot->clock = 0; 174 slot->power = 0; 175 } 176 177 /* Wait max 100 ms */ 178 timeout = 100; 179 /* Controller clears the bits when it's done */ 180 while ((res = RD1(slot, SDHCI_SOFTWARE_RESET)) & mask) { 181 if (timeout == 0) { 182 slot_printf(slot, 183 "Reset 0x%x never completed - 0x%x.\n", 184 (int)mask, (int)res); 185 sdhci_dumpregs(slot); 186 return; 187 } 188 timeout--; 189 DELAY(1000); 190 } 191 } 192 193 static void 194 sdhci_init(struct sdhci_slot *slot) 195 { 196 197 sdhci_reset(slot, SDHCI_RESET_ALL); 198 199 /* Enable interrupts. */ 200 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 201 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 202 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 203 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | 204 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 205 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 206 SDHCI_INT_ACMD12ERR; 207 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 208 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 209 } 210 211 static void 212 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 213 { 214 uint32_t res; 215 uint16_t clk; 216 uint16_t div; 217 int timeout; 218 219 if (clock == slot->clock) 220 return; 221 slot->clock = clock; 222 223 /* Turn off the clock. */ 224 clk = RD2(slot, SDHCI_CLOCK_CONTROL); 225 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); 226 /* If no clock requested - left it so. */ 227 if (clock == 0) 228 return; 229 230 /* Recalculate timeout clock frequency based on the new sd clock. */ 231 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 232 slot->timeout_clk = slot->clock / 1000; 233 234 if (slot->version < SDHCI_SPEC_300) { 235 /* Looking for highest freq <= clock. */ 236 res = slot->max_clk; 237 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { 238 if (res <= clock) 239 break; 240 res >>= 1; 241 } 242 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 243 div >>= 1; 244 } 245 else { 246 /* Version 3.0 divisors are multiples of two up to 1023*2 */ 247 if (clock >= slot->max_clk) 248 div = 0; 249 else { 250 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { 251 if ((slot->max_clk / div) <= clock) 252 break; 253 } 254 } 255 div >>= 1; 256 } 257 258 if (bootverbose || sdhci_debug) 259 slot_printf(slot, "Divider %d for freq %d (max %d)\n", 260 div, clock, slot->max_clk); 261 262 /* Now we have got divider, set it. */ 263 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 264 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 265 << SDHCI_DIVIDER_HI_SHIFT; 266 267 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 268 /* Enable clock. */ 269 clk |= SDHCI_CLOCK_INT_EN; 270 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 271 /* Wait up to 10 ms until it stabilize. */ 272 timeout = 10; 273 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 274 & SDHCI_CLOCK_INT_STABLE)) { 275 if (timeout == 0) { 276 slot_printf(slot, 277 "Internal clock never stabilised.\n"); 278 sdhci_dumpregs(slot); 279 return; 280 } 281 timeout--; 282 DELAY(1000); 283 } 284 /* Pass clock signal to the bus. */ 285 clk |= SDHCI_CLOCK_CARD_EN; 286 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 287 } 288 289 static void 290 sdhci_set_power(struct sdhci_slot *slot, u_char power) 291 { 292 uint8_t pwr; 293 294 if (slot->power == power) 295 return; 296 297 slot->power = power; 298 299 /* Turn off the power. */ 300 pwr = 0; 301 WR1(slot, SDHCI_POWER_CONTROL, pwr); 302 /* If power down requested - left it so. */ 303 if (power == 0) 304 return; 305 /* Set voltage. */ 306 switch (1 << power) { 307 case MMC_OCR_LOW_VOLTAGE: 308 pwr |= SDHCI_POWER_180; 309 break; 310 case MMC_OCR_290_300: 311 case MMC_OCR_300_310: 312 pwr |= SDHCI_POWER_300; 313 break; 314 case MMC_OCR_320_330: 315 case MMC_OCR_330_340: 316 pwr |= SDHCI_POWER_330; 317 break; 318 } 319 WR1(slot, SDHCI_POWER_CONTROL, pwr); 320 /* Turn on the power. */ 321 pwr |= SDHCI_POWER_ON; 322 WR1(slot, SDHCI_POWER_CONTROL, pwr); 323 } 324 325 static void 326 sdhci_read_block_pio(struct sdhci_slot *slot) 327 { 328 uint32_t data; 329 char *buffer; 330 size_t left; 331 332 buffer = slot->curcmd->data->data; 333 buffer += slot->offset; 334 /* Transfer one block at a time. */ 335 left = min(512, slot->curcmd->data->len - slot->offset); 336 slot->offset += left; 337 338 /* If we are too fast, broken controllers return zeroes. */ 339 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 340 DELAY(10); 341 /* Handle unaligned and aligned buffer cases. */ 342 if ((intptr_t)buffer & 3) { 343 while (left > 3) { 344 data = RD4(slot, SDHCI_BUFFER); 345 buffer[0] = data; 346 buffer[1] = (data >> 8); 347 buffer[2] = (data >> 16); 348 buffer[3] = (data >> 24); 349 buffer += 4; 350 left -= 4; 351 } 352 } else { 353 RD_MULTI_4(slot, SDHCI_BUFFER, 354 (uint32_t *)buffer, left >> 2); 355 left &= 3; 356 } 357 /* Handle uneven size case. */ 358 if (left > 0) { 359 data = RD4(slot, SDHCI_BUFFER); 360 while (left > 0) { 361 *(buffer++) = data; 362 data >>= 8; 363 left--; 364 } 365 } 366 } 367 368 static void 369 sdhci_write_block_pio(struct sdhci_slot *slot) 370 { 371 uint32_t data = 0; 372 char *buffer; 373 size_t left; 374 375 buffer = slot->curcmd->data->data; 376 buffer += slot->offset; 377 /* Transfer one block at a time. */ 378 left = min(512, slot->curcmd->data->len - slot->offset); 379 slot->offset += left; 380 381 /* Handle unaligned and aligned buffer cases. */ 382 if ((intptr_t)buffer & 3) { 383 while (left > 3) { 384 data = buffer[0] + 385 (buffer[1] << 8) + 386 (buffer[2] << 16) + 387 (buffer[3] << 24); 388 left -= 4; 389 buffer += 4; 390 WR4(slot, SDHCI_BUFFER, data); 391 } 392 } else { 393 WR_MULTI_4(slot, SDHCI_BUFFER, 394 (uint32_t *)buffer, left >> 2); 395 left &= 3; 396 } 397 /* Handle uneven size case. */ 398 if (left > 0) { 399 while (left > 0) { 400 data <<= 8; 401 data += *(buffer++); 402 left--; 403 } 404 WR4(slot, SDHCI_BUFFER, data); 405 } 406 } 407 408 static void 409 sdhci_transfer_pio(struct sdhci_slot *slot) 410 { 411 412 /* Read as many blocks as possible. */ 413 if (slot->curcmd->data->flags & MMC_DATA_READ) { 414 while (RD4(slot, SDHCI_PRESENT_STATE) & 415 SDHCI_DATA_AVAILABLE) { 416 sdhci_read_block_pio(slot); 417 if (slot->offset >= slot->curcmd->data->len) 418 break; 419 } 420 } else { 421 while (RD4(slot, SDHCI_PRESENT_STATE) & 422 SDHCI_SPACE_AVAILABLE) { 423 sdhci_write_block_pio(slot); 424 if (slot->offset >= slot->curcmd->data->len) 425 break; 426 } 427 } 428 } 429 430 static void 431 sdhci_card_delay(void *arg) 432 { 433 struct sdhci_slot *slot = arg; 434 435 taskqueue_enqueue(taskqueue_swi, &slot->card_task); 436 } 437 438 static void 439 sdhci_card_task(void *arg, int pending) 440 { 441 struct sdhci_slot *slot = arg; 442 443 SDHCI_LOCK(slot); 444 if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) { 445 if (slot->dev == NULL) { 446 /* If card is present - attach mmc bus. */ 447 slot->dev = device_add_child(slot->bus, "mmc", -1); 448 device_set_ivars(slot->dev, slot); 449 SDHCI_UNLOCK(slot); 450 device_probe_and_attach(slot->dev); 451 } else 452 SDHCI_UNLOCK(slot); 453 } else { 454 if (slot->dev != NULL) { 455 /* If no card present - detach mmc bus. */ 456 device_t d = slot->dev; 457 slot->dev = NULL; 458 SDHCI_UNLOCK(slot); 459 device_delete_child(slot->bus, d); 460 } else 461 SDHCI_UNLOCK(slot); 462 } 463 } 464 465 int 466 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 467 { 468 uint32_t caps, freq; 469 int err; 470 471 SDHCI_LOCK_INIT(slot); 472 slot->num = num; 473 slot->bus = dev; 474 475 /* Allocate DMA tag. */ 476 err = bus_dma_tag_create(bus_get_dma_tag(dev), 477 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 478 BUS_SPACE_MAXADDR, NULL, NULL, 479 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 480 BUS_DMA_ALLOCNOW, 481 &slot->dmatag); 482 if (err != 0) { 483 device_printf(dev, "Can't create DMA tag\n"); 484 SDHCI_LOCK_DESTROY(slot); 485 return (err); 486 } 487 /* Allocate DMA memory. */ 488 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 489 BUS_DMA_NOWAIT, &slot->dmamap); 490 if (err != 0) { 491 device_printf(dev, "Can't alloc DMA memory\n"); 492 SDHCI_LOCK_DESTROY(slot); 493 return (err); 494 } 495 /* Map the memory. */ 496 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 497 (void *)slot->dmamem, DMA_BLOCK_SIZE, 498 sdhci_getaddr, &slot->paddr, 0); 499 if (err != 0 || slot->paddr == 0) { 500 device_printf(dev, "Can't load DMA memory\n"); 501 SDHCI_LOCK_DESTROY(slot); 502 if(err) 503 return (err); 504 else 505 return (EFAULT); 506 } 507 508 /* Initialize slot. */ 509 sdhci_init(slot); 510 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 511 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 512 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) 513 caps = slot->caps; 514 else 515 caps = RD4(slot, SDHCI_CAPABILITIES); 516 /* Calculate base clock frequency. */ 517 if (slot->version >= SDHCI_SPEC_300) 518 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 519 SDHCI_CLOCK_BASE_SHIFT; 520 else 521 freq = (caps & SDHCI_CLOCK_BASE_MASK) >> 522 SDHCI_CLOCK_BASE_SHIFT; 523 if (freq != 0) 524 slot->max_clk = freq * 1000000; 525 /* 526 * If the frequency wasn't in the capabilities and the hardware driver 527 * hasn't already set max_clk we're probably not going to work right 528 * with an assumption, so complain about it. 529 */ 530 if (slot->max_clk == 0) { 531 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000; 532 device_printf(dev, "Hardware doesn't specify base clock " 533 "frequency, using %dMHz as default.\n", SDHCI_DEFAULT_MAX_FREQ); 534 } 535 /* Calculate timeout clock frequency. */ 536 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 537 slot->timeout_clk = slot->max_clk / 1000; 538 } else { 539 slot->timeout_clk = 540 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 541 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 542 slot->timeout_clk *= 1000; 543 } 544 /* 545 * If the frequency wasn't in the capabilities and the hardware driver 546 * hasn't already set timeout_clk we'll probably work okay using the 547 * max timeout, but still mention it. 548 */ 549 if (slot->timeout_clk == 0) { 550 device_printf(dev, "Hardware doesn't specify timeout clock " 551 "frequency, setting BROKEN_TIMEOUT quirk.\n"); 552 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 553 } 554 555 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); 556 slot->host.f_max = slot->max_clk; 557 slot->host.host_ocr = 0; 558 if (caps & SDHCI_CAN_VDD_330) 559 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 560 if (caps & SDHCI_CAN_VDD_300) 561 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 562 if (caps & SDHCI_CAN_VDD_180) 563 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 564 if (slot->host.host_ocr == 0) { 565 device_printf(dev, "Hardware doesn't report any " 566 "support voltages.\n"); 567 } 568 slot->host.caps = MMC_CAP_4_BIT_DATA; 569 if (caps & SDHCI_CAN_DO_HISPD) 570 slot->host.caps |= MMC_CAP_HSPEED; 571 /* Decide if we have usable DMA. */ 572 if (caps & SDHCI_CAN_DO_DMA) 573 slot->opt |= SDHCI_HAVE_DMA; 574 575 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 576 slot->opt &= ~SDHCI_HAVE_DMA; 577 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 578 slot->opt |= SDHCI_HAVE_DMA; 579 580 /* 581 * Use platform-provided transfer backend 582 * with PIO as a fallback mechanism 583 */ 584 if (slot->opt & SDHCI_PLATFORM_TRANSFER) 585 slot->opt &= ~SDHCI_HAVE_DMA; 586 587 if (bootverbose || sdhci_debug) { 588 slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n", 589 slot->max_clk / 1000000, 590 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 591 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 592 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 593 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", 594 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); 595 sdhci_dumpregs(slot); 596 } 597 598 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 599 callout_init(&slot->card_callout); 600 callout_init(&slot->timeout_callout); 601 return (0); 602 } 603 604 void 605 sdhci_start_slot(struct sdhci_slot *slot) 606 { 607 sdhci_card_task(slot, 0); 608 } 609 610 int 611 sdhci_cleanup_slot(struct sdhci_slot *slot) 612 { 613 device_t d; 614 615 callout_drain(&slot->timeout_callout); 616 callout_drain(&slot->card_callout); 617 taskqueue_drain(taskqueue_swi, &slot->card_task); 618 619 SDHCI_LOCK(slot); 620 d = slot->dev; 621 slot->dev = NULL; 622 SDHCI_UNLOCK(slot); 623 if (d != NULL) 624 device_delete_child(slot->bus, d); 625 626 SDHCI_LOCK(slot); 627 sdhci_reset(slot, SDHCI_RESET_ALL); 628 SDHCI_UNLOCK(slot); 629 bus_dmamap_unload(slot->dmatag, slot->dmamap); 630 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 631 bus_dma_tag_destroy(slot->dmatag); 632 633 SDHCI_LOCK_DESTROY(slot); 634 635 return (0); 636 } 637 638 int 639 sdhci_generic_suspend(struct sdhci_slot *slot) 640 { 641 sdhci_reset(slot, SDHCI_RESET_ALL); 642 643 return (0); 644 } 645 646 int 647 sdhci_generic_resume(struct sdhci_slot *slot) 648 { 649 sdhci_init(slot); 650 651 return (0); 652 } 653 654 uint32_t 655 sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot) 656 { 657 if (slot->version >= SDHCI_SPEC_300) 658 return (slot->max_clk / SDHCI_300_MAX_DIVIDER); 659 else 660 return (slot->max_clk / SDHCI_200_MAX_DIVIDER); 661 } 662 663 int 664 sdhci_generic_update_ios(device_t brdev, device_t reqdev) 665 { 666 struct sdhci_slot *slot = device_get_ivars(reqdev); 667 struct mmc_ios *ios = &slot->host.ios; 668 669 SDHCI_LOCK(slot); 670 /* Do full reset on bus power down to clear from any state. */ 671 if (ios->power_mode == power_off) { 672 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 673 sdhci_init(slot); 674 } 675 /* Configure the bus. */ 676 sdhci_set_clock(slot, ios->clock); 677 sdhci_set_power(slot, (ios->power_mode == power_off)?0:ios->vdd); 678 if (ios->bus_width == bus_width_4) 679 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 680 else 681 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 682 if (ios->timing == bus_timing_hs) 683 slot->hostctrl |= SDHCI_CTRL_HISPD; 684 else 685 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 686 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 687 /* Some controllers like reset after bus changes. */ 688 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 689 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 690 691 SDHCI_UNLOCK(slot); 692 return (0); 693 } 694 695 static void 696 sdhci_req_done(struct sdhci_slot *slot) 697 { 698 struct mmc_request *req; 699 700 if (slot->req != NULL && slot->curcmd != NULL) { 701 callout_stop(&slot->timeout_callout); 702 req = slot->req; 703 slot->req = NULL; 704 slot->curcmd = NULL; 705 req->done(req); 706 } 707 } 708 709 static void 710 sdhci_timeout(void *arg) 711 { 712 struct sdhci_slot *slot = arg; 713 714 SDHCI_LOCK(slot); 715 if (slot->curcmd != NULL) { 716 sdhci_reset(slot, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 717 slot->curcmd->error = MMC_ERR_TIMEOUT; 718 sdhci_req_done(slot); 719 } 720 SDHCI_UNLOCK(slot); 721 } 722 723 static void 724 sdhci_set_transfer_mode(struct sdhci_slot *slot, 725 struct mmc_data *data) 726 { 727 uint16_t mode; 728 729 if (data == NULL) 730 return; 731 732 mode = SDHCI_TRNS_BLK_CNT_EN; 733 if (data->len > 512) 734 mode |= SDHCI_TRNS_MULTI; 735 if (data->flags & MMC_DATA_READ) 736 mode |= SDHCI_TRNS_READ; 737 if (slot->req->stop) 738 mode |= SDHCI_TRNS_ACMD12; 739 if (slot->flags & SDHCI_USE_DMA) 740 mode |= SDHCI_TRNS_DMA; 741 742 WR2(slot, SDHCI_TRANSFER_MODE, mode); 743 } 744 745 static void 746 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 747 { 748 int flags, timeout; 749 uint32_t mask, state; 750 751 slot->curcmd = cmd; 752 slot->cmd_done = 0; 753 754 cmd->error = MMC_ERR_NONE; 755 756 /* This flags combination is not supported by controller. */ 757 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 758 slot_printf(slot, "Unsupported response type!\n"); 759 cmd->error = MMC_ERR_FAILED; 760 sdhci_req_done(slot); 761 return; 762 } 763 764 /* Read controller present state. */ 765 state = RD4(slot, SDHCI_PRESENT_STATE); 766 /* Do not issue command if there is no card, clock or power. 767 * Controller will not detect timeout without clock active. */ 768 if ((state & SDHCI_CARD_PRESENT) == 0 || 769 slot->power == 0 || 770 slot->clock == 0) { 771 cmd->error = MMC_ERR_FAILED; 772 sdhci_req_done(slot); 773 return; 774 } 775 /* Always wait for free CMD bus. */ 776 mask = SDHCI_CMD_INHIBIT; 777 /* Wait for free DAT if we have data or busy signal. */ 778 if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) 779 mask |= SDHCI_DAT_INHIBIT; 780 /* We shouldn't wait for DAT for stop commands. */ 781 if (cmd == slot->req->stop) 782 mask &= ~SDHCI_DAT_INHIBIT; 783 /* 784 * Wait for bus no more then 250 ms. Typically there will be no wait 785 * here at all, but when writing a crash dump we may be bypassing the 786 * host platform's interrupt handler, and in some cases that handler 787 * may be working around hardware quirks such as not respecting r1b 788 * busy indications. In those cases, this wait-loop serves the purpose 789 * of waiting for the prior command and data transfers to be done, and 790 * SD cards are allowed to take up to 250ms for write and erase ops. 791 * (It's usually more like 20-30ms in the real world.) 792 */ 793 timeout = 250; 794 while (state & mask) { 795 if (timeout == 0) { 796 slot_printf(slot, "Controller never released " 797 "inhibit bit(s).\n"); 798 sdhci_dumpregs(slot); 799 cmd->error = MMC_ERR_FAILED; 800 sdhci_req_done(slot); 801 return; 802 } 803 timeout--; 804 DELAY(1000); 805 state = RD4(slot, SDHCI_PRESENT_STATE); 806 } 807 808 /* Prepare command flags. */ 809 if (!(cmd->flags & MMC_RSP_PRESENT)) 810 flags = SDHCI_CMD_RESP_NONE; 811 else if (cmd->flags & MMC_RSP_136) 812 flags = SDHCI_CMD_RESP_LONG; 813 else if (cmd->flags & MMC_RSP_BUSY) 814 flags = SDHCI_CMD_RESP_SHORT_BUSY; 815 else 816 flags = SDHCI_CMD_RESP_SHORT; 817 if (cmd->flags & MMC_RSP_CRC) 818 flags |= SDHCI_CMD_CRC; 819 if (cmd->flags & MMC_RSP_OPCODE) 820 flags |= SDHCI_CMD_INDEX; 821 if (cmd->data) 822 flags |= SDHCI_CMD_DATA; 823 if (cmd->opcode == MMC_STOP_TRANSMISSION) 824 flags |= SDHCI_CMD_TYPE_ABORT; 825 /* Prepare data. */ 826 sdhci_start_data(slot, cmd->data); 827 /* 828 * Interrupt aggregation: To reduce total number of interrupts 829 * group response interrupt with data interrupt when possible. 830 * If there going to be data interrupt, mask response one. 831 */ 832 if (slot->data_done == 0) { 833 WR4(slot, SDHCI_SIGNAL_ENABLE, 834 slot->intmask &= ~SDHCI_INT_RESPONSE); 835 } 836 /* Set command argument. */ 837 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 838 /* Set data transfer mode. */ 839 sdhci_set_transfer_mode(slot, cmd->data); 840 /* Start command. */ 841 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 842 /* Start timeout callout. */ 843 callout_reset(&slot->timeout_callout, 2*hz, sdhci_timeout, slot); 844 } 845 846 static void 847 sdhci_finish_command(struct sdhci_slot *slot) 848 { 849 int i; 850 851 slot->cmd_done = 1; 852 /* Interrupt aggregation: Restore command interrupt. 853 * Main restore point for the case when command interrupt 854 * happened first. */ 855 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 856 /* In case of error - reset host and return. */ 857 if (slot->curcmd->error) { 858 sdhci_reset(slot, SDHCI_RESET_CMD); 859 sdhci_reset(slot, SDHCI_RESET_DATA); 860 sdhci_start(slot); 861 return; 862 } 863 /* If command has response - fetch it. */ 864 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 865 if (slot->curcmd->flags & MMC_RSP_136) { 866 /* CRC is stripped so we need one byte shift. */ 867 uint8_t extra = 0; 868 for (i = 0; i < 4; i++) { 869 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4); 870 if (slot->quirks & SDHCI_QUIRK_DONT_SHIFT_RESPONSE) { 871 slot->curcmd->resp[3 - i] = val; 872 } else { 873 slot->curcmd->resp[3 - i] = 874 (val << 8) | extra; 875 extra = val >> 24; 876 } 877 } 878 } else { 879 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 880 } 881 } 882 /* If data ready - finish. */ 883 if (slot->data_done) 884 sdhci_start(slot); 885 } 886 887 static void 888 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 889 { 890 uint32_t target_timeout, current_timeout; 891 uint8_t div; 892 893 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 894 slot->data_done = 1; 895 return; 896 } 897 898 slot->data_done = 0; 899 900 /* Calculate and set data timeout.*/ 901 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 902 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { 903 div = 0xe; 904 } else { 905 target_timeout = 1000000; 906 div = 0; 907 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 908 while (current_timeout < target_timeout && div < 0xE) { 909 ++div; 910 current_timeout <<= 1; 911 } 912 /* Compensate for an off-by-one error in the CaFe chip.*/ 913 if (div < 0xE && 914 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) { 915 ++div; 916 } 917 } 918 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 919 920 if (data == NULL) 921 return; 922 923 /* Use DMA if possible. */ 924 if ((slot->opt & SDHCI_HAVE_DMA)) 925 slot->flags |= SDHCI_USE_DMA; 926 /* If data is small, broken DMA may return zeroes instead of data, */ 927 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 928 (data->len <= 512)) 929 slot->flags &= ~SDHCI_USE_DMA; 930 /* Some controllers require even block sizes. */ 931 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 932 ((data->len) & 0x3)) 933 slot->flags &= ~SDHCI_USE_DMA; 934 /* Load DMA buffer. */ 935 if (slot->flags & SDHCI_USE_DMA) { 936 if (data->flags & MMC_DATA_READ) { 937 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREREAD); 938 } else { 939 memcpy(slot->dmamem, data->data, 940 (data->len < DMA_BLOCK_SIZE)?data->len:DMA_BLOCK_SIZE); 941 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREWRITE); 942 } 943 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 944 /* Interrupt aggregation: Mask border interrupt 945 * for the last page and unmask else. */ 946 if (data->len == DMA_BLOCK_SIZE) 947 slot->intmask &= ~SDHCI_INT_DMA_END; 948 else 949 slot->intmask |= SDHCI_INT_DMA_END; 950 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 951 } 952 /* Current data offset for both PIO and DMA. */ 953 slot->offset = 0; 954 /* Set block size and request IRQ on 4K border. */ 955 WR2(slot, SDHCI_BLOCK_SIZE, 956 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512)); 957 /* Set block count. */ 958 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 959 } 960 961 void 962 sdhci_finish_data(struct sdhci_slot *slot) 963 { 964 struct mmc_data *data = slot->curcmd->data; 965 966 slot->data_done = 1; 967 /* Interrupt aggregation: Restore command interrupt. 968 * Auxiliary restore point for the case when data interrupt 969 * happened first. */ 970 if (!slot->cmd_done) { 971 WR4(slot, SDHCI_SIGNAL_ENABLE, 972 slot->intmask |= SDHCI_INT_RESPONSE); 973 } 974 /* Unload rest of data from DMA buffer. */ 975 if (slot->flags & SDHCI_USE_DMA) { 976 if (data->flags & MMC_DATA_READ) { 977 size_t left = data->len - slot->offset; 978 bus_dmamap_sync(slot->dmatag, slot->dmamap, 979 BUS_DMASYNC_POSTREAD); 980 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 981 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 982 } else 983 bus_dmamap_sync(slot->dmatag, slot->dmamap, 984 BUS_DMASYNC_POSTWRITE); 985 } 986 /* If there was error - reset the host. */ 987 if (slot->curcmd->error) { 988 sdhci_reset(slot, SDHCI_RESET_CMD); 989 sdhci_reset(slot, SDHCI_RESET_DATA); 990 sdhci_start(slot); 991 return; 992 } 993 /* If we already have command response - finish. */ 994 if (slot->cmd_done) 995 sdhci_start(slot); 996 } 997 998 static void 999 sdhci_start(struct sdhci_slot *slot) 1000 { 1001 struct mmc_request *req; 1002 1003 req = slot->req; 1004 if (req == NULL) 1005 return; 1006 1007 if (!(slot->flags & CMD_STARTED)) { 1008 slot->flags |= CMD_STARTED; 1009 sdhci_start_command(slot, req->cmd); 1010 return; 1011 } 1012 /* We don't need this until using Auto-CMD12 feature 1013 if (!(slot->flags & STOP_STARTED) && req->stop) { 1014 slot->flags |= STOP_STARTED; 1015 sdhci_start_command(slot, req->stop); 1016 return; 1017 } 1018 */ 1019 if (sdhci_debug > 1) 1020 slot_printf(slot, "result: %d\n", req->cmd->error); 1021 if (!req->cmd->error && 1022 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 1023 sdhci_reset(slot, SDHCI_RESET_CMD); 1024 sdhci_reset(slot, SDHCI_RESET_DATA); 1025 } 1026 1027 sdhci_req_done(slot); 1028 } 1029 1030 int 1031 sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req) 1032 { 1033 struct sdhci_slot *slot = device_get_ivars(reqdev); 1034 1035 SDHCI_LOCK(slot); 1036 if (slot->req != NULL) { 1037 SDHCI_UNLOCK(slot); 1038 return (EBUSY); 1039 } 1040 if (sdhci_debug > 1) { 1041 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1042 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 1043 (req->cmd->data)?(u_int)req->cmd->data->len:0, 1044 (req->cmd->data)?req->cmd->data->flags:0); 1045 } 1046 slot->req = req; 1047 slot->flags = 0; 1048 sdhci_start(slot); 1049 SDHCI_UNLOCK(slot); 1050 if (dumping) { 1051 while (slot->req != NULL) { 1052 sdhci_generic_intr(slot); 1053 DELAY(10); 1054 } 1055 } 1056 return (0); 1057 } 1058 1059 int 1060 sdhci_generic_get_ro(device_t brdev, device_t reqdev) 1061 { 1062 struct sdhci_slot *slot = device_get_ivars(reqdev); 1063 uint32_t val; 1064 1065 SDHCI_LOCK(slot); 1066 val = RD4(slot, SDHCI_PRESENT_STATE); 1067 SDHCI_UNLOCK(slot); 1068 return (!(val & SDHCI_WRITE_PROTECT)); 1069 } 1070 1071 int 1072 sdhci_generic_acquire_host(device_t brdev, device_t reqdev) 1073 { 1074 struct sdhci_slot *slot = device_get_ivars(reqdev); 1075 int err = 0; 1076 1077 SDHCI_LOCK(slot); 1078 while (slot->bus_busy) 1079 lksleep(slot, &slot->lock, 0, "sdhciah", 0); 1080 slot->bus_busy++; 1081 /* Activate led. */ 1082 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1083 SDHCI_UNLOCK(slot); 1084 return (err); 1085 } 1086 1087 int 1088 sdhci_generic_release_host(device_t brdev, device_t reqdev) 1089 { 1090 struct sdhci_slot *slot = device_get_ivars(reqdev); 1091 1092 SDHCI_LOCK(slot); 1093 /* Deactivate led. */ 1094 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 1095 slot->bus_busy--; 1096 SDHCI_UNLOCK(slot); 1097 wakeup(slot); 1098 return (0); 1099 } 1100 1101 static void 1102 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1103 { 1104 1105 if (!slot->curcmd) { 1106 slot_printf(slot, "Got command interrupt 0x%08x, but " 1107 "there is no active command.\n", intmask); 1108 sdhci_dumpregs(slot); 1109 return; 1110 } 1111 if (intmask & SDHCI_INT_TIMEOUT) 1112 slot->curcmd->error = MMC_ERR_TIMEOUT; 1113 else if (intmask & SDHCI_INT_CRC) 1114 slot->curcmd->error = MMC_ERR_BADCRC; 1115 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1116 slot->curcmd->error = MMC_ERR_FIFO; 1117 1118 sdhci_finish_command(slot); 1119 } 1120 1121 static void 1122 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1123 { 1124 1125 if (!slot->curcmd) { 1126 slot_printf(slot, "Got data interrupt 0x%08x, but " 1127 "there is no active command.\n", intmask); 1128 sdhci_dumpregs(slot); 1129 return; 1130 } 1131 if (slot->curcmd->data == NULL && 1132 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1133 slot_printf(slot, "Got data interrupt 0x%08x, but " 1134 "there is no active data operation.\n", 1135 intmask); 1136 sdhci_dumpregs(slot); 1137 return; 1138 } 1139 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1140 slot->curcmd->error = MMC_ERR_TIMEOUT; 1141 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1142 slot->curcmd->error = MMC_ERR_BADCRC; 1143 if (slot->curcmd->data == NULL && 1144 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1145 SDHCI_INT_DMA_END))) { 1146 slot_printf(slot, "Got data interrupt 0x%08x, but " 1147 "there is busy-only command.\n", intmask); 1148 sdhci_dumpregs(slot); 1149 slot->curcmd->error = MMC_ERR_INVALID; 1150 } 1151 if (slot->curcmd->error) { 1152 /* No need to continue after any error. */ 1153 if (slot->flags & PLATFORM_DATA_STARTED) { 1154 slot->flags &= ~PLATFORM_DATA_STARTED; 1155 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1156 } else 1157 sdhci_finish_data(slot); 1158 return; 1159 } 1160 1161 /* Handle PIO interrupt. */ 1162 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { 1163 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) && 1164 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) { 1165 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, &intmask); 1166 slot->flags |= PLATFORM_DATA_STARTED; 1167 } else 1168 sdhci_transfer_pio(slot); 1169 } 1170 /* Handle DMA border. */ 1171 if (intmask & SDHCI_INT_DMA_END) { 1172 struct mmc_data *data = slot->curcmd->data; 1173 size_t left; 1174 1175 /* Unload DMA buffer... */ 1176 left = data->len - slot->offset; 1177 if (data->flags & MMC_DATA_READ) { 1178 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1179 BUS_DMASYNC_POSTREAD); 1180 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1181 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1182 } else { 1183 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1184 BUS_DMASYNC_POSTWRITE); 1185 } 1186 /* ... and reload it again. */ 1187 slot->offset += DMA_BLOCK_SIZE; 1188 left = data->len - slot->offset; 1189 if (data->flags & MMC_DATA_READ) { 1190 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1191 BUS_DMASYNC_PREREAD); 1192 } else { 1193 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 1194 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1195 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1196 BUS_DMASYNC_PREWRITE); 1197 } 1198 /* Interrupt aggregation: Mask border interrupt 1199 * for the last page. */ 1200 if (left == DMA_BLOCK_SIZE) { 1201 slot->intmask &= ~SDHCI_INT_DMA_END; 1202 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1203 } 1204 /* Restart DMA. */ 1205 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1206 } 1207 /* We have got all data. */ 1208 if (intmask & SDHCI_INT_DATA_END) { 1209 if (slot->flags & PLATFORM_DATA_STARTED) { 1210 slot->flags &= ~PLATFORM_DATA_STARTED; 1211 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1212 } else { 1213 sdhci_finish_data(slot); 1214 } 1215 } 1216 } 1217 1218 static void 1219 sdhci_acmd_irq(struct sdhci_slot *slot) 1220 { 1221 uint16_t err; 1222 1223 err = RD4(slot, SDHCI_ACMD12_ERR); 1224 if (!slot->curcmd) { 1225 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1226 "there is no active command.\n", err); 1227 sdhci_dumpregs(slot); 1228 return; 1229 } 1230 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1231 sdhci_reset(slot, SDHCI_RESET_CMD); 1232 } 1233 1234 void 1235 sdhci_generic_intr(struct sdhci_slot *slot) 1236 { 1237 uint32_t intmask; 1238 1239 SDHCI_LOCK(slot); 1240 /* Read slot interrupt status. */ 1241 intmask = RD4(slot, SDHCI_INT_STATUS); 1242 if (intmask == 0 || intmask == 0xffffffff) { 1243 SDHCI_UNLOCK(slot); 1244 return; 1245 } 1246 if (sdhci_debug > 2) 1247 slot_printf(slot, "Interrupt %#x\n", intmask); 1248 1249 /* Handle card presence interrupts. */ 1250 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1251 WR4(slot, SDHCI_INT_STATUS, intmask & 1252 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1253 1254 if (intmask & SDHCI_INT_CARD_REMOVE) { 1255 if (bootverbose || sdhci_debug) 1256 slot_printf(slot, "Card removed\n"); 1257 callout_stop(&slot->card_callout); 1258 taskqueue_enqueue(taskqueue_swi, 1259 &slot->card_task); 1260 } 1261 if (intmask & SDHCI_INT_CARD_INSERT) { 1262 if (bootverbose || sdhci_debug) 1263 slot_printf(slot, "Card inserted\n"); 1264 callout_reset(&slot->card_callout, hz / 2, 1265 sdhci_card_delay, slot); 1266 } 1267 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1268 } 1269 /* Handle command interrupts. */ 1270 if (intmask & SDHCI_INT_CMD_MASK) { 1271 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1272 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1273 } 1274 /* Handle data interrupts. */ 1275 if (intmask & SDHCI_INT_DATA_MASK) { 1276 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1277 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1278 } 1279 /* Handle AutoCMD12 error interrupt. */ 1280 if (intmask & SDHCI_INT_ACMD12ERR) { 1281 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1282 sdhci_acmd_irq(slot); 1283 } 1284 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1285 intmask &= ~SDHCI_INT_ACMD12ERR; 1286 intmask &= ~SDHCI_INT_ERROR; 1287 /* Handle bus power interrupt. */ 1288 if (intmask & SDHCI_INT_BUS_POWER) { 1289 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1290 slot_printf(slot, 1291 "Card is consuming too much power!\n"); 1292 intmask &= ~SDHCI_INT_BUS_POWER; 1293 } 1294 /* The rest is unknown. */ 1295 if (intmask) { 1296 WR4(slot, SDHCI_INT_STATUS, intmask); 1297 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1298 intmask); 1299 sdhci_dumpregs(slot); 1300 } 1301 1302 SDHCI_UNLOCK(slot); 1303 } 1304 1305 int 1306 sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 1307 { 1308 struct sdhci_slot *slot = device_get_ivars(child); 1309 1310 switch (which) { 1311 default: 1312 return (EINVAL); 1313 case MMCBR_IVAR_BUS_MODE: 1314 *(int *)result = slot->host.ios.bus_mode; 1315 break; 1316 case MMCBR_IVAR_BUS_WIDTH: 1317 *(int *)result = slot->host.ios.bus_width; 1318 break; 1319 case MMCBR_IVAR_CHIP_SELECT: 1320 *(int *)result = slot->host.ios.chip_select; 1321 break; 1322 case MMCBR_IVAR_CLOCK: 1323 *(int *)result = slot->host.ios.clock; 1324 break; 1325 case MMCBR_IVAR_F_MIN: 1326 *(int *)result = slot->host.f_min; 1327 break; 1328 case MMCBR_IVAR_F_MAX: 1329 *(int *)result = slot->host.f_max; 1330 break; 1331 case MMCBR_IVAR_HOST_OCR: 1332 *(int *)result = slot->host.host_ocr; 1333 break; 1334 case MMCBR_IVAR_MODE: 1335 *(int *)result = slot->host.mode; 1336 break; 1337 case MMCBR_IVAR_OCR: 1338 *(int *)result = slot->host.ocr; 1339 break; 1340 case MMCBR_IVAR_POWER_MODE: 1341 *(int *)result = slot->host.ios.power_mode; 1342 break; 1343 case MMCBR_IVAR_VDD: 1344 *(int *)result = slot->host.ios.vdd; 1345 break; 1346 case MMCBR_IVAR_CAPS: 1347 *(int *)result = slot->host.caps; 1348 break; 1349 case MMCBR_IVAR_TIMING: 1350 *(int *)result = slot->host.ios.timing; 1351 break; 1352 case MMCBR_IVAR_MAX_DATA: 1353 *(int *)result = 65535; 1354 break; 1355 } 1356 return (0); 1357 } 1358 1359 int 1360 sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1361 { 1362 struct sdhci_slot *slot = device_get_ivars(child); 1363 1364 switch (which) { 1365 default: 1366 return (EINVAL); 1367 case MMCBR_IVAR_BUS_MODE: 1368 slot->host.ios.bus_mode = value; 1369 break; 1370 case MMCBR_IVAR_BUS_WIDTH: 1371 slot->host.ios.bus_width = value; 1372 break; 1373 case MMCBR_IVAR_CHIP_SELECT: 1374 slot->host.ios.chip_select = value; 1375 break; 1376 case MMCBR_IVAR_CLOCK: 1377 if (value > 0) { 1378 uint32_t max_clock; 1379 uint32_t clock; 1380 int i; 1381 1382 max_clock = slot->max_clk; 1383 clock = max_clock; 1384 1385 if (slot->version < SDHCI_SPEC_300) { 1386 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 1387 i <<= 1) { 1388 if (clock <= value) 1389 break; 1390 clock >>= 1; 1391 } 1392 } 1393 else { 1394 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 1395 i += 2) { 1396 if (clock <= value) 1397 break; 1398 clock = max_clock / (i + 2); 1399 } 1400 } 1401 1402 slot->host.ios.clock = clock; 1403 } else 1404 slot->host.ios.clock = 0; 1405 break; 1406 case MMCBR_IVAR_MODE: 1407 slot->host.mode = value; 1408 break; 1409 case MMCBR_IVAR_OCR: 1410 slot->host.ocr = value; 1411 break; 1412 case MMCBR_IVAR_POWER_MODE: 1413 slot->host.ios.power_mode = value; 1414 break; 1415 case MMCBR_IVAR_VDD: 1416 slot->host.ios.vdd = value; 1417 break; 1418 case MMCBR_IVAR_TIMING: 1419 slot->host.ios.timing = value; 1420 break; 1421 case MMCBR_IVAR_CAPS: 1422 case MMCBR_IVAR_HOST_OCR: 1423 case MMCBR_IVAR_F_MIN: 1424 case MMCBR_IVAR_F_MAX: 1425 case MMCBR_IVAR_MAX_DATA: 1426 return (EINVAL); 1427 } 1428 return (0); 1429 } 1430 1431 MODULE_VERSION(sdhci, 1); 1432