1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * $FreeBSD: src/sys/dev/sdhci/sdhci.c,v 1.8 2009/02/17 19:12:15 mav Exp $ 26 */ 27 28 #include <stdarg.h> 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/callout.h> 34 #include <sys/conf.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/module.h> 38 #include <sys/spinlock.h> 39 #include <sys/resource.h> 40 #include <sys/rman.h> 41 #include <sys/sysctl.h> 42 #include <sys/taskqueue.h> 43 44 #include <bus/mmc/bridge.h> 45 #include <bus/mmc/mmcreg.h> 46 #include <bus/mmc/mmcbrvar.h> 47 48 #include "mmcbr_if.h" 49 #include "sdhci.h" 50 #include "sdhci_if.h" 51 52 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 53 54 int sdhci_debug = 0; 55 TUNABLE_INT("hw.sdhci.debug", &sdhci_debug); 56 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level"); 57 58 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 59 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 60 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 61 #define RD_MULTI_4(slot, off, ptr, count) \ 62 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 63 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 64 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 65 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 66 #define WR_MULTI_4(slot, off, ptr, count) \ 67 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 68 69 static int slot_printf(struct sdhci_slot *, const char *, ...) 70 __printflike(2, 3); 71 72 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 73 static void sdhci_start(struct sdhci_slot *slot); 74 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 75 76 static void sdhci_card_task(void *, int); 77 78 /* helper routines */ 79 #define SDHCI_LOCK(_slot) lockmgr(&(_slot)->lock, LK_EXCLUSIVE) 80 #define SDHCI_UNLOCK(_slot) lockmgr(&(_slot)->lock, LK_RELEASE) 81 #define SDHCI_LOCK_INIT(_slot) lockinit(&(_slot)->lock, "sdhci", 0, LK_CANRECURSE) 82 #define SDHCI_LOCK_DESTROY(_slot) lockuninit(&(_slot)->lock); 83 #define SDHCI_ASSERT_LOCKED(_slot) KKASSERT(lockstatus(&(_slot)->lock, curthread) != 0); 84 #define SDHCI_ASSERT_UNLOCKED(_slot) KKASSERT(lockstatus(&(_slot)->lock, curthread) == 0); 85 86 #define SDHCI_DEFAULT_MAX_FREQ 50 87 88 #define SDHCI_200_MAX_DIVIDER 256 89 #define SDHCI_300_MAX_DIVIDER 2046 90 91 /* 92 * Broadcom BCM577xx Controller Constants 93 */ 94 #define BCM577XX_DEFAULT_MAX_DIVIDER 256 /* Maximum divider supported by the default clock source. */ 95 #define BCM577XX_ALT_CLOCK_BASE 63000000 /* Alternative clock's base frequency. */ 96 97 #define BCM577XX_HOST_CONTROL 0x198 98 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF 99 #define BCM577XX_CTRL_CLKSEL_SHIFT 12 100 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0 101 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3 102 103 104 static void 105 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 106 { 107 if (error != 0) { 108 kprintf("getaddr: error %d\n", error); 109 return; 110 } 111 *(bus_addr_t *)arg = segs[0].ds_addr; 112 } 113 114 static int 115 slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 116 { 117 va_list ap; 118 int retval; 119 120 retval = kprintf("%s-slot%d: ", 121 device_get_nameunit(slot->bus), slot->num); 122 123 va_start(ap, fmt); 124 retval += kvprintf(fmt, ap); 125 va_end(ap); 126 return (retval); 127 } 128 129 static void 130 sdhci_dumpregs(struct sdhci_slot *slot) 131 { 132 slot_printf(slot, 133 "============== REGISTER DUMP ==============\n"); 134 135 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 136 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 137 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 138 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 139 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 140 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 141 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 142 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 143 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 144 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 145 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 146 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 147 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 148 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 149 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 150 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 151 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n", 152 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS)); 153 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n", 154 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT)); 155 156 slot_printf(slot, 157 "===========================================\n"); 158 } 159 160 static void 161 sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 162 { 163 int timeout; 164 165 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 166 if (!(RD4(slot, SDHCI_PRESENT_STATE) & 167 SDHCI_CARD_PRESENT)) 168 return; 169 } 170 171 /* Some controllers need this kick or reset won't work. */ 172 if ((mask & SDHCI_RESET_ALL) == 0 && 173 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 174 uint32_t clock; 175 176 /* This is to force an update */ 177 clock = slot->clock; 178 slot->clock = 0; 179 sdhci_set_clock(slot, clock); 180 } 181 182 if (mask & SDHCI_RESET_ALL) { 183 slot->clock = 0; 184 slot->power = 0; 185 } 186 187 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 188 189 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) { 190 /* 191 * Resets on TI OMAPs and AM335x are incompatible with SDHCI 192 * specification. The reset bit has internal propagation delay, 193 * so a fast read after write returns 0 even if reset process is 194 * in progress. The workaround is to poll for 1 before polling 195 * for 0. In the worst case, if we miss seeing it asserted the 196 * time we spent waiting is enough to ensure the reset finishes. 197 */ 198 timeout = 10000; 199 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) { 200 if (timeout <= 0) 201 break; 202 timeout--; 203 DELAY(1); 204 } 205 } 206 207 /* Wait max 100 ms */ 208 timeout = 10000; 209 /* Controller clears the bits when it's done */ 210 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) { 211 if (timeout <= 0) { 212 slot_printf(slot, "Reset 0x%x never completed.\n", 213 mask); 214 sdhci_dumpregs(slot); 215 return; 216 } 217 timeout--; 218 DELAY(10); 219 } 220 } 221 222 static void 223 sdhci_init(struct sdhci_slot *slot) 224 { 225 226 sdhci_reset(slot, SDHCI_RESET_ALL); 227 228 /* Enable interrupts. */ 229 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 230 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 231 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 232 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | 233 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 234 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 235 SDHCI_INT_ACMD12ERR; 236 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 237 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 238 } 239 240 static void 241 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 242 { 243 uint32_t clk_base; 244 uint32_t clk_sel; 245 uint32_t res; 246 uint16_t clk; 247 uint16_t div; 248 int timeout; 249 250 if (clock == slot->clock) 251 return; 252 slot->clock = clock; 253 254 /* Turn off the clock. */ 255 clk = RD2(slot, SDHCI_CLOCK_CONTROL); 256 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); 257 /* If no clock requested - left it so. */ 258 if (clock == 0) 259 return; 260 261 /* Determine the clock base frequency */ 262 clk_base = slot->max_clk; 263 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) { 264 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & BCM577XX_CTRL_CLKSEL_MASK; 265 266 /* Select clock source appropriate for the requested frequency. */ 267 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) { 268 clk_base = BCM577XX_ALT_CLOCK_BASE; 269 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ << BCM577XX_CTRL_CLKSEL_SHIFT); 270 } else { 271 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT << BCM577XX_CTRL_CLKSEL_SHIFT); 272 } 273 274 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel); 275 } 276 277 /* Recalculate timeout clock frequency based on the new sd clock. */ 278 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 279 slot->timeout_clk = slot->clock / 1000; 280 281 if (slot->version < SDHCI_SPEC_300) { 282 /* Looking for highest freq <= clock. */ 283 res = clk_base; 284 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { 285 if (res <= clock) 286 break; 287 res >>= 1; 288 } 289 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 290 div >>= 1; 291 } 292 else { 293 /* Version 3.0 divisors are multiples of two up to 1023*2 */ 294 if (clock >= clk_base) 295 div = 0; 296 else { 297 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { 298 if ((clk_base / div) <= clock) 299 break; 300 } 301 } 302 div >>= 1; 303 } 304 305 if (bootverbose || sdhci_debug) 306 slot_printf(slot, "Divider %d for freq %d (base %d)\n", 307 div, clock, clk_base); 308 309 /* Now we have got divider, set it. */ 310 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 311 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 312 << SDHCI_DIVIDER_HI_SHIFT; 313 314 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 315 /* Enable clock. */ 316 clk |= SDHCI_CLOCK_INT_EN; 317 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 318 /* Wait up to 10 ms until it stabilize. */ 319 timeout = 10; 320 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 321 & SDHCI_CLOCK_INT_STABLE)) { 322 if (timeout == 0) { 323 slot_printf(slot, 324 "Internal clock never stabilised.\n"); 325 sdhci_dumpregs(slot); 326 return; 327 } 328 timeout--; 329 DELAY(1000); 330 } 331 /* Pass clock signal to the bus. */ 332 clk |= SDHCI_CLOCK_CARD_EN; 333 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 334 } 335 336 static void 337 sdhci_set_power(struct sdhci_slot *slot, u_char power) 338 { 339 uint8_t pwr; 340 341 if (slot->power == power) 342 return; 343 344 slot->power = power; 345 346 /* Turn off the power. */ 347 pwr = 0; 348 WR1(slot, SDHCI_POWER_CONTROL, pwr); 349 /* If power down requested - left it so. */ 350 if (power == 0) 351 return; 352 /* Set voltage. */ 353 switch (1 << power) { 354 case MMC_OCR_LOW_VOLTAGE: 355 pwr |= SDHCI_POWER_180; 356 break; 357 case MMC_OCR_290_300: 358 case MMC_OCR_300_310: 359 pwr |= SDHCI_POWER_300; 360 break; 361 case MMC_OCR_320_330: 362 case MMC_OCR_330_340: 363 pwr |= SDHCI_POWER_330; 364 break; 365 } 366 WR1(slot, SDHCI_POWER_CONTROL, pwr); 367 /* Turn on the power. */ 368 pwr |= SDHCI_POWER_ON; 369 WR1(slot, SDHCI_POWER_CONTROL, pwr); 370 } 371 372 static void 373 sdhci_read_block_pio(struct sdhci_slot *slot) 374 { 375 uint32_t data; 376 char *buffer; 377 size_t left; 378 379 buffer = slot->curcmd->data->data; 380 buffer += slot->offset; 381 /* Transfer one block at a time. */ 382 left = min(512, slot->curcmd->data->len - slot->offset); 383 slot->offset += left; 384 385 /* If we are too fast, broken controllers return zeroes. */ 386 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 387 DELAY(10); 388 /* Handle unaligned and aligned buffer cases. */ 389 if ((intptr_t)buffer & 3) { 390 while (left > 3) { 391 data = RD4(slot, SDHCI_BUFFER); 392 buffer[0] = data; 393 buffer[1] = (data >> 8); 394 buffer[2] = (data >> 16); 395 buffer[3] = (data >> 24); 396 buffer += 4; 397 left -= 4; 398 } 399 } else { 400 RD_MULTI_4(slot, SDHCI_BUFFER, 401 (uint32_t *)buffer, left >> 2); 402 left &= 3; 403 } 404 /* Handle uneven size case. */ 405 if (left > 0) { 406 data = RD4(slot, SDHCI_BUFFER); 407 while (left > 0) { 408 *(buffer++) = data; 409 data >>= 8; 410 left--; 411 } 412 } 413 } 414 415 static void 416 sdhci_write_block_pio(struct sdhci_slot *slot) 417 { 418 uint32_t data = 0; 419 char *buffer; 420 size_t left; 421 422 buffer = slot->curcmd->data->data; 423 buffer += slot->offset; 424 /* Transfer one block at a time. */ 425 left = min(512, slot->curcmd->data->len - slot->offset); 426 slot->offset += left; 427 428 /* Handle unaligned and aligned buffer cases. */ 429 if ((intptr_t)buffer & 3) { 430 while (left > 3) { 431 data = buffer[0] + 432 (buffer[1] << 8) + 433 (buffer[2] << 16) + 434 (buffer[3] << 24); 435 left -= 4; 436 buffer += 4; 437 WR4(slot, SDHCI_BUFFER, data); 438 } 439 } else { 440 WR_MULTI_4(slot, SDHCI_BUFFER, 441 (uint32_t *)buffer, left >> 2); 442 left &= 3; 443 } 444 /* Handle uneven size case. */ 445 if (left > 0) { 446 while (left > 0) { 447 data <<= 8; 448 data += *(buffer++); 449 left--; 450 } 451 WR4(slot, SDHCI_BUFFER, data); 452 } 453 } 454 455 static void 456 sdhci_transfer_pio(struct sdhci_slot *slot) 457 { 458 459 /* Read as many blocks as possible. */ 460 if (slot->curcmd->data->flags & MMC_DATA_READ) { 461 while (RD4(slot, SDHCI_PRESENT_STATE) & 462 SDHCI_DATA_AVAILABLE) { 463 sdhci_read_block_pio(slot); 464 if (slot->offset >= slot->curcmd->data->len) 465 break; 466 } 467 } else { 468 while (RD4(slot, SDHCI_PRESENT_STATE) & 469 SDHCI_SPACE_AVAILABLE) { 470 sdhci_write_block_pio(slot); 471 if (slot->offset >= slot->curcmd->data->len) 472 break; 473 } 474 } 475 } 476 477 static void 478 sdhci_card_delay(void *arg) 479 { 480 struct sdhci_slot *slot = arg; 481 482 taskqueue_enqueue(taskqueue_swi, &slot->card_task); 483 } 484 485 static void 486 sdhci_card_task(void *arg, int pending) 487 { 488 struct sdhci_slot *slot = arg; 489 490 SDHCI_LOCK(slot); 491 if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) { 492 if (slot->dev == NULL) { 493 /* If card is present - attach mmc bus. */ 494 slot->dev = device_add_child(slot->bus, "mmc", -1); 495 device_set_ivars(slot->dev, slot); 496 SDHCI_UNLOCK(slot); 497 device_probe_and_attach(slot->dev); 498 } else 499 SDHCI_UNLOCK(slot); 500 } else { 501 if (slot->dev != NULL) { 502 /* If no card present - detach mmc bus. */ 503 device_t d = slot->dev; 504 slot->dev = NULL; 505 SDHCI_UNLOCK(slot); 506 device_delete_child(slot->bus, d); 507 } else 508 SDHCI_UNLOCK(slot); 509 } 510 } 511 512 int 513 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 514 { 515 uint32_t caps, freq; 516 int err; 517 518 SDHCI_LOCK_INIT(slot); 519 slot->num = num; 520 slot->bus = dev; 521 522 /* Allocate DMA tag. */ 523 err = bus_dma_tag_create(bus_get_dma_tag(dev), 524 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 525 BUS_SPACE_MAXADDR, NULL, NULL, 526 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 527 BUS_DMA_ALLOCNOW, 528 &slot->dmatag); 529 if (err != 0) { 530 device_printf(dev, "Can't create DMA tag\n"); 531 SDHCI_LOCK_DESTROY(slot); 532 return (err); 533 } 534 /* Allocate DMA memory. */ 535 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 536 BUS_DMA_NOWAIT, &slot->dmamap); 537 if (err != 0) { 538 device_printf(dev, "Can't alloc DMA memory\n"); 539 SDHCI_LOCK_DESTROY(slot); 540 return (err); 541 } 542 /* Map the memory. */ 543 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 544 (void *)slot->dmamem, DMA_BLOCK_SIZE, 545 sdhci_getaddr, &slot->paddr, 0); 546 if (err != 0 || slot->paddr == 0) { 547 device_printf(dev, "Can't load DMA memory\n"); 548 SDHCI_LOCK_DESTROY(slot); 549 if(err) 550 return (err); 551 else 552 return (EFAULT); 553 } 554 555 /* Initialize slot. */ 556 sdhci_init(slot); 557 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 558 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 559 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) 560 caps = slot->caps; 561 else 562 caps = RD4(slot, SDHCI_CAPABILITIES); 563 /* Calculate base clock frequency. */ 564 if (slot->version >= SDHCI_SPEC_300) 565 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 566 SDHCI_CLOCK_BASE_SHIFT; 567 else 568 freq = (caps & SDHCI_CLOCK_BASE_MASK) >> 569 SDHCI_CLOCK_BASE_SHIFT; 570 if (freq != 0) 571 slot->max_clk = freq * 1000000; 572 /* 573 * If the frequency wasn't in the capabilities and the hardware driver 574 * hasn't already set max_clk we're probably not going to work right 575 * with an assumption, so complain about it. 576 */ 577 if (slot->max_clk == 0) { 578 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000; 579 device_printf(dev, "Hardware doesn't specify base clock " 580 "frequency, using %dMHz as default.\n", SDHCI_DEFAULT_MAX_FREQ); 581 } 582 /* Calculate timeout clock frequency. */ 583 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 584 slot->timeout_clk = slot->max_clk / 1000; 585 } else { 586 slot->timeout_clk = 587 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 588 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 589 slot->timeout_clk *= 1000; 590 } 591 /* 592 * If the frequency wasn't in the capabilities and the hardware driver 593 * hasn't already set timeout_clk we'll probably work okay using the 594 * max timeout, but still mention it. 595 */ 596 if (slot->timeout_clk == 0) { 597 device_printf(dev, "Hardware doesn't specify timeout clock " 598 "frequency, setting BROKEN_TIMEOUT quirk.\n"); 599 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 600 } 601 602 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); 603 slot->host.f_max = slot->max_clk; 604 slot->host.host_ocr = 0; 605 if (caps & SDHCI_CAN_VDD_330) 606 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 607 if (caps & SDHCI_CAN_VDD_300) 608 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 609 if (caps & SDHCI_CAN_VDD_180) 610 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 611 if (slot->host.host_ocr == 0) { 612 device_printf(dev, "Hardware doesn't report any " 613 "support voltages.\n"); 614 } 615 slot->host.caps = MMC_CAP_4_BIT_DATA; 616 if (caps & SDHCI_CAN_DO_8BITBUS) 617 slot->host.caps |= MMC_CAP_8_BIT_DATA; 618 if (caps & SDHCI_CAN_DO_HISPD) 619 slot->host.caps |= MMC_CAP_HSPEED; 620 /* Decide if we have usable DMA. */ 621 if (caps & SDHCI_CAN_DO_DMA) 622 slot->opt |= SDHCI_HAVE_DMA; 623 624 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 625 slot->opt &= ~SDHCI_HAVE_DMA; 626 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 627 slot->opt |= SDHCI_HAVE_DMA; 628 629 /* 630 * Use platform-provided transfer backend 631 * with PIO as a fallback mechanism 632 */ 633 if (slot->opt & SDHCI_PLATFORM_TRANSFER) 634 slot->opt &= ~SDHCI_HAVE_DMA; 635 636 if (bootverbose || sdhci_debug) { 637 slot_printf(slot, "%uMHz%s %s%s%s%s %s\n", 638 slot->max_clk / 1000000, 639 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 640 (caps & MMC_CAP_8_BIT_DATA) ? "8bits" : 641 ((caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"), 642 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 643 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 644 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", 645 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); 646 sdhci_dumpregs(slot); 647 } 648 649 slot->timeout = 10; 650 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus), 651 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO, 652 "timeout", CTLFLAG_RW, &slot->timeout, 0, 653 "Maximum timeout for SDHCI transfers (in secs)"); 654 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 655 callout_init(&slot->card_callout); 656 callout_init_lk(&slot->timeout_callout, &slot->lock); 657 return (0); 658 } 659 660 void 661 sdhci_start_slot(struct sdhci_slot *slot) 662 { 663 sdhci_card_task(slot, 0); 664 } 665 666 int 667 sdhci_cleanup_slot(struct sdhci_slot *slot) 668 { 669 device_t d; 670 671 callout_drain(&slot->timeout_callout); 672 callout_drain(&slot->card_callout); 673 taskqueue_drain(taskqueue_swi, &slot->card_task); 674 675 SDHCI_LOCK(slot); 676 d = slot->dev; 677 slot->dev = NULL; 678 SDHCI_UNLOCK(slot); 679 if (d != NULL) 680 device_delete_child(slot->bus, d); 681 682 SDHCI_LOCK(slot); 683 sdhci_reset(slot, SDHCI_RESET_ALL); 684 SDHCI_UNLOCK(slot); 685 bus_dmamap_unload(slot->dmatag, slot->dmamap); 686 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 687 bus_dma_tag_destroy(slot->dmatag); 688 689 SDHCI_LOCK_DESTROY(slot); 690 691 return (0); 692 } 693 694 int 695 sdhci_generic_suspend(struct sdhci_slot *slot) 696 { 697 sdhci_reset(slot, SDHCI_RESET_ALL); 698 699 return (0); 700 } 701 702 int 703 sdhci_generic_resume(struct sdhci_slot *slot) 704 { 705 sdhci_init(slot); 706 707 return (0); 708 } 709 710 uint32_t 711 sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot) 712 { 713 if (slot->version >= SDHCI_SPEC_300) 714 return (slot->max_clk / SDHCI_300_MAX_DIVIDER); 715 else 716 return (slot->max_clk / SDHCI_200_MAX_DIVIDER); 717 } 718 719 int 720 sdhci_generic_update_ios(device_t brdev, device_t reqdev) 721 { 722 struct sdhci_slot *slot = device_get_ivars(reqdev); 723 struct mmc_ios *ios = &slot->host.ios; 724 725 SDHCI_LOCK(slot); 726 /* Do full reset on bus power down to clear from any state. */ 727 if (ios->power_mode == power_off) { 728 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 729 sdhci_init(slot); 730 } 731 /* Configure the bus. */ 732 sdhci_set_clock(slot, ios->clock); 733 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 734 if (ios->bus_width == bus_width_8) { 735 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 736 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 737 } else if (ios->bus_width == bus_width_4) { 738 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 739 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 740 } else if (ios->bus_width == bus_width_1) { 741 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 742 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 743 } else { 744 panic("Invalid bus width: %d", ios->bus_width); 745 } 746 if (ios->timing == bus_timing_hs && 747 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 748 slot->hostctrl |= SDHCI_CTRL_HISPD; 749 else 750 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 751 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 752 /* Some controllers like reset after bus changes. */ 753 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 754 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 755 756 SDHCI_UNLOCK(slot); 757 return (0); 758 } 759 760 static void 761 sdhci_req_done(struct sdhci_slot *slot) 762 { 763 struct mmc_request *req; 764 765 if (slot->req != NULL && slot->curcmd != NULL) { 766 callout_stop(&slot->timeout_callout); 767 req = slot->req; 768 slot->req = NULL; 769 slot->curcmd = NULL; 770 req->done(req); 771 } 772 } 773 774 static void 775 sdhci_timeout(void *arg) 776 { 777 struct sdhci_slot *slot = arg; 778 779 if (slot->curcmd != NULL) { 780 slot_printf(slot, " Controller timeout\n"); 781 sdhci_dumpregs(slot); 782 sdhci_reset(slot, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 783 slot->curcmd->error = MMC_ERR_TIMEOUT; 784 sdhci_req_done(slot); 785 } else { 786 slot_printf(slot, " Spurious timeout - no active command\n"); 787 } 788 } 789 790 static void 791 sdhci_set_transfer_mode(struct sdhci_slot *slot, 792 struct mmc_data *data) 793 { 794 uint16_t mode; 795 796 if (data == NULL) 797 return; 798 799 mode = SDHCI_TRNS_BLK_CNT_EN; 800 if (data->len > 512) 801 mode |= SDHCI_TRNS_MULTI; 802 if (data->flags & MMC_DATA_READ) 803 mode |= SDHCI_TRNS_READ; 804 if (slot->req->stop) 805 mode |= SDHCI_TRNS_ACMD12; 806 if (slot->flags & SDHCI_USE_DMA) 807 mode |= SDHCI_TRNS_DMA; 808 809 WR2(slot, SDHCI_TRANSFER_MODE, mode); 810 } 811 812 static void 813 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 814 { 815 int flags, timeout; 816 uint32_t mask, state; 817 818 slot->curcmd = cmd; 819 slot->cmd_done = 0; 820 821 cmd->error = MMC_ERR_NONE; 822 823 /* This flags combination is not supported by controller. */ 824 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 825 slot_printf(slot, "Unsupported response type!\n"); 826 cmd->error = MMC_ERR_FAILED; 827 sdhci_req_done(slot); 828 return; 829 } 830 831 /* Read controller present state. */ 832 state = RD4(slot, SDHCI_PRESENT_STATE); 833 /* Do not issue command if there is no card, clock or power. 834 * Controller will not detect timeout without clock active. */ 835 if ((state & SDHCI_CARD_PRESENT) == 0 || 836 slot->power == 0 || 837 slot->clock == 0) { 838 cmd->error = MMC_ERR_FAILED; 839 sdhci_req_done(slot); 840 return; 841 } 842 /* Always wait for free CMD bus. */ 843 mask = SDHCI_CMD_INHIBIT; 844 /* Wait for free DAT if we have data or busy signal. */ 845 if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) 846 mask |= SDHCI_DAT_INHIBIT; 847 /* We shouldn't wait for DAT for stop commands. */ 848 if (cmd == slot->req->stop) 849 mask &= ~SDHCI_DAT_INHIBIT; 850 /* 851 * Wait for bus no more then 250 ms. Typically there will be no wait 852 * here at all, but when writing a crash dump we may be bypassing the 853 * host platform's interrupt handler, and in some cases that handler 854 * may be working around hardware quirks such as not respecting r1b 855 * busy indications. In those cases, this wait-loop serves the purpose 856 * of waiting for the prior command and data transfers to be done, and 857 * SD cards are allowed to take up to 250ms for write and erase ops. 858 * (It's usually more like 20-30ms in the real world.) 859 */ 860 timeout = 250; 861 while (state & mask) { 862 if (timeout == 0) { 863 slot_printf(slot, "Controller never released " 864 "inhibit bit(s).\n"); 865 sdhci_dumpregs(slot); 866 cmd->error = MMC_ERR_FAILED; 867 sdhci_req_done(slot); 868 return; 869 } 870 timeout--; 871 DELAY(1000); 872 state = RD4(slot, SDHCI_PRESENT_STATE); 873 } 874 875 /* Prepare command flags. */ 876 if (!(cmd->flags & MMC_RSP_PRESENT)) 877 flags = SDHCI_CMD_RESP_NONE; 878 else if (cmd->flags & MMC_RSP_136) 879 flags = SDHCI_CMD_RESP_LONG; 880 else if (cmd->flags & MMC_RSP_BUSY) 881 flags = SDHCI_CMD_RESP_SHORT_BUSY; 882 else 883 flags = SDHCI_CMD_RESP_SHORT; 884 if (cmd->flags & MMC_RSP_CRC) 885 flags |= SDHCI_CMD_CRC; 886 if (cmd->flags & MMC_RSP_OPCODE) 887 flags |= SDHCI_CMD_INDEX; 888 if (cmd->data) 889 flags |= SDHCI_CMD_DATA; 890 if (cmd->opcode == MMC_STOP_TRANSMISSION) 891 flags |= SDHCI_CMD_TYPE_ABORT; 892 /* Prepare data. */ 893 sdhci_start_data(slot, cmd->data); 894 /* 895 * Interrupt aggregation: To reduce total number of interrupts 896 * group response interrupt with data interrupt when possible. 897 * If there going to be data interrupt, mask response one. 898 */ 899 if (slot->data_done == 0) { 900 WR4(slot, SDHCI_SIGNAL_ENABLE, 901 slot->intmask &= ~SDHCI_INT_RESPONSE); 902 } 903 /* Set command argument. */ 904 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 905 /* Set data transfer mode. */ 906 sdhci_set_transfer_mode(slot, cmd->data); 907 /* Start command. */ 908 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 909 /* Start timeout callout. */ 910 callout_reset(&slot->timeout_callout, slot->timeout * hz, 911 sdhci_timeout, slot); 912 } 913 914 static void 915 sdhci_finish_command(struct sdhci_slot *slot) 916 { 917 int i; 918 919 slot->cmd_done = 1; 920 /* Interrupt aggregation: Restore command interrupt. 921 * Main restore point for the case when command interrupt 922 * happened first. */ 923 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 924 /* In case of error - reset host and return. */ 925 if (slot->curcmd->error) { 926 sdhci_reset(slot, SDHCI_RESET_CMD); 927 sdhci_reset(slot, SDHCI_RESET_DATA); 928 sdhci_start(slot); 929 return; 930 } 931 /* If command has response - fetch it. */ 932 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 933 if (slot->curcmd->flags & MMC_RSP_136) { 934 /* CRC is stripped so we need one byte shift. */ 935 uint8_t extra = 0; 936 for (i = 0; i < 4; i++) { 937 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4); 938 if (slot->quirks & SDHCI_QUIRK_DONT_SHIFT_RESPONSE) { 939 slot->curcmd->resp[3 - i] = val; 940 } else { 941 slot->curcmd->resp[3 - i] = 942 (val << 8) | extra; 943 extra = val >> 24; 944 } 945 } 946 } else { 947 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 948 } 949 } 950 /* If data ready - finish. */ 951 if (slot->data_done) 952 sdhci_start(slot); 953 } 954 955 static void 956 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 957 { 958 uint32_t target_timeout, current_timeout; 959 uint8_t div; 960 961 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 962 slot->data_done = 1; 963 return; 964 } 965 966 slot->data_done = 0; 967 968 /* Calculate and set data timeout.*/ 969 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 970 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { 971 div = 0xe; 972 } else { 973 target_timeout = 1000000; 974 div = 0; 975 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 976 while (current_timeout < target_timeout && div < 0xE) { 977 ++div; 978 current_timeout <<= 1; 979 } 980 /* Compensate for an off-by-one error in the CaFe chip.*/ 981 if (div < 0xE && 982 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) { 983 ++div; 984 } 985 } 986 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 987 988 if (data == NULL) 989 return; 990 991 /* Use DMA if possible. */ 992 if ((slot->opt & SDHCI_HAVE_DMA)) 993 slot->flags |= SDHCI_USE_DMA; 994 /* If data is small, broken DMA may return zeroes instead of data, */ 995 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 996 (data->len <= 512)) 997 slot->flags &= ~SDHCI_USE_DMA; 998 /* Some controllers require even block sizes. */ 999 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 1000 ((data->len) & 0x3)) 1001 slot->flags &= ~SDHCI_USE_DMA; 1002 /* Load DMA buffer. */ 1003 if (slot->flags & SDHCI_USE_DMA) { 1004 if (data->flags & MMC_DATA_READ) { 1005 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1006 BUS_DMASYNC_PREREAD); 1007 } else { 1008 memcpy(slot->dmamem, data->data, 1009 (data->len < DMA_BLOCK_SIZE) ? 1010 data->len : DMA_BLOCK_SIZE); 1011 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1012 BUS_DMASYNC_PREWRITE); 1013 } 1014 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1015 /* Interrupt aggregation: Mask border interrupt 1016 * for the last page and unmask else. */ 1017 if (data->len == DMA_BLOCK_SIZE) 1018 slot->intmask &= ~SDHCI_INT_DMA_END; 1019 else 1020 slot->intmask |= SDHCI_INT_DMA_END; 1021 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1022 } 1023 /* Current data offset for both PIO and DMA. */ 1024 slot->offset = 0; 1025 /* Set block size and request IRQ on 4K border. */ 1026 WR2(slot, SDHCI_BLOCK_SIZE, 1027 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512)); 1028 /* Set block count. */ 1029 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 1030 } 1031 1032 void 1033 sdhci_finish_data(struct sdhci_slot *slot) 1034 { 1035 struct mmc_data *data = slot->curcmd->data; 1036 1037 /* Interrupt aggregation: Restore command interrupt. 1038 * Auxiliary restore point for the case when data interrupt 1039 * happened first. */ 1040 if (!slot->cmd_done) { 1041 WR4(slot, SDHCI_SIGNAL_ENABLE, 1042 slot->intmask |= SDHCI_INT_RESPONSE); 1043 } 1044 /* Unload rest of data from DMA buffer. */ 1045 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA)) { 1046 if (data->flags & MMC_DATA_READ) { 1047 size_t left = data->len - slot->offset; 1048 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1049 BUS_DMASYNC_POSTREAD); 1050 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1051 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1052 } else 1053 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1054 BUS_DMASYNC_POSTWRITE); 1055 } 1056 slot->data_done = 1; 1057 /* If there was error - reset the host. */ 1058 if (slot->curcmd->error) { 1059 sdhci_reset(slot, SDHCI_RESET_CMD); 1060 sdhci_reset(slot, SDHCI_RESET_DATA); 1061 sdhci_start(slot); 1062 return; 1063 } 1064 /* If we already have command response - finish. */ 1065 if (slot->cmd_done) 1066 sdhci_start(slot); 1067 } 1068 1069 static void 1070 sdhci_start(struct sdhci_slot *slot) 1071 { 1072 struct mmc_request *req; 1073 1074 req = slot->req; 1075 if (req == NULL) 1076 return; 1077 1078 if (!(slot->flags & CMD_STARTED)) { 1079 slot->flags |= CMD_STARTED; 1080 sdhci_start_command(slot, req->cmd); 1081 return; 1082 } 1083 /* We don't need this until using Auto-CMD12 feature 1084 if (!(slot->flags & STOP_STARTED) && req->stop) { 1085 slot->flags |= STOP_STARTED; 1086 sdhci_start_command(slot, req->stop); 1087 return; 1088 } 1089 */ 1090 if (sdhci_debug > 1) 1091 slot_printf(slot, "result: %d\n", req->cmd->error); 1092 if (!req->cmd->error && 1093 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 1094 sdhci_reset(slot, SDHCI_RESET_CMD); 1095 sdhci_reset(slot, SDHCI_RESET_DATA); 1096 } 1097 1098 sdhci_req_done(slot); 1099 } 1100 1101 int 1102 sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req) 1103 { 1104 struct sdhci_slot *slot = device_get_ivars(reqdev); 1105 1106 SDHCI_LOCK(slot); 1107 if (slot->req != NULL) { 1108 SDHCI_UNLOCK(slot); 1109 return (EBUSY); 1110 } 1111 if (sdhci_debug > 1) { 1112 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1113 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 1114 (req->cmd->data)?(u_int)req->cmd->data->len:0, 1115 (req->cmd->data)?req->cmd->data->flags:0); 1116 } 1117 slot->req = req; 1118 slot->flags = 0; 1119 sdhci_start(slot); 1120 SDHCI_UNLOCK(slot); 1121 if (dumping) { 1122 while (slot->req != NULL) { 1123 sdhci_generic_intr(slot); 1124 DELAY(10); 1125 } 1126 } 1127 return (0); 1128 } 1129 1130 int 1131 sdhci_generic_get_ro(device_t brdev, device_t reqdev) 1132 { 1133 struct sdhci_slot *slot = device_get_ivars(reqdev); 1134 uint32_t val; 1135 1136 SDHCI_LOCK(slot); 1137 val = RD4(slot, SDHCI_PRESENT_STATE); 1138 SDHCI_UNLOCK(slot); 1139 return (!(val & SDHCI_WRITE_PROTECT)); 1140 } 1141 1142 int 1143 sdhci_generic_acquire_host(device_t brdev, device_t reqdev) 1144 { 1145 struct sdhci_slot *slot = device_get_ivars(reqdev); 1146 int err = 0; 1147 1148 SDHCI_LOCK(slot); 1149 while (slot->bus_busy) 1150 lksleep(slot, &slot->lock, 0, "sdhciah", 0); 1151 slot->bus_busy++; 1152 /* Activate led. */ 1153 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1154 SDHCI_UNLOCK(slot); 1155 return (err); 1156 } 1157 1158 int 1159 sdhci_generic_release_host(device_t brdev, device_t reqdev) 1160 { 1161 struct sdhci_slot *slot = device_get_ivars(reqdev); 1162 1163 SDHCI_LOCK(slot); 1164 /* Deactivate led. */ 1165 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 1166 slot->bus_busy--; 1167 SDHCI_UNLOCK(slot); 1168 wakeup(slot); 1169 return (0); 1170 } 1171 1172 static void 1173 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1174 { 1175 1176 if (!slot->curcmd) { 1177 slot_printf(slot, "Got command interrupt 0x%08x, but " 1178 "there is no active command.\n", intmask); 1179 sdhci_dumpregs(slot); 1180 return; 1181 } 1182 if (intmask & SDHCI_INT_TIMEOUT) 1183 slot->curcmd->error = MMC_ERR_TIMEOUT; 1184 else if (intmask & SDHCI_INT_CRC) 1185 slot->curcmd->error = MMC_ERR_BADCRC; 1186 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1187 slot->curcmd->error = MMC_ERR_FIFO; 1188 1189 sdhci_finish_command(slot); 1190 } 1191 1192 static void 1193 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1194 { 1195 1196 if (!slot->curcmd) { 1197 slot_printf(slot, "Got data interrupt 0x%08x, but " 1198 "there is no active command.\n", intmask); 1199 sdhci_dumpregs(slot); 1200 return; 1201 } 1202 if (slot->curcmd->data == NULL && 1203 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1204 slot_printf(slot, "Got data interrupt 0x%08x, but " 1205 "there is no active data operation.\n", 1206 intmask); 1207 sdhci_dumpregs(slot); 1208 return; 1209 } 1210 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1211 slot->curcmd->error = MMC_ERR_TIMEOUT; 1212 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1213 slot->curcmd->error = MMC_ERR_BADCRC; 1214 if (slot->curcmd->data == NULL && 1215 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1216 SDHCI_INT_DMA_END))) { 1217 slot_printf(slot, "Got data interrupt 0x%08x, but " 1218 "there is busy-only command.\n", intmask); 1219 sdhci_dumpregs(slot); 1220 slot->curcmd->error = MMC_ERR_INVALID; 1221 } 1222 if (slot->curcmd->error) { 1223 /* No need to continue after any error. */ 1224 goto done; 1225 } 1226 1227 /* Handle PIO interrupt. */ 1228 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { 1229 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) && 1230 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) { 1231 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, &intmask); 1232 slot->flags |= PLATFORM_DATA_STARTED; 1233 } else 1234 sdhci_transfer_pio(slot); 1235 } 1236 /* Handle DMA border. */ 1237 if (intmask & SDHCI_INT_DMA_END) { 1238 struct mmc_data *data = slot->curcmd->data; 1239 size_t left; 1240 1241 /* Unload DMA buffer... */ 1242 left = data->len - slot->offset; 1243 if (data->flags & MMC_DATA_READ) { 1244 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1245 BUS_DMASYNC_POSTREAD); 1246 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1247 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1248 } else { 1249 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1250 BUS_DMASYNC_POSTWRITE); 1251 } 1252 /* ... and reload it again. */ 1253 slot->offset += DMA_BLOCK_SIZE; 1254 left = data->len - slot->offset; 1255 if (data->flags & MMC_DATA_READ) { 1256 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1257 BUS_DMASYNC_PREREAD); 1258 } else { 1259 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 1260 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1261 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1262 BUS_DMASYNC_PREWRITE); 1263 } 1264 /* Interrupt aggregation: Mask border interrupt 1265 * for the last page. */ 1266 if (left == DMA_BLOCK_SIZE) { 1267 slot->intmask &= ~SDHCI_INT_DMA_END; 1268 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1269 } 1270 /* Restart DMA. */ 1271 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1272 } 1273 /* We have got all data. */ 1274 if (intmask & SDHCI_INT_DATA_END) { 1275 if (slot->flags & PLATFORM_DATA_STARTED) { 1276 slot->flags &= ~PLATFORM_DATA_STARTED; 1277 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1278 } else { 1279 sdhci_finish_data(slot); 1280 } 1281 } 1282 done: 1283 if (slot->curcmd != NULL && slot->curcmd->error != 0) { 1284 if (slot->flags & PLATFORM_DATA_STARTED) { 1285 slot->flags &= ~PLATFORM_DATA_STARTED; 1286 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1287 } else 1288 sdhci_finish_data(slot); 1289 return; 1290 } 1291 } 1292 1293 static void 1294 sdhci_acmd_irq(struct sdhci_slot *slot) 1295 { 1296 uint16_t err; 1297 1298 err = RD4(slot, SDHCI_ACMD12_ERR); 1299 if (!slot->curcmd) { 1300 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1301 "there is no active command.\n", err); 1302 sdhci_dumpregs(slot); 1303 return; 1304 } 1305 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1306 sdhci_reset(slot, SDHCI_RESET_CMD); 1307 } 1308 1309 void 1310 sdhci_generic_intr(struct sdhci_slot *slot) 1311 { 1312 uint32_t intmask; 1313 1314 SDHCI_LOCK(slot); 1315 /* Read slot interrupt status. */ 1316 intmask = RD4(slot, SDHCI_INT_STATUS); 1317 if (intmask == 0 || intmask == 0xffffffff) { 1318 SDHCI_UNLOCK(slot); 1319 return; 1320 } 1321 if (sdhci_debug > 2) 1322 slot_printf(slot, "Interrupt %#x\n", intmask); 1323 1324 /* Handle card presence interrupts. */ 1325 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1326 WR4(slot, SDHCI_INT_STATUS, intmask & 1327 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1328 1329 if (intmask & SDHCI_INT_CARD_REMOVE) { 1330 if (bootverbose || sdhci_debug) 1331 slot_printf(slot, "Card removed\n"); 1332 callout_stop(&slot->card_callout); 1333 taskqueue_enqueue(taskqueue_swi, 1334 &slot->card_task); 1335 } 1336 if (intmask & SDHCI_INT_CARD_INSERT) { 1337 if (bootverbose || sdhci_debug) 1338 slot_printf(slot, "Card inserted\n"); 1339 callout_reset(&slot->card_callout, hz / 2, 1340 sdhci_card_delay, slot); 1341 } 1342 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1343 } 1344 /* Handle command interrupts. */ 1345 if (intmask & SDHCI_INT_CMD_MASK) { 1346 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1347 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1348 } 1349 /* Handle data interrupts. */ 1350 if (intmask & SDHCI_INT_DATA_MASK) { 1351 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1352 /* Dont call data_irq in case of errored command */ 1353 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0) 1354 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1355 } 1356 /* Handle AutoCMD12 error interrupt. */ 1357 if (intmask & SDHCI_INT_ACMD12ERR) { 1358 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1359 sdhci_acmd_irq(slot); 1360 } 1361 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1362 intmask &= ~SDHCI_INT_ACMD12ERR; 1363 intmask &= ~SDHCI_INT_ERROR; 1364 /* Handle bus power interrupt. */ 1365 if (intmask & SDHCI_INT_BUS_POWER) { 1366 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1367 slot_printf(slot, 1368 "Card is consuming too much power!\n"); 1369 intmask &= ~SDHCI_INT_BUS_POWER; 1370 } 1371 /* The rest is unknown. */ 1372 if (intmask) { 1373 WR4(slot, SDHCI_INT_STATUS, intmask); 1374 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1375 intmask); 1376 sdhci_dumpregs(slot); 1377 } 1378 1379 SDHCI_UNLOCK(slot); 1380 } 1381 1382 int 1383 sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 1384 { 1385 struct sdhci_slot *slot = device_get_ivars(child); 1386 1387 switch (which) { 1388 default: 1389 return (EINVAL); 1390 case MMCBR_IVAR_BUS_MODE: 1391 *(int *)result = slot->host.ios.bus_mode; 1392 break; 1393 case MMCBR_IVAR_BUS_WIDTH: 1394 *(int *)result = slot->host.ios.bus_width; 1395 break; 1396 case MMCBR_IVAR_CHIP_SELECT: 1397 *(int *)result = slot->host.ios.chip_select; 1398 break; 1399 case MMCBR_IVAR_CLOCK: 1400 *(int *)result = slot->host.ios.clock; 1401 break; 1402 case MMCBR_IVAR_F_MIN: 1403 *(int *)result = slot->host.f_min; 1404 break; 1405 case MMCBR_IVAR_F_MAX: 1406 *(int *)result = slot->host.f_max; 1407 break; 1408 case MMCBR_IVAR_HOST_OCR: 1409 *(int *)result = slot->host.host_ocr; 1410 break; 1411 case MMCBR_IVAR_MODE: 1412 *(int *)result = slot->host.mode; 1413 break; 1414 case MMCBR_IVAR_OCR: 1415 *(int *)result = slot->host.ocr; 1416 break; 1417 case MMCBR_IVAR_POWER_MODE: 1418 *(int *)result = slot->host.ios.power_mode; 1419 break; 1420 case MMCBR_IVAR_VDD: 1421 *(int *)result = slot->host.ios.vdd; 1422 break; 1423 case MMCBR_IVAR_CAPS: 1424 *(int *)result = slot->host.caps; 1425 break; 1426 case MMCBR_IVAR_TIMING: 1427 *(int *)result = slot->host.ios.timing; 1428 break; 1429 case MMCBR_IVAR_MAX_DATA: 1430 *(int *)result = 65535; 1431 break; 1432 } 1433 return (0); 1434 } 1435 1436 int 1437 sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1438 { 1439 struct sdhci_slot *slot = device_get_ivars(child); 1440 1441 switch (which) { 1442 default: 1443 return (EINVAL); 1444 case MMCBR_IVAR_BUS_MODE: 1445 slot->host.ios.bus_mode = value; 1446 break; 1447 case MMCBR_IVAR_BUS_WIDTH: 1448 slot->host.ios.bus_width = value; 1449 break; 1450 case MMCBR_IVAR_CHIP_SELECT: 1451 slot->host.ios.chip_select = value; 1452 break; 1453 case MMCBR_IVAR_CLOCK: 1454 if (value > 0) { 1455 uint32_t max_clock; 1456 uint32_t clock; 1457 int i; 1458 1459 max_clock = slot->max_clk; 1460 clock = max_clock; 1461 1462 if (slot->version < SDHCI_SPEC_300) { 1463 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 1464 i <<= 1) { 1465 if (clock <= value) 1466 break; 1467 clock >>= 1; 1468 } 1469 } 1470 else { 1471 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 1472 i += 2) { 1473 if (clock <= value) 1474 break; 1475 clock = max_clock / (i + 2); 1476 } 1477 } 1478 1479 slot->host.ios.clock = clock; 1480 } else 1481 slot->host.ios.clock = 0; 1482 break; 1483 case MMCBR_IVAR_MODE: 1484 slot->host.mode = value; 1485 break; 1486 case MMCBR_IVAR_OCR: 1487 slot->host.ocr = value; 1488 break; 1489 case MMCBR_IVAR_POWER_MODE: 1490 slot->host.ios.power_mode = value; 1491 break; 1492 case MMCBR_IVAR_VDD: 1493 slot->host.ios.vdd = value; 1494 break; 1495 case MMCBR_IVAR_TIMING: 1496 slot->host.ios.timing = value; 1497 break; 1498 case MMCBR_IVAR_CAPS: 1499 case MMCBR_IVAR_HOST_OCR: 1500 case MMCBR_IVAR_F_MIN: 1501 case MMCBR_IVAR_F_MAX: 1502 case MMCBR_IVAR_MAX_DATA: 1503 return (EINVAL); 1504 } 1505 return (0); 1506 } 1507 1508 MODULE_VERSION(sdhci, 1); 1509