1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * $FreeBSD: src/sys/dev/sdhci/sdhci.c,v 1.8 2009/02/17 19:12:15 mav Exp $ 26 */ 27 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/bus.h> 31 #include <sys/callout.h> 32 #include <sys/conf.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/module.h> 36 #include <sys/spinlock.h> 37 #include <sys/resource.h> 38 #include <sys/rman.h> 39 #include <sys/sysctl.h> 40 #include <sys/taskqueue.h> 41 42 #include <bus/mmc/bridge.h> 43 #include <bus/mmc/mmcreg.h> 44 #include <bus/mmc/mmcbrvar.h> 45 46 #include "mmcbr_if.h" 47 #include "sdhci.h" 48 #include "sdhci_if.h" 49 50 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 51 52 int sdhci_debug = 0; 53 TUNABLE_INT("hw.sdhci.debug", &sdhci_debug); 54 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level"); 55 56 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 57 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 58 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 59 #define RD_MULTI_4(slot, off, ptr, count) \ 60 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 61 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 62 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 63 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 64 #define WR_MULTI_4(slot, off, ptr, count) \ 65 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 66 67 static int slot_printf(struct sdhci_slot *, const char *, ...) 68 __printflike(2, 3); 69 70 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 71 static void sdhci_start(struct sdhci_slot *slot); 72 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 73 74 static void sdhci_card_task(void *, int); 75 76 /* helper routines */ 77 #define SDHCI_LOCK(_slot) lockmgr(&(_slot)->lock, LK_EXCLUSIVE) 78 #define SDHCI_UNLOCK(_slot) lockmgr(&(_slot)->lock, LK_RELEASE) 79 #define SDHCI_LOCK_INIT(_slot) lockinit(&(_slot)->lock, "sdhci", 0, LK_CANRECURSE) 80 #define SDHCI_LOCK_DESTROY(_slot) lockuninit(&(_slot)->lock); 81 #define SDHCI_ASSERT_LOCKED(_slot) KKASSERT(lockstatus(&(_slot)->lock, curthread) != 0); 82 #define SDHCI_ASSERT_UNLOCKED(_slot) KKASSERT(lockstatus(&(_slot)->lock, curthread) == 0); 83 84 #define SDHCI_DEFAULT_MAX_FREQ 50 85 86 #define SDHCI_200_MAX_DIVIDER 256 87 #define SDHCI_300_MAX_DIVIDER 2046 88 89 /* 90 * Broadcom BCM577xx Controller Constants 91 */ 92 #define BCM577XX_DEFAULT_MAX_DIVIDER 256 /* Maximum divider supported by the default clock source. */ 93 #define BCM577XX_ALT_CLOCK_BASE 63000000 /* Alternative clock's base frequency. */ 94 95 #define BCM577XX_HOST_CONTROL 0x198 96 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF 97 #define BCM577XX_CTRL_CLKSEL_SHIFT 12 98 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0 99 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3 100 101 102 static void 103 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 104 { 105 if (error != 0) { 106 kprintf("getaddr: error %d\n", error); 107 return; 108 } 109 *(bus_addr_t *)arg = segs[0].ds_addr; 110 } 111 112 static int 113 slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 114 { 115 __va_list ap; 116 int retval; 117 118 retval = kprintf("%s-slot%d: ", 119 device_get_nameunit(slot->bus), slot->num); 120 121 __va_start(ap, fmt); 122 retval += kvprintf(fmt, ap); 123 __va_end(ap); 124 return (retval); 125 } 126 127 static void 128 sdhci_dumpregs(struct sdhci_slot *slot) 129 { 130 slot_printf(slot, 131 "============== REGISTER DUMP ==============\n"); 132 133 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 134 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 135 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 136 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 137 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 138 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 139 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 140 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 141 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 142 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 143 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 144 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 145 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 146 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 147 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 148 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 149 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n", 150 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS)); 151 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n", 152 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT)); 153 154 slot_printf(slot, 155 "===========================================\n"); 156 } 157 158 static void 159 sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 160 { 161 int timeout; 162 163 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 164 if (!(RD4(slot, SDHCI_PRESENT_STATE) & 165 SDHCI_CARD_PRESENT)) 166 return; 167 } 168 169 /* Some controllers need this kick or reset won't work. */ 170 if ((mask & SDHCI_RESET_ALL) == 0 && 171 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 172 uint32_t clock; 173 174 /* This is to force an update */ 175 clock = slot->clock; 176 slot->clock = 0; 177 sdhci_set_clock(slot, clock); 178 } 179 180 if (mask & SDHCI_RESET_ALL) { 181 slot->clock = 0; 182 slot->power = 0; 183 } 184 185 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 186 187 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) { 188 /* 189 * Resets on TI OMAPs and AM335x are incompatible with SDHCI 190 * specification. The reset bit has internal propagation delay, 191 * so a fast read after write returns 0 even if reset process is 192 * in progress. The workaround is to poll for 1 before polling 193 * for 0. In the worst case, if we miss seeing it asserted the 194 * time we spent waiting is enough to ensure the reset finishes. 195 */ 196 timeout = 10000; 197 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) { 198 if (timeout <= 0) 199 break; 200 timeout--; 201 DELAY(1); 202 } 203 } 204 205 /* Wait max 100 ms */ 206 timeout = 10000; 207 /* Controller clears the bits when it's done */ 208 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) { 209 if (timeout <= 0) { 210 slot_printf(slot, "Reset 0x%x never completed.\n", 211 mask); 212 sdhci_dumpregs(slot); 213 return; 214 } 215 timeout--; 216 DELAY(10); 217 } 218 } 219 220 static void 221 sdhci_init(struct sdhci_slot *slot) 222 { 223 224 sdhci_reset(slot, SDHCI_RESET_ALL); 225 226 /* Enable interrupts. */ 227 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 228 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 229 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 230 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | 231 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 232 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 233 SDHCI_INT_ACMD12ERR; 234 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 235 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 236 } 237 238 static void 239 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 240 { 241 uint32_t clk_base; 242 uint32_t clk_sel; 243 uint32_t res; 244 uint16_t clk; 245 uint16_t div; 246 int timeout; 247 248 if (clock == slot->clock) 249 return; 250 slot->clock = clock; 251 252 /* Turn off the clock. */ 253 clk = RD2(slot, SDHCI_CLOCK_CONTROL); 254 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); 255 /* If no clock requested - left it so. */ 256 if (clock == 0) 257 return; 258 259 /* Determine the clock base frequency */ 260 clk_base = slot->max_clk; 261 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) { 262 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & BCM577XX_CTRL_CLKSEL_MASK; 263 264 /* Select clock source appropriate for the requested frequency. */ 265 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) { 266 clk_base = BCM577XX_ALT_CLOCK_BASE; 267 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ << BCM577XX_CTRL_CLKSEL_SHIFT); 268 } else { 269 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT << BCM577XX_CTRL_CLKSEL_SHIFT); 270 } 271 272 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel); 273 } 274 275 /* Recalculate timeout clock frequency based on the new sd clock. */ 276 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 277 slot->timeout_clk = slot->clock / 1000; 278 279 if (slot->version < SDHCI_SPEC_300) { 280 /* Looking for highest freq <= clock. */ 281 res = clk_base; 282 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { 283 if (res <= clock) 284 break; 285 res >>= 1; 286 } 287 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 288 div >>= 1; 289 } 290 else { 291 /* Version 3.0 divisors are multiples of two up to 1023*2 */ 292 if (clock >= clk_base) 293 div = 0; 294 else { 295 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { 296 if ((clk_base / div) <= clock) 297 break; 298 } 299 } 300 div >>= 1; 301 } 302 303 if (bootverbose || sdhci_debug) 304 slot_printf(slot, "Divider %d for freq %d (base %d)\n", 305 div, clock, clk_base); 306 307 /* Now we have got divider, set it. */ 308 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 309 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 310 << SDHCI_DIVIDER_HI_SHIFT; 311 312 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 313 /* Enable clock. */ 314 clk |= SDHCI_CLOCK_INT_EN; 315 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 316 /* Wait up to 10 ms until it stabilize. */ 317 timeout = 10; 318 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 319 & SDHCI_CLOCK_INT_STABLE)) { 320 if (timeout == 0) { 321 slot_printf(slot, 322 "Internal clock never stabilised.\n"); 323 sdhci_dumpregs(slot); 324 return; 325 } 326 timeout--; 327 DELAY(1000); 328 } 329 /* Pass clock signal to the bus. */ 330 clk |= SDHCI_CLOCK_CARD_EN; 331 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 332 } 333 334 static void 335 sdhci_set_power(struct sdhci_slot *slot, u_char power) 336 { 337 uint8_t pwr; 338 339 if (slot->power == power) 340 return; 341 342 slot->power = power; 343 344 /* Turn off the power. */ 345 pwr = 0; 346 WR1(slot, SDHCI_POWER_CONTROL, pwr); 347 /* If power down requested - left it so. */ 348 if (power == 0) 349 return; 350 /* Set voltage. */ 351 switch (1 << power) { 352 case MMC_OCR_LOW_VOLTAGE: 353 pwr |= SDHCI_POWER_180; 354 break; 355 case MMC_OCR_290_300: 356 case MMC_OCR_300_310: 357 pwr |= SDHCI_POWER_300; 358 break; 359 case MMC_OCR_320_330: 360 case MMC_OCR_330_340: 361 pwr |= SDHCI_POWER_330; 362 break; 363 } 364 WR1(slot, SDHCI_POWER_CONTROL, pwr); 365 /* Turn on the power. */ 366 pwr |= SDHCI_POWER_ON; 367 WR1(slot, SDHCI_POWER_CONTROL, pwr); 368 } 369 370 static void 371 sdhci_read_block_pio(struct sdhci_slot *slot) 372 { 373 uint32_t data; 374 char *buffer; 375 size_t left; 376 377 buffer = slot->curcmd->data->data; 378 buffer += slot->offset; 379 /* Transfer one block at a time. */ 380 left = min(512, slot->curcmd->data->len - slot->offset); 381 slot->offset += left; 382 383 /* If we are too fast, broken controllers return zeroes. */ 384 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 385 DELAY(10); 386 /* Handle unaligned and aligned buffer cases. */ 387 if ((intptr_t)buffer & 3) { 388 while (left > 3) { 389 data = RD4(slot, SDHCI_BUFFER); 390 buffer[0] = data; 391 buffer[1] = (data >> 8); 392 buffer[2] = (data >> 16); 393 buffer[3] = (data >> 24); 394 buffer += 4; 395 left -= 4; 396 } 397 } else { 398 RD_MULTI_4(slot, SDHCI_BUFFER, 399 (uint32_t *)buffer, left >> 2); 400 left &= 3; 401 } 402 /* Handle uneven size case. */ 403 if (left > 0) { 404 data = RD4(slot, SDHCI_BUFFER); 405 while (left > 0) { 406 *(buffer++) = data; 407 data >>= 8; 408 left--; 409 } 410 } 411 } 412 413 static void 414 sdhci_write_block_pio(struct sdhci_slot *slot) 415 { 416 uint32_t data = 0; 417 char *buffer; 418 size_t left; 419 420 buffer = slot->curcmd->data->data; 421 buffer += slot->offset; 422 /* Transfer one block at a time. */ 423 left = min(512, slot->curcmd->data->len - slot->offset); 424 slot->offset += left; 425 426 /* Handle unaligned and aligned buffer cases. */ 427 if ((intptr_t)buffer & 3) { 428 while (left > 3) { 429 data = buffer[0] + 430 (buffer[1] << 8) + 431 (buffer[2] << 16) + 432 (buffer[3] << 24); 433 left -= 4; 434 buffer += 4; 435 WR4(slot, SDHCI_BUFFER, data); 436 } 437 } else { 438 WR_MULTI_4(slot, SDHCI_BUFFER, 439 (uint32_t *)buffer, left >> 2); 440 left &= 3; 441 } 442 /* Handle uneven size case. */ 443 if (left > 0) { 444 while (left > 0) { 445 data <<= 8; 446 data += *(buffer++); 447 left--; 448 } 449 WR4(slot, SDHCI_BUFFER, data); 450 } 451 } 452 453 static void 454 sdhci_transfer_pio(struct sdhci_slot *slot) 455 { 456 457 /* Read as many blocks as possible. */ 458 if (slot->curcmd->data->flags & MMC_DATA_READ) { 459 while (RD4(slot, SDHCI_PRESENT_STATE) & 460 SDHCI_DATA_AVAILABLE) { 461 sdhci_read_block_pio(slot); 462 if (slot->offset >= slot->curcmd->data->len) 463 break; 464 } 465 } else { 466 while (RD4(slot, SDHCI_PRESENT_STATE) & 467 SDHCI_SPACE_AVAILABLE) { 468 sdhci_write_block_pio(slot); 469 if (slot->offset >= slot->curcmd->data->len) 470 break; 471 } 472 } 473 } 474 475 static void 476 sdhci_card_delay(void *arg) 477 { 478 struct sdhci_slot *slot = arg; 479 480 taskqueue_enqueue(taskqueue_swi, &slot->card_task); 481 } 482 483 static void 484 sdhci_card_task(void *arg, int pending) 485 { 486 struct sdhci_slot *slot = arg; 487 488 SDHCI_LOCK(slot); 489 if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) { 490 if (slot->dev == NULL) { 491 /* If card is present - attach mmc bus. */ 492 slot->dev = device_add_child(slot->bus, "mmc", -1); 493 device_set_ivars(slot->dev, slot); 494 SDHCI_UNLOCK(slot); 495 device_probe_and_attach(slot->dev); 496 } else 497 SDHCI_UNLOCK(slot); 498 } else { 499 if (slot->dev != NULL) { 500 /* If no card present - detach mmc bus. */ 501 device_t d = slot->dev; 502 slot->dev = NULL; 503 SDHCI_UNLOCK(slot); 504 device_delete_child(slot->bus, d); 505 } else 506 SDHCI_UNLOCK(slot); 507 } 508 } 509 510 int 511 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 512 { 513 uint32_t caps, freq; 514 int err; 515 516 SDHCI_LOCK_INIT(slot); 517 slot->num = num; 518 slot->bus = dev; 519 520 /* Allocate DMA tag. */ 521 err = bus_dma_tag_create(bus_get_dma_tag(dev), 522 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 523 BUS_SPACE_MAXADDR, NULL, NULL, 524 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 525 BUS_DMA_ALLOCNOW, 526 &slot->dmatag); 527 if (err != 0) { 528 device_printf(dev, "Can't create DMA tag\n"); 529 SDHCI_LOCK_DESTROY(slot); 530 return (err); 531 } 532 /* Allocate DMA memory. */ 533 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 534 BUS_DMA_NOWAIT, &slot->dmamap); 535 if (err != 0) { 536 device_printf(dev, "Can't alloc DMA memory\n"); 537 SDHCI_LOCK_DESTROY(slot); 538 return (err); 539 } 540 /* Map the memory. */ 541 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 542 (void *)slot->dmamem, DMA_BLOCK_SIZE, 543 sdhci_getaddr, &slot->paddr, 0); 544 if (err != 0 || slot->paddr == 0) { 545 device_printf(dev, "Can't load DMA memory\n"); 546 SDHCI_LOCK_DESTROY(slot); 547 if(err) 548 return (err); 549 else 550 return (EFAULT); 551 } 552 553 /* Initialize slot. */ 554 sdhci_init(slot); 555 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 556 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 557 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) 558 caps = slot->caps; 559 else 560 caps = RD4(slot, SDHCI_CAPABILITIES); 561 /* Calculate base clock frequency. */ 562 if (slot->version >= SDHCI_SPEC_300) 563 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 564 SDHCI_CLOCK_BASE_SHIFT; 565 else 566 freq = (caps & SDHCI_CLOCK_BASE_MASK) >> 567 SDHCI_CLOCK_BASE_SHIFT; 568 if (freq != 0) 569 slot->max_clk = freq * 1000000; 570 /* 571 * If the frequency wasn't in the capabilities and the hardware driver 572 * hasn't already set max_clk we're probably not going to work right 573 * with an assumption, so complain about it. 574 */ 575 if (slot->max_clk == 0) { 576 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000; 577 device_printf(dev, "Hardware doesn't specify base clock " 578 "frequency, using %dMHz as default.\n", SDHCI_DEFAULT_MAX_FREQ); 579 } 580 /* Calculate timeout clock frequency. */ 581 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 582 slot->timeout_clk = slot->max_clk / 1000; 583 } else { 584 slot->timeout_clk = 585 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 586 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 587 slot->timeout_clk *= 1000; 588 } 589 /* 590 * If the frequency wasn't in the capabilities and the hardware driver 591 * hasn't already set timeout_clk we'll probably work okay using the 592 * max timeout, but still mention it. 593 */ 594 if (slot->timeout_clk == 0) { 595 device_printf(dev, "Hardware doesn't specify timeout clock " 596 "frequency, setting BROKEN_TIMEOUT quirk.\n"); 597 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 598 } 599 600 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); 601 slot->host.f_max = slot->max_clk; 602 slot->host.host_ocr = 0; 603 if (caps & SDHCI_CAN_VDD_330) 604 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 605 if (caps & SDHCI_CAN_VDD_300) 606 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 607 if (caps & SDHCI_CAN_VDD_180) 608 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 609 if (slot->host.host_ocr == 0) { 610 device_printf(dev, "Hardware doesn't report any " 611 "support voltages.\n"); 612 } 613 slot->host.caps = MMC_CAP_4_BIT_DATA; 614 if (caps & SDHCI_CAN_DO_8BITBUS) 615 slot->host.caps |= MMC_CAP_8_BIT_DATA; 616 if (caps & SDHCI_CAN_DO_HISPD) 617 slot->host.caps |= MMC_CAP_HSPEED; 618 /* Decide if we have usable DMA. */ 619 if (caps & SDHCI_CAN_DO_DMA) 620 slot->opt |= SDHCI_HAVE_DMA; 621 622 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 623 slot->opt &= ~SDHCI_HAVE_DMA; 624 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 625 slot->opt |= SDHCI_HAVE_DMA; 626 627 /* 628 * Use platform-provided transfer backend 629 * with PIO as a fallback mechanism 630 */ 631 if (slot->opt & SDHCI_PLATFORM_TRANSFER) 632 slot->opt &= ~SDHCI_HAVE_DMA; 633 634 if (bootverbose || sdhci_debug) { 635 slot_printf(slot, "%uMHz%s %s%s%s%s %s\n", 636 slot->max_clk / 1000000, 637 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 638 (caps & MMC_CAP_8_BIT_DATA) ? "8bits" : 639 ((caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"), 640 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 641 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 642 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", 643 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); 644 sdhci_dumpregs(slot); 645 } 646 647 slot->timeout = 10; 648 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus), 649 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO, 650 "timeout", CTLFLAG_RW, &slot->timeout, 0, 651 "Maximum timeout for SDHCI transfers (in secs)"); 652 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 653 callout_init(&slot->card_callout); 654 callout_init_lk(&slot->timeout_callout, &slot->lock); 655 return (0); 656 } 657 658 void 659 sdhci_start_slot(struct sdhci_slot *slot) 660 { 661 sdhci_card_task(slot, 0); 662 } 663 664 int 665 sdhci_cleanup_slot(struct sdhci_slot *slot) 666 { 667 device_t d; 668 669 callout_drain(&slot->timeout_callout); 670 callout_drain(&slot->card_callout); 671 taskqueue_drain(taskqueue_swi, &slot->card_task); 672 673 SDHCI_LOCK(slot); 674 d = slot->dev; 675 slot->dev = NULL; 676 SDHCI_UNLOCK(slot); 677 if (d != NULL) 678 device_delete_child(slot->bus, d); 679 680 SDHCI_LOCK(slot); 681 sdhci_reset(slot, SDHCI_RESET_ALL); 682 SDHCI_UNLOCK(slot); 683 bus_dmamap_unload(slot->dmatag, slot->dmamap); 684 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 685 bus_dma_tag_destroy(slot->dmatag); 686 687 SDHCI_LOCK_DESTROY(slot); 688 689 return (0); 690 } 691 692 int 693 sdhci_generic_suspend(struct sdhci_slot *slot) 694 { 695 sdhci_reset(slot, SDHCI_RESET_ALL); 696 697 return (0); 698 } 699 700 int 701 sdhci_generic_resume(struct sdhci_slot *slot) 702 { 703 sdhci_init(slot); 704 705 return (0); 706 } 707 708 uint32_t 709 sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot) 710 { 711 if (slot->version >= SDHCI_SPEC_300) 712 return (slot->max_clk / SDHCI_300_MAX_DIVIDER); 713 else 714 return (slot->max_clk / SDHCI_200_MAX_DIVIDER); 715 } 716 717 int 718 sdhci_generic_update_ios(device_t brdev, device_t reqdev) 719 { 720 struct sdhci_slot *slot = device_get_ivars(reqdev); 721 struct mmc_ios *ios = &slot->host.ios; 722 723 SDHCI_LOCK(slot); 724 /* Do full reset on bus power down to clear from any state. */ 725 if (ios->power_mode == power_off) { 726 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 727 sdhci_init(slot); 728 } 729 /* Configure the bus. */ 730 sdhci_set_clock(slot, ios->clock); 731 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 732 if (ios->bus_width == bus_width_8) { 733 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 734 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 735 } else if (ios->bus_width == bus_width_4) { 736 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 737 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 738 } else if (ios->bus_width == bus_width_1) { 739 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 740 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 741 } else { 742 panic("Invalid bus width: %d", ios->bus_width); 743 } 744 if (ios->timing == bus_timing_hs && 745 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 746 slot->hostctrl |= SDHCI_CTRL_HISPD; 747 else 748 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 749 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 750 /* Some controllers like reset after bus changes. */ 751 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 752 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 753 754 SDHCI_UNLOCK(slot); 755 return (0); 756 } 757 758 static void 759 sdhci_req_done(struct sdhci_slot *slot) 760 { 761 struct mmc_request *req; 762 763 if (slot->req != NULL && slot->curcmd != NULL) { 764 callout_stop(&slot->timeout_callout); 765 req = slot->req; 766 slot->req = NULL; 767 slot->curcmd = NULL; 768 req->done(req); 769 } 770 } 771 772 static void 773 sdhci_timeout(void *arg) 774 { 775 struct sdhci_slot *slot = arg; 776 777 if (slot->curcmd != NULL) { 778 slot_printf(slot, " Controller timeout\n"); 779 sdhci_dumpregs(slot); 780 sdhci_reset(slot, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 781 slot->curcmd->error = MMC_ERR_TIMEOUT; 782 sdhci_req_done(slot); 783 } else { 784 slot_printf(slot, " Spurious timeout - no active command\n"); 785 } 786 } 787 788 static void 789 sdhci_set_transfer_mode(struct sdhci_slot *slot, 790 struct mmc_data *data) 791 { 792 uint16_t mode; 793 794 if (data == NULL) 795 return; 796 797 mode = SDHCI_TRNS_BLK_CNT_EN; 798 if (data->len > 512) 799 mode |= SDHCI_TRNS_MULTI; 800 if (data->flags & MMC_DATA_READ) 801 mode |= SDHCI_TRNS_READ; 802 if (slot->req->stop) 803 mode |= SDHCI_TRNS_ACMD12; 804 if (slot->flags & SDHCI_USE_DMA) 805 mode |= SDHCI_TRNS_DMA; 806 807 WR2(slot, SDHCI_TRANSFER_MODE, mode); 808 } 809 810 static void 811 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 812 { 813 int flags, timeout; 814 uint32_t mask, state; 815 816 slot->curcmd = cmd; 817 slot->cmd_done = 0; 818 819 cmd->error = MMC_ERR_NONE; 820 821 /* This flags combination is not supported by controller. */ 822 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 823 slot_printf(slot, "Unsupported response type!\n"); 824 cmd->error = MMC_ERR_FAILED; 825 sdhci_req_done(slot); 826 return; 827 } 828 829 /* Read controller present state. */ 830 state = RD4(slot, SDHCI_PRESENT_STATE); 831 /* Do not issue command if there is no card, clock or power. 832 * Controller will not detect timeout without clock active. */ 833 if ((state & SDHCI_CARD_PRESENT) == 0 || 834 slot->power == 0 || 835 slot->clock == 0) { 836 cmd->error = MMC_ERR_FAILED; 837 sdhci_req_done(slot); 838 return; 839 } 840 /* Always wait for free CMD bus. */ 841 mask = SDHCI_CMD_INHIBIT; 842 /* Wait for free DAT if we have data or busy signal. */ 843 if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) 844 mask |= SDHCI_DAT_INHIBIT; 845 /* We shouldn't wait for DAT for stop commands. */ 846 if (cmd == slot->req->stop) 847 mask &= ~SDHCI_DAT_INHIBIT; 848 /* 849 * Wait for bus no more then 250 ms. Typically there will be no wait 850 * here at all, but when writing a crash dump we may be bypassing the 851 * host platform's interrupt handler, and in some cases that handler 852 * may be working around hardware quirks such as not respecting r1b 853 * busy indications. In those cases, this wait-loop serves the purpose 854 * of waiting for the prior command and data transfers to be done, and 855 * SD cards are allowed to take up to 250ms for write and erase ops. 856 * (It's usually more like 20-30ms in the real world.) 857 */ 858 timeout = 250; 859 while (state & mask) { 860 if (timeout == 0) { 861 slot_printf(slot, "Controller never released " 862 "inhibit bit(s).\n"); 863 sdhci_dumpregs(slot); 864 cmd->error = MMC_ERR_FAILED; 865 sdhci_req_done(slot); 866 return; 867 } 868 timeout--; 869 DELAY(1000); 870 state = RD4(slot, SDHCI_PRESENT_STATE); 871 } 872 873 /* Prepare command flags. */ 874 if (!(cmd->flags & MMC_RSP_PRESENT)) 875 flags = SDHCI_CMD_RESP_NONE; 876 else if (cmd->flags & MMC_RSP_136) 877 flags = SDHCI_CMD_RESP_LONG; 878 else if (cmd->flags & MMC_RSP_BUSY) 879 flags = SDHCI_CMD_RESP_SHORT_BUSY; 880 else 881 flags = SDHCI_CMD_RESP_SHORT; 882 if (cmd->flags & MMC_RSP_CRC) 883 flags |= SDHCI_CMD_CRC; 884 if (cmd->flags & MMC_RSP_OPCODE) 885 flags |= SDHCI_CMD_INDEX; 886 if (cmd->data) 887 flags |= SDHCI_CMD_DATA; 888 if (cmd->opcode == MMC_STOP_TRANSMISSION) 889 flags |= SDHCI_CMD_TYPE_ABORT; 890 /* Prepare data. */ 891 sdhci_start_data(slot, cmd->data); 892 /* 893 * Interrupt aggregation: To reduce total number of interrupts 894 * group response interrupt with data interrupt when possible. 895 * If there going to be data interrupt, mask response one. 896 */ 897 if (slot->data_done == 0) { 898 WR4(slot, SDHCI_SIGNAL_ENABLE, 899 slot->intmask &= ~SDHCI_INT_RESPONSE); 900 } 901 /* Set command argument. */ 902 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 903 /* Set data transfer mode. */ 904 sdhci_set_transfer_mode(slot, cmd->data); 905 /* Start command. */ 906 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 907 /* Start timeout callout. */ 908 callout_reset(&slot->timeout_callout, slot->timeout * hz, 909 sdhci_timeout, slot); 910 } 911 912 static void 913 sdhci_finish_command(struct sdhci_slot *slot) 914 { 915 int i; 916 917 slot->cmd_done = 1; 918 /* Interrupt aggregation: Restore command interrupt. 919 * Main restore point for the case when command interrupt 920 * happened first. */ 921 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 922 /* In case of error - reset host and return. */ 923 if (slot->curcmd->error) { 924 sdhci_reset(slot, SDHCI_RESET_CMD); 925 sdhci_reset(slot, SDHCI_RESET_DATA); 926 sdhci_start(slot); 927 return; 928 } 929 /* If command has response - fetch it. */ 930 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 931 if (slot->curcmd->flags & MMC_RSP_136) { 932 /* CRC is stripped so we need one byte shift. */ 933 uint8_t extra = 0; 934 for (i = 0; i < 4; i++) { 935 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4); 936 if (slot->quirks & SDHCI_QUIRK_DONT_SHIFT_RESPONSE) { 937 slot->curcmd->resp[3 - i] = val; 938 } else { 939 slot->curcmd->resp[3 - i] = 940 (val << 8) | extra; 941 extra = val >> 24; 942 } 943 } 944 } else { 945 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 946 } 947 } 948 /* If data ready - finish. */ 949 if (slot->data_done) 950 sdhci_start(slot); 951 } 952 953 static void 954 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 955 { 956 uint32_t target_timeout, current_timeout; 957 uint8_t div; 958 959 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 960 slot->data_done = 1; 961 return; 962 } 963 964 slot->data_done = 0; 965 966 /* Calculate and set data timeout.*/ 967 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 968 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { 969 div = 0xe; 970 } else { 971 target_timeout = 1000000; 972 div = 0; 973 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 974 while (current_timeout < target_timeout && div < 0xE) { 975 ++div; 976 current_timeout <<= 1; 977 } 978 /* Compensate for an off-by-one error in the CaFe chip.*/ 979 if (div < 0xE && 980 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) { 981 ++div; 982 } 983 } 984 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 985 986 if (data == NULL) 987 return; 988 989 /* Use DMA if possible. */ 990 if ((slot->opt & SDHCI_HAVE_DMA)) 991 slot->flags |= SDHCI_USE_DMA; 992 /* If data is small, broken DMA may return zeroes instead of data, */ 993 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 994 (data->len <= 512)) 995 slot->flags &= ~SDHCI_USE_DMA; 996 /* Some controllers require even block sizes. */ 997 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 998 ((data->len) & 0x3)) 999 slot->flags &= ~SDHCI_USE_DMA; 1000 /* Load DMA buffer. */ 1001 if (slot->flags & SDHCI_USE_DMA) { 1002 if (data->flags & MMC_DATA_READ) { 1003 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1004 BUS_DMASYNC_PREREAD); 1005 } else { 1006 memcpy(slot->dmamem, data->data, 1007 (data->len < DMA_BLOCK_SIZE) ? 1008 data->len : DMA_BLOCK_SIZE); 1009 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1010 BUS_DMASYNC_PREWRITE); 1011 } 1012 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1013 /* Interrupt aggregation: Mask border interrupt 1014 * for the last page and unmask else. */ 1015 if (data->len == DMA_BLOCK_SIZE) 1016 slot->intmask &= ~SDHCI_INT_DMA_END; 1017 else 1018 slot->intmask |= SDHCI_INT_DMA_END; 1019 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1020 } 1021 /* Current data offset for both PIO and DMA. */ 1022 slot->offset = 0; 1023 /* Set block size and request IRQ on 4K border. */ 1024 WR2(slot, SDHCI_BLOCK_SIZE, 1025 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512)); 1026 /* Set block count. */ 1027 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 1028 } 1029 1030 void 1031 sdhci_finish_data(struct sdhci_slot *slot) 1032 { 1033 struct mmc_data *data = slot->curcmd->data; 1034 1035 /* Interrupt aggregation: Restore command interrupt. 1036 * Auxiliary restore point for the case when data interrupt 1037 * happened first. */ 1038 if (!slot->cmd_done) { 1039 WR4(slot, SDHCI_SIGNAL_ENABLE, 1040 slot->intmask |= SDHCI_INT_RESPONSE); 1041 } 1042 /* Unload rest of data from DMA buffer. */ 1043 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA)) { 1044 if (data->flags & MMC_DATA_READ) { 1045 size_t left = data->len - slot->offset; 1046 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1047 BUS_DMASYNC_POSTREAD); 1048 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1049 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1050 } else 1051 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1052 BUS_DMASYNC_POSTWRITE); 1053 } 1054 slot->data_done = 1; 1055 /* If there was error - reset the host. */ 1056 if (slot->curcmd->error) { 1057 sdhci_reset(slot, SDHCI_RESET_CMD); 1058 sdhci_reset(slot, SDHCI_RESET_DATA); 1059 sdhci_start(slot); 1060 return; 1061 } 1062 /* If we already have command response - finish. */ 1063 if (slot->cmd_done) 1064 sdhci_start(slot); 1065 } 1066 1067 static void 1068 sdhci_start(struct sdhci_slot *slot) 1069 { 1070 struct mmc_request *req; 1071 1072 req = slot->req; 1073 if (req == NULL) 1074 return; 1075 1076 if (!(slot->flags & CMD_STARTED)) { 1077 slot->flags |= CMD_STARTED; 1078 sdhci_start_command(slot, req->cmd); 1079 return; 1080 } 1081 /* We don't need this until using Auto-CMD12 feature 1082 if (!(slot->flags & STOP_STARTED) && req->stop) { 1083 slot->flags |= STOP_STARTED; 1084 sdhci_start_command(slot, req->stop); 1085 return; 1086 } 1087 */ 1088 if (sdhci_debug > 1) 1089 slot_printf(slot, "result: %d\n", req->cmd->error); 1090 if (!req->cmd->error && 1091 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 1092 sdhci_reset(slot, SDHCI_RESET_CMD); 1093 sdhci_reset(slot, SDHCI_RESET_DATA); 1094 } 1095 1096 sdhci_req_done(slot); 1097 } 1098 1099 int 1100 sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req) 1101 { 1102 struct sdhci_slot *slot = device_get_ivars(reqdev); 1103 1104 SDHCI_LOCK(slot); 1105 if (slot->req != NULL) { 1106 SDHCI_UNLOCK(slot); 1107 return (EBUSY); 1108 } 1109 if (sdhci_debug > 1) { 1110 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1111 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 1112 (req->cmd->data)?(u_int)req->cmd->data->len:0, 1113 (req->cmd->data)?req->cmd->data->flags:0); 1114 } 1115 slot->req = req; 1116 slot->flags = 0; 1117 sdhci_start(slot); 1118 SDHCI_UNLOCK(slot); 1119 if (dumping) { 1120 while (slot->req != NULL) { 1121 sdhci_generic_intr(slot); 1122 DELAY(10); 1123 } 1124 } 1125 return (0); 1126 } 1127 1128 int 1129 sdhci_generic_get_ro(device_t brdev, device_t reqdev) 1130 { 1131 struct sdhci_slot *slot = device_get_ivars(reqdev); 1132 uint32_t val; 1133 1134 SDHCI_LOCK(slot); 1135 val = RD4(slot, SDHCI_PRESENT_STATE); 1136 SDHCI_UNLOCK(slot); 1137 return (!(val & SDHCI_WRITE_PROTECT)); 1138 } 1139 1140 int 1141 sdhci_generic_acquire_host(device_t brdev, device_t reqdev) 1142 { 1143 struct sdhci_slot *slot = device_get_ivars(reqdev); 1144 int err = 0; 1145 1146 SDHCI_LOCK(slot); 1147 while (slot->bus_busy) 1148 lksleep(slot, &slot->lock, 0, "sdhciah", 0); 1149 slot->bus_busy++; 1150 /* Activate led. */ 1151 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1152 SDHCI_UNLOCK(slot); 1153 return (err); 1154 } 1155 1156 int 1157 sdhci_generic_release_host(device_t brdev, device_t reqdev) 1158 { 1159 struct sdhci_slot *slot = device_get_ivars(reqdev); 1160 1161 SDHCI_LOCK(slot); 1162 /* Deactivate led. */ 1163 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 1164 slot->bus_busy--; 1165 SDHCI_UNLOCK(slot); 1166 wakeup(slot); 1167 return (0); 1168 } 1169 1170 static void 1171 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1172 { 1173 1174 if (!slot->curcmd) { 1175 slot_printf(slot, "Got command interrupt 0x%08x, but " 1176 "there is no active command.\n", intmask); 1177 sdhci_dumpregs(slot); 1178 return; 1179 } 1180 if (intmask & SDHCI_INT_TIMEOUT) 1181 slot->curcmd->error = MMC_ERR_TIMEOUT; 1182 else if (intmask & SDHCI_INT_CRC) 1183 slot->curcmd->error = MMC_ERR_BADCRC; 1184 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1185 slot->curcmd->error = MMC_ERR_FIFO; 1186 1187 sdhci_finish_command(slot); 1188 } 1189 1190 static void 1191 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1192 { 1193 1194 if (!slot->curcmd) { 1195 slot_printf(slot, "Got data interrupt 0x%08x, but " 1196 "there is no active command.\n", intmask); 1197 sdhci_dumpregs(slot); 1198 return; 1199 } 1200 if (slot->curcmd->data == NULL && 1201 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1202 slot_printf(slot, "Got data interrupt 0x%08x, but " 1203 "there is no active data operation.\n", 1204 intmask); 1205 sdhci_dumpregs(slot); 1206 return; 1207 } 1208 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1209 slot->curcmd->error = MMC_ERR_TIMEOUT; 1210 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1211 slot->curcmd->error = MMC_ERR_BADCRC; 1212 if (slot->curcmd->data == NULL && 1213 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1214 SDHCI_INT_DMA_END))) { 1215 slot_printf(slot, "Got data interrupt 0x%08x, but " 1216 "there is busy-only command.\n", intmask); 1217 sdhci_dumpregs(slot); 1218 slot->curcmd->error = MMC_ERR_INVALID; 1219 } 1220 if (slot->curcmd->error) { 1221 /* No need to continue after any error. */ 1222 goto done; 1223 } 1224 1225 /* Handle PIO interrupt. */ 1226 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { 1227 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) && 1228 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) { 1229 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, &intmask); 1230 slot->flags |= PLATFORM_DATA_STARTED; 1231 } else 1232 sdhci_transfer_pio(slot); 1233 } 1234 /* Handle DMA border. */ 1235 if (intmask & SDHCI_INT_DMA_END) { 1236 struct mmc_data *data = slot->curcmd->data; 1237 size_t left; 1238 1239 /* Unload DMA buffer... */ 1240 left = data->len - slot->offset; 1241 if (data->flags & MMC_DATA_READ) { 1242 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1243 BUS_DMASYNC_POSTREAD); 1244 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1245 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1246 } else { 1247 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1248 BUS_DMASYNC_POSTWRITE); 1249 } 1250 /* ... and reload it again. */ 1251 slot->offset += DMA_BLOCK_SIZE; 1252 left = data->len - slot->offset; 1253 if (data->flags & MMC_DATA_READ) { 1254 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1255 BUS_DMASYNC_PREREAD); 1256 } else { 1257 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 1258 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1259 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1260 BUS_DMASYNC_PREWRITE); 1261 } 1262 /* Interrupt aggregation: Mask border interrupt 1263 * for the last page. */ 1264 if (left == DMA_BLOCK_SIZE) { 1265 slot->intmask &= ~SDHCI_INT_DMA_END; 1266 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1267 } 1268 /* Restart DMA. */ 1269 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1270 } 1271 /* We have got all data. */ 1272 if (intmask & SDHCI_INT_DATA_END) { 1273 if (slot->flags & PLATFORM_DATA_STARTED) { 1274 slot->flags &= ~PLATFORM_DATA_STARTED; 1275 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1276 } else { 1277 sdhci_finish_data(slot); 1278 } 1279 } 1280 done: 1281 if (slot->curcmd != NULL && slot->curcmd->error != 0) { 1282 if (slot->flags & PLATFORM_DATA_STARTED) { 1283 slot->flags &= ~PLATFORM_DATA_STARTED; 1284 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1285 } else 1286 sdhci_finish_data(slot); 1287 return; 1288 } 1289 } 1290 1291 static void 1292 sdhci_acmd_irq(struct sdhci_slot *slot) 1293 { 1294 uint16_t err; 1295 1296 err = RD4(slot, SDHCI_ACMD12_ERR); 1297 if (!slot->curcmd) { 1298 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1299 "there is no active command.\n", err); 1300 sdhci_dumpregs(slot); 1301 return; 1302 } 1303 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1304 sdhci_reset(slot, SDHCI_RESET_CMD); 1305 } 1306 1307 void 1308 sdhci_generic_intr(struct sdhci_slot *slot) 1309 { 1310 uint32_t intmask; 1311 1312 SDHCI_LOCK(slot); 1313 /* Read slot interrupt status. */ 1314 intmask = RD4(slot, SDHCI_INT_STATUS); 1315 if (intmask == 0 || intmask == 0xffffffff) { 1316 SDHCI_UNLOCK(slot); 1317 return; 1318 } 1319 if (sdhci_debug > 2) 1320 slot_printf(slot, "Interrupt %#x\n", intmask); 1321 1322 /* Handle card presence interrupts. */ 1323 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1324 WR4(slot, SDHCI_INT_STATUS, intmask & 1325 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1326 1327 if (intmask & SDHCI_INT_CARD_REMOVE) { 1328 if (bootverbose || sdhci_debug) 1329 slot_printf(slot, "Card removed\n"); 1330 callout_stop(&slot->card_callout); 1331 taskqueue_enqueue(taskqueue_swi, 1332 &slot->card_task); 1333 } 1334 if (intmask & SDHCI_INT_CARD_INSERT) { 1335 if (bootverbose || sdhci_debug) 1336 slot_printf(slot, "Card inserted\n"); 1337 callout_reset(&slot->card_callout, hz / 2, 1338 sdhci_card_delay, slot); 1339 } 1340 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1341 } 1342 /* Handle command interrupts. */ 1343 if (intmask & SDHCI_INT_CMD_MASK) { 1344 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1345 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1346 } 1347 /* Handle data interrupts. */ 1348 if (intmask & SDHCI_INT_DATA_MASK) { 1349 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1350 /* Dont call data_irq in case of errored command */ 1351 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0) 1352 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1353 } 1354 /* Handle AutoCMD12 error interrupt. */ 1355 if (intmask & SDHCI_INT_ACMD12ERR) { 1356 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1357 sdhci_acmd_irq(slot); 1358 } 1359 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1360 intmask &= ~SDHCI_INT_ACMD12ERR; 1361 intmask &= ~SDHCI_INT_ERROR; 1362 /* Handle bus power interrupt. */ 1363 if (intmask & SDHCI_INT_BUS_POWER) { 1364 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1365 slot_printf(slot, 1366 "Card is consuming too much power!\n"); 1367 intmask &= ~SDHCI_INT_BUS_POWER; 1368 } 1369 /* The rest is unknown. */ 1370 if (intmask) { 1371 WR4(slot, SDHCI_INT_STATUS, intmask); 1372 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1373 intmask); 1374 sdhci_dumpregs(slot); 1375 } 1376 1377 SDHCI_UNLOCK(slot); 1378 } 1379 1380 int 1381 sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 1382 { 1383 struct sdhci_slot *slot = device_get_ivars(child); 1384 1385 switch (which) { 1386 default: 1387 return (EINVAL); 1388 case MMCBR_IVAR_BUS_MODE: 1389 *(int *)result = slot->host.ios.bus_mode; 1390 break; 1391 case MMCBR_IVAR_BUS_WIDTH: 1392 *(int *)result = slot->host.ios.bus_width; 1393 break; 1394 case MMCBR_IVAR_CHIP_SELECT: 1395 *(int *)result = slot->host.ios.chip_select; 1396 break; 1397 case MMCBR_IVAR_CLOCK: 1398 *(int *)result = slot->host.ios.clock; 1399 break; 1400 case MMCBR_IVAR_F_MIN: 1401 *(int *)result = slot->host.f_min; 1402 break; 1403 case MMCBR_IVAR_F_MAX: 1404 *(int *)result = slot->host.f_max; 1405 break; 1406 case MMCBR_IVAR_HOST_OCR: 1407 *(int *)result = slot->host.host_ocr; 1408 break; 1409 case MMCBR_IVAR_MODE: 1410 *(int *)result = slot->host.mode; 1411 break; 1412 case MMCBR_IVAR_OCR: 1413 *(int *)result = slot->host.ocr; 1414 break; 1415 case MMCBR_IVAR_POWER_MODE: 1416 *(int *)result = slot->host.ios.power_mode; 1417 break; 1418 case MMCBR_IVAR_VDD: 1419 *(int *)result = slot->host.ios.vdd; 1420 break; 1421 case MMCBR_IVAR_CAPS: 1422 *(int *)result = slot->host.caps; 1423 break; 1424 case MMCBR_IVAR_TIMING: 1425 *(int *)result = slot->host.ios.timing; 1426 break; 1427 case MMCBR_IVAR_MAX_DATA: 1428 *(int *)result = 65535; 1429 break; 1430 } 1431 return (0); 1432 } 1433 1434 int 1435 sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1436 { 1437 struct sdhci_slot *slot = device_get_ivars(child); 1438 1439 switch (which) { 1440 default: 1441 return (EINVAL); 1442 case MMCBR_IVAR_BUS_MODE: 1443 slot->host.ios.bus_mode = value; 1444 break; 1445 case MMCBR_IVAR_BUS_WIDTH: 1446 slot->host.ios.bus_width = value; 1447 break; 1448 case MMCBR_IVAR_CHIP_SELECT: 1449 slot->host.ios.chip_select = value; 1450 break; 1451 case MMCBR_IVAR_CLOCK: 1452 if (value > 0) { 1453 uint32_t max_clock; 1454 uint32_t clock; 1455 int i; 1456 1457 max_clock = slot->max_clk; 1458 clock = max_clock; 1459 1460 if (slot->version < SDHCI_SPEC_300) { 1461 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 1462 i <<= 1) { 1463 if (clock <= value) 1464 break; 1465 clock >>= 1; 1466 } 1467 } 1468 else { 1469 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 1470 i += 2) { 1471 if (clock <= value) 1472 break; 1473 clock = max_clock / (i + 2); 1474 } 1475 } 1476 1477 slot->host.ios.clock = clock; 1478 } else 1479 slot->host.ios.clock = 0; 1480 break; 1481 case MMCBR_IVAR_MODE: 1482 slot->host.mode = value; 1483 break; 1484 case MMCBR_IVAR_OCR: 1485 slot->host.ocr = value; 1486 break; 1487 case MMCBR_IVAR_POWER_MODE: 1488 slot->host.ios.power_mode = value; 1489 break; 1490 case MMCBR_IVAR_VDD: 1491 slot->host.ios.vdd = value; 1492 break; 1493 case MMCBR_IVAR_TIMING: 1494 slot->host.ios.timing = value; 1495 break; 1496 case MMCBR_IVAR_CAPS: 1497 case MMCBR_IVAR_HOST_OCR: 1498 case MMCBR_IVAR_F_MIN: 1499 case MMCBR_IVAR_F_MAX: 1500 case MMCBR_IVAR_MAX_DATA: 1501 return (EINVAL); 1502 } 1503 return (0); 1504 } 1505 1506 MODULE_VERSION(sdhci, 1); 1507