1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/param.h> 27 #include <sys/systm.h> 28 #include <sys/bus.h> 29 #include <sys/kernel.h> 30 #include <sys/lock.h> 31 #include <sys/module.h> 32 #include <sys/resource.h> 33 #include <sys/rman.h> 34 #include <sys/sysctl.h> 35 #include <sys/taskqueue.h> 36 #include <sys/lock.h> 37 38 #include <bus/pci/pcireg.h> 39 #include <bus/pci/pcivar.h> 40 41 #include <sys/bus.h> 42 #include <sys/resource.h> 43 44 #include <bus/mmc/bridge.h> 45 46 #include <dev/disk/sdhci/sdhci.h> 47 48 #include "mmcbr_if.h" 49 #include "sdhci_if.h" 50 51 /* 52 * PCI registers 53 */ 54 #define PCI_SDHCI_IFPIO 0x00 55 #define PCI_SDHCI_IFDMA 0x01 56 #define PCI_SDHCI_IFVENDOR 0x02 57 58 #define PCI_SLOT_INFO 0x40 /* 8 bits */ 59 #define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) 60 #define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) 61 62 /* 63 * RICOH specific PCI registers 64 */ 65 #define SDHC_PCI_MODE_KEY 0xf9 66 #define SDHC_PCI_MODE 0x150 67 #define SDHC_PCI_MODE_SD20 0x10 68 #define SDHC_PCI_BASE_FREQ_KEY 0xfc 69 #define SDHC_PCI_BASE_FREQ 0xe1 70 71 static const struct sdhci_device { 72 uint32_t model; 73 uint16_t subvendor; 74 const char *desc; 75 u_int quirks; 76 } sdhci_devices[] = { 77 { 0x08221180, 0xffff, "RICOH R5C822 SD", 78 SDHCI_QUIRK_FORCE_SDMA }, 79 { 0xe8221180, 0xffff, "RICOH R5CE822 SD", 80 SDHCI_QUIRK_FORCE_SDMA | 81 SDHCI_QUIRK_LOWER_FREQUENCY }, 82 { 0xe8231180, 0xffff, "RICOH R5CE823 SD", 83 SDHCI_QUIRK_LOWER_FREQUENCY }, 84 { 0x8034104c, 0xffff, "TI XX21/XX11 SD", 85 SDHCI_QUIRK_FORCE_SDMA }, 86 { 0x05501524, 0xffff, "ENE CB712 SD", 87 SDHCI_QUIRK_BROKEN_TIMINGS }, 88 { 0x05511524, 0xffff, "ENE CB712 SD 2", 89 SDHCI_QUIRK_BROKEN_TIMINGS }, 90 { 0x07501524, 0xffff, "ENE CB714 SD", 91 SDHCI_QUIRK_RESET_ON_IOS | 92 SDHCI_QUIRK_BROKEN_TIMINGS }, 93 { 0x07511524, 0xffff, "ENE CB714 SD 2", 94 SDHCI_QUIRK_RESET_ON_IOS | 95 SDHCI_QUIRK_BROKEN_TIMINGS }, 96 { 0x410111ab, 0xffff, "Marvell CaFe SD", 97 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, 98 { 0x2381197B, 0xffff, "JMicron JMB38X SD", 99 SDHCI_QUIRK_32BIT_DMA_SIZE | 100 SDHCI_QUIRK_RESET_AFTER_REQUEST }, 101 { 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader", 102 SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC }, 103 { 0x0f148086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", 104 SDHCI_QUIRK_WHITELIST_ADMA2 | 105 SDHCI_QUIRK_WAIT_WHILE_BUSY | 106 SDHCI_QUIRK_MMC_DDR52 | 107 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 108 SDHCI_QUIRK_PRESET_VALUE_BROKEN}, 109 { 0x0f158086, 0xffff, "Intel Bay Trail SDXC Controller", 110 SDHCI_QUIRK_WHITELIST_ADMA2 | 111 SDHCI_QUIRK_WAIT_WHILE_BUSY | 112 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 113 { 0x0f508086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", 114 SDHCI_QUIRK_WHITELIST_ADMA2 | 115 SDHCI_QUIRK_WAIT_WHILE_BUSY | 116 SDHCI_QUIRK_MMC_DDR52 | 117 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 118 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 119 { 0x22948086, 0xffff, "Intel Braswell eMMC 4.5.1 Controller", 120 SDHCI_QUIRK_WHITELIST_ADMA2 | 121 SDHCI_QUIRK_WAIT_WHILE_BUSY | 122 SDHCI_QUIRK_MMC_DDR52 | 123 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 124 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 125 { 0x22968086, 0xffff, "Intel Braswell SDXC Controller", 126 SDHCI_QUIRK_WHITELIST_ADMA2 | 127 SDHCI_QUIRK_WAIT_WHILE_BUSY | 128 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 129 { 0x5aca8086, 0xffff, "Intel Apollo Lake SDXC Controller", 130 SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */ 131 SDHCI_QUIRK_WAIT_WHILE_BUSY | 132 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 133 { 0x5acc8086, 0xffff, "Intel Apollo Lake eMMC 5.0 Controller", 134 SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */ 135 SDHCI_QUIRK_WAIT_WHILE_BUSY | 136 SDHCI_QUIRK_MMC_DDR52 | 137 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 138 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 139 { 0, 0xffff, NULL, 140 0 } 141 }; 142 143 struct sdhci_pci_softc { 144 u_int quirks; /* Chip specific quirks */ 145 struct resource *irq_res; /* IRQ resource */ 146 void *intrhand; /* Interrupt handle */ 147 148 int num_slots; /* Number of slots on this controller */ 149 struct sdhci_slot slots[6]; 150 struct resource *mem_res[6]; /* Memory resource */ 151 uint8_t cfg_freq; /* Saved mode */ 152 uint8_t cfg_mode; /* Saved frequency */ 153 }; 154 155 static int sdhci_enable_msi = 1; 156 TUNABLE_INT("hw.sdhci_enable_msi", &sdhci_enable_msi); 157 158 static uint8_t 159 sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 160 { 161 struct sdhci_pci_softc *sc = device_get_softc(dev); 162 163 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 164 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 165 return bus_read_1(sc->mem_res[slot->num], off); 166 } 167 168 static void 169 sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot __unused, 170 bus_size_t off, uint8_t val) 171 { 172 struct sdhci_pci_softc *sc = device_get_softc(dev); 173 174 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 175 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 176 bus_write_1(sc->mem_res[slot->num], off, val); 177 } 178 179 static uint16_t 180 sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 181 { 182 struct sdhci_pci_softc *sc = device_get_softc(dev); 183 184 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 185 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 186 return bus_read_2(sc->mem_res[slot->num], off); 187 } 188 189 static void 190 sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot __unused, 191 bus_size_t off, uint16_t val) 192 { 193 struct sdhci_pci_softc *sc = device_get_softc(dev); 194 195 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 196 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 197 bus_write_2(sc->mem_res[slot->num], off, val); 198 } 199 200 static uint32_t 201 sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 202 { 203 struct sdhci_pci_softc *sc = device_get_softc(dev); 204 205 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 206 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 207 return bus_read_4(sc->mem_res[slot->num], off); 208 } 209 210 static void 211 sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot __unused, 212 bus_size_t off, uint32_t val) 213 { 214 struct sdhci_pci_softc *sc = device_get_softc(dev); 215 216 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 217 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 218 bus_write_4(sc->mem_res[slot->num], off, val); 219 } 220 221 static void 222 sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot __unused, 223 bus_size_t off, uint32_t *data, bus_size_t count) 224 { 225 struct sdhci_pci_softc *sc = device_get_softc(dev); 226 227 bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count); 228 } 229 230 static void 231 sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot __unused, 232 bus_size_t off, uint32_t *data, bus_size_t count) 233 { 234 struct sdhci_pci_softc *sc = device_get_softc(dev); 235 236 bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count); 237 } 238 239 static void sdhci_pci_intr(void *arg); 240 241 static void 242 sdhci_lower_frequency(device_t dev) 243 { 244 struct sdhci_pci_softc *sc = device_get_softc(dev); 245 246 /* 247 * Enable SD2.0 mode. 248 * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822. 249 */ 250 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 251 sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1); 252 pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); 253 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 254 255 /* 256 * Some SD/MMC cards don't work with the default base 257 * clock frequency of 200 MHz. Lower it to 50 MHz. 258 */ 259 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 260 sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1); 261 pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); 262 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 263 } 264 265 static void 266 sdhci_restore_frequency(device_t dev) 267 { 268 struct sdhci_pci_softc *sc = device_get_softc(dev); 269 270 /* Restore mode. */ 271 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 272 pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1); 273 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 274 275 /* Restore frequency. */ 276 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 277 pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1); 278 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 279 } 280 281 static int 282 sdhci_pci_probe(device_t dev) 283 { 284 uint32_t model; 285 uint16_t subvendor; 286 uint8_t class, subclass; 287 int i, result; 288 289 model = (uint32_t)pci_get_device(dev) << 16; 290 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 291 subvendor = pci_get_subvendor(dev); 292 class = pci_get_class(dev); 293 subclass = pci_get_subclass(dev); 294 295 result = ENXIO; 296 for (i = 0; sdhci_devices[i].model != 0; i++) { 297 if (sdhci_devices[i].model == model && 298 (sdhci_devices[i].subvendor == 0xffff || 299 sdhci_devices[i].subvendor == subvendor)) { 300 device_set_desc(dev, sdhci_devices[i].desc); 301 result = BUS_PROBE_DEFAULT; 302 break; 303 } 304 } 305 if (result == ENXIO && class == PCIC_BASEPERIPH && 306 subclass == PCIS_BASEPERIPH_SDHC) { 307 device_set_desc(dev, "Generic SD HCI"); 308 result = BUS_PROBE_GENERIC; 309 } 310 311 return (result); 312 } 313 314 static int 315 sdhci_pci_attach(device_t dev) 316 { 317 struct sdhci_pci_softc *sc = device_get_softc(dev); 318 uint32_t model; 319 uint16_t subvendor; 320 int bar, err, rid, slots, i; 321 #if defined(__DragonFly__) 322 int irq_flags; 323 #else 324 int count; 325 #endif 326 327 model = (uint32_t)pci_get_device(dev) << 16; 328 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 329 subvendor = pci_get_subvendor(dev); 330 /* Apply chip specific quirks. */ 331 for (i = 0; sdhci_devices[i].model != 0; i++) { 332 if (sdhci_devices[i].model == model && 333 (sdhci_devices[i].subvendor == 0xffff || 334 sdhci_devices[i].subvendor == subvendor)) { 335 sc->quirks = sdhci_devices[i].quirks; 336 break; 337 } 338 } 339 sc->quirks &= ~sdhci_quirk_clear; 340 sc->quirks |= sdhci_quirk_set; 341 /* Some controllers need to be bumped into the right mode. */ 342 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 343 sdhci_lower_frequency(dev); 344 /* Read slots info from PCI registers. */ 345 slots = pci_read_config(dev, PCI_SLOT_INFO, 1); 346 bar = PCI_SLOT_INFO_FIRST_BAR(slots); 347 slots = PCI_SLOT_INFO_SLOTS(slots); 348 if (slots > 6 || bar > 5) { 349 device_printf(dev, "Incorrect slots information (%d, %d).\n", 350 slots, bar); 351 return (EINVAL); 352 } 353 /* Allocate IRQ. */ 354 rid = 0; 355 #if defined(__DragonFly__) 356 pci_alloc_1intr(dev, sdhci_enable_msi, &rid, &irq_flags); 357 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, irq_flags); 358 #else 359 i = 1; 360 if (sdhci_enable_msi != 0) { 361 count = pci_msi_count(dev); 362 if (count >= 1) { 363 count = 1; 364 if (pci_alloc_msi(dev, &i, 1, count) == 0) { 365 if (bootverbose) 366 device_printf(dev, "MSI enabled\n"); 367 rid = 1; 368 } 369 } 370 } 371 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 372 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 373 #endif 374 if (sc->irq_res == NULL) { 375 device_printf(dev, "Can't allocate IRQ\n"); 376 pci_release_msi(dev); 377 return (ENOMEM); 378 } 379 /* Scan all slots. */ 380 for (i = 0; i < slots; i++) { 381 struct sdhci_slot *slot = &sc->slots[sc->num_slots]; 382 383 /* Allocate memory. */ 384 rid = PCIR_BAR(bar + i); 385 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 386 &rid, RF_ACTIVE); 387 if (sc->mem_res[i] == NULL) { 388 device_printf(dev, "Can't allocate memory for slot %d\n", i); 389 continue; 390 } 391 392 slot->quirks = sc->quirks; 393 394 if (sdhci_init_slot(dev, slot, i) != 0) { 395 memset(slot, 0, sizeof(*slot)); 396 continue; 397 } 398 399 sc->num_slots++; 400 } 401 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 402 /* Activate the interrupt */ 403 err = bus_setup_intr(dev, sc->irq_res, INTR_MPSAFE, 404 sdhci_pci_intr, sc, &sc->intrhand, NULL); 405 if (err) 406 device_printf(dev, "Can't setup IRQ\n"); 407 pci_enable_busmaster(dev); 408 /* Process cards detection. */ 409 for (i = 0; i < sc->num_slots; i++) { 410 struct sdhci_slot *slot = &sc->slots[i]; 411 412 sdhci_start_slot(slot); 413 } 414 415 return (0); 416 } 417 418 static int 419 sdhci_pci_detach(device_t dev) 420 { 421 struct sdhci_pci_softc *sc = device_get_softc(dev); 422 int i; 423 424 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 425 bus_release_resource(dev, SYS_RES_IRQ, 426 rman_get_rid(sc->irq_res), sc->irq_res); 427 pci_release_msi(dev); 428 429 for (i = 0; i < sc->num_slots; i++) { 430 struct sdhci_slot *slot = &sc->slots[i]; 431 432 sdhci_cleanup_slot(slot); 433 bus_release_resource(dev, SYS_RES_MEMORY, 434 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); 435 } 436 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 437 sdhci_restore_frequency(dev); 438 return (0); 439 } 440 441 static int 442 sdhci_pci_shutdown(device_t dev) 443 { 444 struct sdhci_pci_softc *sc = device_get_softc(dev); 445 446 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 447 sdhci_restore_frequency(dev); 448 return (0); 449 } 450 451 static int 452 sdhci_pci_suspend(device_t dev) 453 { 454 struct sdhci_pci_softc *sc = device_get_softc(dev); 455 int i, err; 456 457 err = bus_generic_suspend(dev); 458 if (err) 459 return (err); 460 for (i = 0; i < sc->num_slots; i++) 461 sdhci_generic_suspend(&sc->slots[i]); 462 return (0); 463 } 464 465 static int 466 sdhci_pci_resume(device_t dev) 467 { 468 struct sdhci_pci_softc *sc = device_get_softc(dev); 469 int i; 470 471 for (i = 0; i < sc->num_slots; i++) 472 sdhci_generic_resume(&sc->slots[i]); 473 return (bus_generic_resume(dev)); 474 } 475 476 static void 477 sdhci_pci_intr(void *arg) 478 { 479 struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg; 480 int i; 481 482 for (i = 0; i < sc->num_slots; i++) { 483 struct sdhci_slot *slot = &sc->slots[i]; 484 sdhci_generic_intr(slot); 485 } 486 } 487 488 static device_method_t sdhci_methods[] = { 489 /* device_if */ 490 DEVMETHOD(device_probe, sdhci_pci_probe), 491 DEVMETHOD(device_attach, sdhci_pci_attach), 492 DEVMETHOD(device_detach, sdhci_pci_detach), 493 DEVMETHOD(device_shutdown, sdhci_pci_shutdown), 494 DEVMETHOD(device_suspend, sdhci_pci_suspend), 495 DEVMETHOD(device_resume, sdhci_pci_resume), 496 497 /* Bus interface */ 498 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 499 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 500 501 /* mmcbr_if */ 502 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 503 DEVMETHOD(mmcbr_switch_vccq, sdhci_generic_switch_vccq), 504 DEVMETHOD(mmcbr_request, sdhci_generic_request), 505 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro), 506 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 507 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 508 509 /* SDHCI accessors */ 510 DEVMETHOD(sdhci_read_1, sdhci_pci_read_1), 511 DEVMETHOD(sdhci_read_2, sdhci_pci_read_2), 512 DEVMETHOD(sdhci_read_4, sdhci_pci_read_4), 513 DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4), 514 DEVMETHOD(sdhci_write_1, sdhci_pci_write_1), 515 DEVMETHOD(sdhci_write_2, sdhci_pci_write_2), 516 DEVMETHOD(sdhci_write_4, sdhci_pci_write_4), 517 DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4), 518 DEVMETHOD(sdhci_set_uhs_timing, sdhci_generic_set_uhs_timing), 519 520 DEVMETHOD_END 521 }; 522 523 static driver_t sdhci_pci_driver = { 524 "sdhci_pci", 525 sdhci_methods, 526 sizeof(struct sdhci_pci_softc), 527 }; 528 static devclass_t sdhci_pci_devclass; 529 530 DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL, 531 NULL); 532 MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1); 533