1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/param.h> 27 #include <sys/systm.h> 28 #include <sys/bus.h> 29 #include <sys/conf.h> 30 #include <sys/kernel.h> 31 #include <sys/lock.h> 32 #include <sys/module.h> 33 #include <sys/mutex.h> 34 #include <sys/resource.h> 35 #include <sys/rman.h> 36 #include <sys/sysctl.h> 37 #include <sys/taskqueue.h> 38 #include <sys/lock.h> 39 40 #include <bus/pci/pcireg.h> 41 #include <bus/pci/pcivar.h> 42 43 #include <sys/bus.h> 44 #include <sys/resource.h> 45 #include <machine/stdarg.h> 46 47 #include <bus/mmc/bridge.h> 48 #include <bus/mmc/mmcreg.h> 49 #include <bus/mmc/mmcbrvar.h> 50 51 #include "sdhci.h" 52 #include "mmcbr_if.h" 53 #include "sdhci_if.h" 54 55 /* 56 * PCI registers 57 */ 58 59 #define PCI_SDHCI_IFPIO 0x00 60 #define PCI_SDHCI_IFDMA 0x01 61 #define PCI_SDHCI_IFVENDOR 0x02 62 63 #define PCI_SLOT_INFO 0x40 /* 8 bits */ 64 #define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) 65 #define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) 66 67 /* 68 * RICOH specific PCI registers 69 */ 70 #define SDHC_PCI_MODE_KEY 0xf9 71 #define SDHC_PCI_MODE 0x150 72 #define SDHC_PCI_MODE_SD20 0x10 73 #define SDHC_PCI_BASE_FREQ_KEY 0xfc 74 #define SDHC_PCI_BASE_FREQ 0xe1 75 76 static const struct sdhci_device { 77 uint32_t model; 78 uint16_t subvendor; 79 const char *desc; 80 u_int quirks; 81 } sdhci_devices[] = { 82 { 0x08221180, 0xffff, "RICOH R5C822 SD", 83 SDHCI_QUIRK_FORCE_DMA }, 84 { 0xe8221180, 0xffff, "RICOH SD", 85 SDHCI_QUIRK_FORCE_DMA }, 86 { 0xe8231180, 0xffff, "RICOH R5CE823 SD", 87 SDHCI_QUIRK_LOWER_FREQUENCY }, 88 { 0x8034104c, 0xffff, "TI XX21/XX11 SD", 89 SDHCI_QUIRK_FORCE_DMA }, 90 { 0x05501524, 0xffff, "ENE CB712 SD", 91 SDHCI_QUIRK_BROKEN_TIMINGS }, 92 { 0x05511524, 0xffff, "ENE CB712 SD 2", 93 SDHCI_QUIRK_BROKEN_TIMINGS }, 94 { 0x07501524, 0xffff, "ENE CB714 SD", 95 SDHCI_QUIRK_RESET_ON_IOS | 96 SDHCI_QUIRK_BROKEN_TIMINGS }, 97 { 0x07511524, 0xffff, "ENE CB714 SD 2", 98 SDHCI_QUIRK_RESET_ON_IOS | 99 SDHCI_QUIRK_BROKEN_TIMINGS }, 100 { 0x410111ab, 0xffff, "Marvell CaFe SD", 101 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, 102 { 0x2381197B, 0xffff, "JMicron JMB38X SD", 103 SDHCI_QUIRK_32BIT_DMA_SIZE | 104 SDHCI_QUIRK_RESET_AFTER_REQUEST }, 105 { 0, 0xffff, NULL, 106 0 } 107 }; 108 109 struct sdhci_pci_softc { 110 device_t dev; /* Controller device */ 111 u_int quirks; /* Chip specific quirks */ 112 struct resource *irq_res; /* IRQ resource */ 113 void *intrhand; /* Interrupt handle */ 114 115 int num_slots; /* Number of slots on this controller */ 116 struct sdhci_slot slots[6]; 117 struct resource *mem_res[6]; /* Memory resource */ 118 }; 119 120 static int sdhci_enable_msi = 1; 121 TUNABLE_INT("hw.sdhci_enable_msi", &sdhci_enable_msi); 122 123 static uint8_t 124 sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 125 { 126 struct sdhci_pci_softc *sc = device_get_softc(dev); 127 128 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 129 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 130 return bus_read_1(sc->mem_res[slot->num], off); 131 } 132 133 static void 134 sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 135 { 136 struct sdhci_pci_softc *sc = device_get_softc(dev); 137 138 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 139 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 140 bus_write_1(sc->mem_res[slot->num], off, val); 141 } 142 143 static uint16_t 144 sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 145 { 146 struct sdhci_pci_softc *sc = device_get_softc(dev); 147 148 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 149 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 150 return bus_read_2(sc->mem_res[slot->num], off); 151 } 152 153 static void 154 sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 155 { 156 struct sdhci_pci_softc *sc = device_get_softc(dev); 157 158 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 159 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 160 bus_write_2(sc->mem_res[slot->num], off, val); 161 } 162 163 static uint32_t 164 sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 165 { 166 struct sdhci_pci_softc *sc = device_get_softc(dev); 167 168 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 169 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 170 return bus_read_4(sc->mem_res[slot->num], off); 171 } 172 173 static void 174 sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 175 { 176 struct sdhci_pci_softc *sc = device_get_softc(dev); 177 178 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 179 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 180 bus_write_4(sc->mem_res[slot->num], off, val); 181 } 182 183 static void 184 sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot, 185 bus_size_t off, uint32_t *data, bus_size_t count) 186 { 187 struct sdhci_pci_softc *sc = device_get_softc(dev); 188 189 bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count); 190 } 191 192 static void 193 sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot, 194 bus_size_t off, uint32_t *data, bus_size_t count) 195 { 196 struct sdhci_pci_softc *sc = device_get_softc(dev); 197 198 bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count); 199 } 200 201 static void sdhci_pci_intr(void *arg); 202 203 static void 204 sdhci_lower_frequency(device_t dev) 205 { 206 207 /* Enable SD2.0 mode. */ 208 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 209 pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); 210 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 211 212 /* 213 * Some SD/MMC cards don't work with the default base 214 * clock frequency of 200MHz. Lower it to 50Hz. 215 */ 216 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 217 pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); 218 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 219 } 220 221 static int 222 sdhci_pci_probe(device_t dev) 223 { 224 uint32_t model; 225 uint16_t subvendor; 226 uint8_t class, subclass; 227 int i, result; 228 229 model = (uint32_t)pci_get_device(dev) << 16; 230 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 231 subvendor = pci_get_subvendor(dev); 232 class = pci_get_class(dev); 233 subclass = pci_get_subclass(dev); 234 235 result = ENXIO; 236 for (i = 0; sdhci_devices[i].model != 0; i++) { 237 if (sdhci_devices[i].model == model && 238 (sdhci_devices[i].subvendor == 0xffff || 239 sdhci_devices[i].subvendor == subvendor)) { 240 device_set_desc(dev, sdhci_devices[i].desc); 241 result = BUS_PROBE_DEFAULT; 242 break; 243 } 244 } 245 if (result == ENXIO && class == PCIC_BASEPERIPH && 246 subclass == PCIS_BASEPERIPH_SDHC) { 247 device_set_desc(dev, "Generic SD HCI"); 248 result = BUS_PROBE_GENERIC; 249 } 250 251 return (result); 252 } 253 254 static int 255 sdhci_pci_attach(device_t dev) 256 { 257 struct sdhci_pci_softc *sc = device_get_softc(dev); 258 uint32_t model; 259 uint16_t subvendor; 260 uint8_t class, subclass, progif; 261 int bar, count, err, rid, slots, i; 262 263 sc->dev = dev; 264 model = (uint32_t)pci_get_device(dev) << 16; 265 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 266 subvendor = pci_get_subvendor(dev); 267 class = pci_get_class(dev); 268 subclass = pci_get_subclass(dev); 269 progif = pci_get_progif(dev); 270 /* Apply chip specific quirks. */ 271 for (i = 0; sdhci_devices[i].model != 0; i++) { 272 if (sdhci_devices[i].model == model && 273 (sdhci_devices[i].subvendor == 0xffff || 274 sdhci_devices[i].subvendor == subvendor)) { 275 sc->quirks = sdhci_devices[i].quirks; 276 break; 277 } 278 } 279 /* Some controllers need to be bumped into the right mode. */ 280 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 281 sdhci_lower_frequency(dev); 282 /* Read slots info from PCI registers. */ 283 slots = pci_read_config(dev, PCI_SLOT_INFO, 1); 284 bar = PCI_SLOT_INFO_FIRST_BAR(slots); 285 slots = PCI_SLOT_INFO_SLOTS(slots); 286 if (slots > 6 || bar > 5) { 287 device_printf(dev, "Incorrect slots information (%d, %d).\n", 288 slots, bar); 289 return (EINVAL); 290 } 291 /* Allocate IRQ. */ 292 i = 1; 293 rid = 0; 294 if (sdhci_enable_msi != 0) { 295 count = pci_msi_count(dev); 296 if (count >= 1) { 297 count = 1; 298 if (pci_alloc_msi(dev, &i, 1, count) == 0) { 299 if (bootverbose) 300 device_printf(dev, "MSI enabled\n"); 301 rid = 1; 302 } 303 } 304 } 305 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 306 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 307 if (sc->irq_res == NULL) { 308 device_printf(dev, "Can't allocate IRQ\n"); 309 pci_release_msi(dev); 310 return (ENOMEM); 311 } 312 /* Scan all slots. */ 313 for (i = 0; i < slots; i++) { 314 struct sdhci_slot *slot = &sc->slots[sc->num_slots]; 315 316 /* Allocate memory. */ 317 rid = PCIR_BAR(bar + i); 318 sc->mem_res[i] = bus_alloc_resource(dev, SYS_RES_MEMORY, 319 &rid, 0ul, ~0ul, 0x100, RF_ACTIVE); 320 if (sc->mem_res[i] == NULL) { 321 device_printf(dev, "Can't allocate memory for slot %d\n", i); 322 continue; 323 } 324 325 if (sdhci_init_slot(dev, slot, i) != 0) 326 continue; 327 328 sc->num_slots++; 329 } 330 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 331 /* Activate the interrupt */ 332 err = bus_setup_intr(dev, sc->irq_res, INTR_MPSAFE, 333 sdhci_pci_intr, sc, &sc->intrhand, NULL); 334 if (err) 335 device_printf(dev, "Can't setup IRQ\n"); 336 pci_enable_busmaster(dev); 337 /* Process cards detection. */ 338 for (i = 0; i < sc->num_slots; i++) { 339 struct sdhci_slot *slot = &sc->slots[i]; 340 341 sdhci_start_slot(slot); 342 } 343 344 return (0); 345 } 346 347 static int 348 sdhci_pci_detach(device_t dev) 349 { 350 struct sdhci_pci_softc *sc = device_get_softc(dev); 351 int i; 352 353 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 354 bus_release_resource(dev, SYS_RES_IRQ, 355 rman_get_rid(sc->irq_res), sc->irq_res); 356 pci_release_msi(dev); 357 358 for (i = 0; i < sc->num_slots; i++) { 359 struct sdhci_slot *slot = &sc->slots[i]; 360 361 sdhci_cleanup_slot(slot); 362 bus_release_resource(dev, SYS_RES_MEMORY, 363 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); 364 } 365 return (0); 366 } 367 368 static int 369 sdhci_pci_suspend(device_t dev) 370 { 371 struct sdhci_pci_softc *sc = device_get_softc(dev); 372 int i, err; 373 374 err = bus_generic_suspend(dev); 375 if (err) 376 return (err); 377 for (i = 0; i < sc->num_slots; i++) 378 sdhci_generic_suspend(&sc->slots[i]); 379 return (0); 380 } 381 382 static int 383 sdhci_pci_resume(device_t dev) 384 { 385 struct sdhci_pci_softc *sc = device_get_softc(dev); 386 int i; 387 388 for (i = 0; i < sc->num_slots; i++) 389 sdhci_generic_resume(&sc->slots[i]); 390 return (bus_generic_resume(dev)); 391 } 392 393 static void 394 sdhci_pci_intr(void *arg) 395 { 396 struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg; 397 int i; 398 399 for (i = 0; i < sc->num_slots; i++) { 400 struct sdhci_slot *slot = &sc->slots[i]; 401 sdhci_generic_intr(slot); 402 } 403 } 404 405 static device_method_t sdhci_methods[] = { 406 /* device_if */ 407 DEVMETHOD(device_probe, sdhci_pci_probe), 408 DEVMETHOD(device_attach, sdhci_pci_attach), 409 DEVMETHOD(device_detach, sdhci_pci_detach), 410 DEVMETHOD(device_suspend, sdhci_pci_suspend), 411 DEVMETHOD(device_resume, sdhci_pci_resume), 412 413 /* Bus interface */ 414 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 415 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 416 417 /* mmcbr_if */ 418 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 419 DEVMETHOD(mmcbr_request, sdhci_generic_request), 420 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro), 421 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 422 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 423 424 /* SDHCI registers accessors */ 425 DEVMETHOD(sdhci_read_1, sdhci_pci_read_1), 426 DEVMETHOD(sdhci_read_2, sdhci_pci_read_2), 427 DEVMETHOD(sdhci_read_4, sdhci_pci_read_4), 428 DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4), 429 DEVMETHOD(sdhci_write_1, sdhci_pci_write_1), 430 DEVMETHOD(sdhci_write_2, sdhci_pci_write_2), 431 DEVMETHOD(sdhci_write_4, sdhci_pci_write_4), 432 DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4), 433 434 DEVMETHOD_END 435 }; 436 437 static driver_t sdhci_pci_driver = { 438 "sdhci_pci", 439 sdhci_methods, 440 sizeof(struct sdhci_pci_softc), 441 }; 442 static devclass_t sdhci_pci_devclass; 443 444 DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL, 445 NULL); 446 MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1); 447