1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/param.h> 27 #include <sys/systm.h> 28 #include <sys/bus.h> 29 #include <sys/kernel.h> 30 #include <sys/lock.h> 31 #include <sys/module.h> 32 #include <sys/resource.h> 33 #include <sys/rman.h> 34 #include <sys/sysctl.h> 35 #include <sys/taskqueue.h> 36 37 #include <bus/pci/pcireg.h> 38 #include <bus/pci/pcivar.h> 39 40 #include <bus/mmc/bridge.h> 41 42 #include <dev/disk/sdhci/sdhci.h> 43 44 #include "mmcbr_if.h" 45 #include "sdhci_if.h" 46 47 /* 48 * PCI registers 49 */ 50 #define PCI_SDHCI_IFPIO 0x00 51 #define PCI_SDHCI_IFDMA 0x01 52 #define PCI_SDHCI_IFVENDOR 0x02 53 54 #define PCI_SLOT_INFO 0x40 /* 8 bits */ 55 #define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) 56 #define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) 57 58 /* 59 * RICOH specific PCI registers 60 */ 61 #define SDHC_PCI_MODE_KEY 0xf9 62 #define SDHC_PCI_MODE 0x150 63 #define SDHC_PCI_MODE_SD20 0x10 64 #define SDHC_PCI_BASE_FREQ_KEY 0xfc 65 #define SDHC_PCI_BASE_FREQ 0xe1 66 67 static const struct sdhci_device { 68 uint32_t model; 69 uint16_t subvendor; 70 const char *desc; 71 u_int quirks; 72 } sdhci_devices[] = { 73 { 0x08221180, 0xffff, "RICOH R5C822 SD", 74 SDHCI_QUIRK_FORCE_SDMA }, 75 { 0xe8221180, 0xffff, "RICOH R5CE822 SD", 76 SDHCI_QUIRK_FORCE_SDMA | 77 SDHCI_QUIRK_LOWER_FREQUENCY }, 78 { 0xe8231180, 0xffff, "RICOH R5CE823 SD", 79 SDHCI_QUIRK_LOWER_FREQUENCY }, 80 { 0x8034104c, 0xffff, "TI XX21/XX11 SD", 81 SDHCI_QUIRK_FORCE_SDMA }, 82 { 0x05501524, 0xffff, "ENE CB712 SD", 83 SDHCI_QUIRK_BROKEN_TIMINGS }, 84 { 0x05511524, 0xffff, "ENE CB712 SD 2", 85 SDHCI_QUIRK_BROKEN_TIMINGS }, 86 { 0x07501524, 0xffff, "ENE CB714 SD", 87 SDHCI_QUIRK_RESET_ON_IOS | 88 SDHCI_QUIRK_BROKEN_TIMINGS }, 89 { 0x07511524, 0xffff, "ENE CB714 SD 2", 90 SDHCI_QUIRK_RESET_ON_IOS | 91 SDHCI_QUIRK_BROKEN_TIMINGS }, 92 { 0x410111ab, 0xffff, "Marvell CaFe SD", 93 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, 94 { 0x2381197B, 0xffff, "JMicron JMB38X SD", 95 SDHCI_QUIRK_32BIT_DMA_SIZE | 96 SDHCI_QUIRK_RESET_AFTER_REQUEST }, 97 { 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader", 98 SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC }, 99 { 0x0f148086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", 100 SDHCI_QUIRK_WHITELIST_ADMA2 | 101 SDHCI_QUIRK_WAIT_WHILE_BUSY | 102 SDHCI_QUIRK_MMC_DDR52 | 103 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 104 SDHCI_QUIRK_PRESET_VALUE_BROKEN}, 105 { 0x0f158086, 0xffff, "Intel Bay Trail SDXC Controller", 106 SDHCI_QUIRK_WHITELIST_ADMA2 | 107 SDHCI_QUIRK_WAIT_WHILE_BUSY | 108 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 109 { 0x0f508086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", 110 SDHCI_QUIRK_WHITELIST_ADMA2 | 111 SDHCI_QUIRK_WAIT_WHILE_BUSY | 112 SDHCI_QUIRK_MMC_DDR52 | 113 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 114 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 115 { 0x22948086, 0xffff, "Intel Braswell eMMC 4.5.1 Controller", 116 SDHCI_QUIRK_WHITELIST_ADMA2 | 117 SDHCI_QUIRK_WAIT_WHILE_BUSY | 118 SDHCI_QUIRK_MMC_DDR52 | 119 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 120 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 121 { 0x22968086, 0xffff, "Intel Braswell SDXC Controller", 122 SDHCI_QUIRK_WHITELIST_ADMA2 | 123 SDHCI_QUIRK_WAIT_WHILE_BUSY | 124 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 125 { 0x5aca8086, 0xffff, "Intel Apollo Lake SDXC Controller", 126 SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */ 127 SDHCI_QUIRK_WAIT_WHILE_BUSY | 128 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 129 { 0x5acc8086, 0xffff, "Intel Apollo Lake eMMC 5.0 Controller", 130 SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */ 131 SDHCI_QUIRK_WAIT_WHILE_BUSY | 132 SDHCI_QUIRK_MMC_DDR52 | 133 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 134 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 135 { 0, 0xffff, NULL, 136 0 } 137 }; 138 139 struct sdhci_pci_softc { 140 u_int quirks; /* Chip specific quirks */ 141 struct resource *irq_res; /* IRQ resource */ 142 void *intrhand; /* Interrupt handle */ 143 144 int num_slots; /* Number of slots on this controller */ 145 struct sdhci_slot slots[6]; 146 struct resource *mem_res[6]; /* Memory resource */ 147 uint8_t cfg_freq; /* Saved mode */ 148 uint8_t cfg_mode; /* Saved frequency */ 149 }; 150 151 static int sdhci_enable_msi = 1; 152 TUNABLE_INT("hw.sdhci_enable_msi", &sdhci_enable_msi); 153 154 static uint8_t 155 sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 156 { 157 struct sdhci_pci_softc *sc = device_get_softc(dev); 158 159 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 160 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 161 return bus_read_1(sc->mem_res[slot->num], off); 162 } 163 164 static void 165 sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot __unused, 166 bus_size_t off, uint8_t val) 167 { 168 struct sdhci_pci_softc *sc = device_get_softc(dev); 169 170 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 171 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 172 bus_write_1(sc->mem_res[slot->num], off, val); 173 } 174 175 static uint16_t 176 sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 177 { 178 struct sdhci_pci_softc *sc = device_get_softc(dev); 179 180 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 181 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 182 return bus_read_2(sc->mem_res[slot->num], off); 183 } 184 185 static void 186 sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot __unused, 187 bus_size_t off, uint16_t val) 188 { 189 struct sdhci_pci_softc *sc = device_get_softc(dev); 190 191 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 192 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 193 bus_write_2(sc->mem_res[slot->num], off, val); 194 } 195 196 static uint32_t 197 sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 198 { 199 struct sdhci_pci_softc *sc = device_get_softc(dev); 200 201 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 202 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 203 return bus_read_4(sc->mem_res[slot->num], off); 204 } 205 206 static void 207 sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot __unused, 208 bus_size_t off, uint32_t val) 209 { 210 struct sdhci_pci_softc *sc = device_get_softc(dev); 211 212 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 213 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 214 bus_write_4(sc->mem_res[slot->num], off, val); 215 } 216 217 static void 218 sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot __unused, 219 bus_size_t off, uint32_t *data, bus_size_t count) 220 { 221 struct sdhci_pci_softc *sc = device_get_softc(dev); 222 223 bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count); 224 } 225 226 static void 227 sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot __unused, 228 bus_size_t off, uint32_t *data, bus_size_t count) 229 { 230 struct sdhci_pci_softc *sc = device_get_softc(dev); 231 232 bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count); 233 } 234 235 static void sdhci_pci_intr(void *arg); 236 237 static void 238 sdhci_lower_frequency(device_t dev) 239 { 240 struct sdhci_pci_softc *sc = device_get_softc(dev); 241 242 /* 243 * Enable SD2.0 mode. 244 * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822. 245 */ 246 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 247 sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1); 248 pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); 249 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 250 251 /* 252 * Some SD/MMC cards don't work with the default base 253 * clock frequency of 200 MHz. Lower it to 50 MHz. 254 */ 255 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 256 sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1); 257 pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); 258 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 259 } 260 261 static void 262 sdhci_restore_frequency(device_t dev) 263 { 264 struct sdhci_pci_softc *sc = device_get_softc(dev); 265 266 /* Restore mode. */ 267 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 268 pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1); 269 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 270 271 /* Restore frequency. */ 272 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 273 pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1); 274 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 275 } 276 277 static int 278 sdhci_pci_probe(device_t dev) 279 { 280 uint32_t model; 281 uint16_t subvendor; 282 uint8_t class, subclass; 283 int i, result; 284 285 model = (uint32_t)pci_get_device(dev) << 16; 286 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 287 subvendor = pci_get_subvendor(dev); 288 class = pci_get_class(dev); 289 subclass = pci_get_subclass(dev); 290 291 result = ENXIO; 292 for (i = 0; sdhci_devices[i].model != 0; i++) { 293 if (sdhci_devices[i].model == model && 294 (sdhci_devices[i].subvendor == 0xffff || 295 sdhci_devices[i].subvendor == subvendor)) { 296 device_set_desc(dev, sdhci_devices[i].desc); 297 result = BUS_PROBE_DEFAULT; 298 break; 299 } 300 } 301 if (result == ENXIO && class == PCIC_BASEPERIPH && 302 subclass == PCIS_BASEPERIPH_SDHC) { 303 device_set_desc(dev, "Generic SD HCI"); 304 result = BUS_PROBE_GENERIC; 305 } 306 307 return (result); 308 } 309 310 static int 311 sdhci_pci_attach(device_t dev) 312 { 313 struct sdhci_pci_softc *sc = device_get_softc(dev); 314 uint32_t model; 315 uint16_t subvendor; 316 int bar, err, rid, slots, i; 317 #if defined(__DragonFly__) 318 int irq_flags; 319 #else 320 int count; 321 #endif 322 323 model = (uint32_t)pci_get_device(dev) << 16; 324 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 325 subvendor = pci_get_subvendor(dev); 326 /* Apply chip specific quirks. */ 327 for (i = 0; sdhci_devices[i].model != 0; i++) { 328 if (sdhci_devices[i].model == model && 329 (sdhci_devices[i].subvendor == 0xffff || 330 sdhci_devices[i].subvendor == subvendor)) { 331 sc->quirks = sdhci_devices[i].quirks; 332 break; 333 } 334 } 335 sc->quirks &= ~sdhci_quirk_clear; 336 sc->quirks |= sdhci_quirk_set; 337 /* Some controllers need to be bumped into the right mode. */ 338 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 339 sdhci_lower_frequency(dev); 340 /* Read slots info from PCI registers. */ 341 slots = pci_read_config(dev, PCI_SLOT_INFO, 1); 342 bar = PCI_SLOT_INFO_FIRST_BAR(slots); 343 slots = PCI_SLOT_INFO_SLOTS(slots); 344 if (slots > 6 || bar > 5) { 345 device_printf(dev, "Incorrect slots information (%d, %d).\n", 346 slots, bar); 347 return (EINVAL); 348 } 349 /* Allocate IRQ. */ 350 rid = 0; 351 #if defined(__DragonFly__) 352 pci_alloc_1intr(dev, sdhci_enable_msi, &rid, &irq_flags); 353 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, irq_flags); 354 #else 355 i = 1; 356 if (sdhci_enable_msi != 0) { 357 count = pci_msi_count(dev); 358 if (count >= 1) { 359 count = 1; 360 if (pci_alloc_msi(dev, &i, 1, count) == 0) { 361 if (bootverbose) 362 device_printf(dev, "MSI enabled\n"); 363 rid = 1; 364 } 365 } 366 } 367 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 368 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 369 #endif 370 if (sc->irq_res == NULL) { 371 device_printf(dev, "Can't allocate IRQ\n"); 372 pci_release_msi(dev); 373 return (ENOMEM); 374 } 375 /* Scan all slots. */ 376 for (i = 0; i < slots; i++) { 377 struct sdhci_slot *slot = &sc->slots[sc->num_slots]; 378 379 /* Allocate memory. */ 380 rid = PCIR_BAR(bar + i); 381 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 382 &rid, RF_ACTIVE); 383 if (sc->mem_res[i] == NULL) { 384 device_printf(dev, "Can't allocate memory for slot %d\n", i); 385 continue; 386 } 387 388 slot->quirks = sc->quirks; 389 390 if (sdhci_init_slot(dev, slot, i) != 0) { 391 memset(slot, 0, sizeof(*slot)); 392 continue; 393 } 394 395 sc->num_slots++; 396 } 397 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 398 /* Activate the interrupt */ 399 err = bus_setup_intr(dev, sc->irq_res, INTR_MPSAFE, 400 sdhci_pci_intr, sc, &sc->intrhand, NULL); 401 if (err) 402 device_printf(dev, "Can't setup IRQ\n"); 403 pci_enable_busmaster(dev); 404 /* Process cards detection. */ 405 for (i = 0; i < sc->num_slots; i++) { 406 struct sdhci_slot *slot = &sc->slots[i]; 407 408 sdhci_start_slot(slot); 409 } 410 411 return (0); 412 } 413 414 static int 415 sdhci_pci_detach(device_t dev) 416 { 417 struct sdhci_pci_softc *sc = device_get_softc(dev); 418 int i; 419 420 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 421 bus_release_resource(dev, SYS_RES_IRQ, 422 rman_get_rid(sc->irq_res), sc->irq_res); 423 pci_release_msi(dev); 424 425 for (i = 0; i < sc->num_slots; i++) { 426 struct sdhci_slot *slot = &sc->slots[i]; 427 428 sdhci_cleanup_slot(slot); 429 bus_release_resource(dev, SYS_RES_MEMORY, 430 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); 431 } 432 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 433 sdhci_restore_frequency(dev); 434 return (0); 435 } 436 437 static int 438 sdhci_pci_shutdown(device_t dev) 439 { 440 struct sdhci_pci_softc *sc = device_get_softc(dev); 441 442 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 443 sdhci_restore_frequency(dev); 444 return (0); 445 } 446 447 static int 448 sdhci_pci_suspend(device_t dev) 449 { 450 struct sdhci_pci_softc *sc = device_get_softc(dev); 451 int i, err; 452 453 err = bus_generic_suspend(dev); 454 if (err) 455 return (err); 456 for (i = 0; i < sc->num_slots; i++) 457 sdhci_generic_suspend(&sc->slots[i]); 458 return (0); 459 } 460 461 static int 462 sdhci_pci_resume(device_t dev) 463 { 464 struct sdhci_pci_softc *sc = device_get_softc(dev); 465 int i; 466 467 for (i = 0; i < sc->num_slots; i++) 468 sdhci_generic_resume(&sc->slots[i]); 469 return (bus_generic_resume(dev)); 470 } 471 472 static void 473 sdhci_pci_intr(void *arg) 474 { 475 struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg; 476 int i; 477 478 for (i = 0; i < sc->num_slots; i++) { 479 struct sdhci_slot *slot = &sc->slots[i]; 480 sdhci_generic_intr(slot); 481 } 482 } 483 484 static device_method_t sdhci_methods[] = { 485 /* device_if */ 486 DEVMETHOD(device_probe, sdhci_pci_probe), 487 DEVMETHOD(device_attach, sdhci_pci_attach), 488 DEVMETHOD(device_detach, sdhci_pci_detach), 489 DEVMETHOD(device_shutdown, sdhci_pci_shutdown), 490 DEVMETHOD(device_suspend, sdhci_pci_suspend), 491 DEVMETHOD(device_resume, sdhci_pci_resume), 492 493 /* Bus interface */ 494 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 495 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 496 497 /* mmcbr_if */ 498 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 499 DEVMETHOD(mmcbr_switch_vccq, sdhci_generic_switch_vccq), 500 DEVMETHOD(mmcbr_request, sdhci_generic_request), 501 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro), 502 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 503 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 504 505 /* SDHCI accessors */ 506 DEVMETHOD(sdhci_read_1, sdhci_pci_read_1), 507 DEVMETHOD(sdhci_read_2, sdhci_pci_read_2), 508 DEVMETHOD(sdhci_read_4, sdhci_pci_read_4), 509 DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4), 510 DEVMETHOD(sdhci_write_1, sdhci_pci_write_1), 511 DEVMETHOD(sdhci_write_2, sdhci_pci_write_2), 512 DEVMETHOD(sdhci_write_4, sdhci_pci_write_4), 513 DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4), 514 DEVMETHOD(sdhci_set_uhs_timing, sdhci_generic_set_uhs_timing), 515 516 DEVMETHOD_END 517 }; 518 519 static driver_t sdhci_pci_driver = { 520 "sdhci_pci", 521 sdhci_methods, 522 sizeof(struct sdhci_pci_softc), 523 }; 524 static devclass_t sdhci_pci_devclass; 525 526 DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL, 527 NULL); 528 MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1); 529