1 /* 2 * O.S : FreeBSD CAM 3 * FILE NAME : trm.c 4 * BY : C.L. Huang (ching@tekram.com.tw) 5 * Erich Chen (erich@tekram.com.tw) 6 * Description: Device Driver for Tekram DC395U/UW/F ,DC315/U 7 * PCI SCSI Bus Master Host Adapter 8 * (SCSI chip set used Tekram ASIC TRM-S1040) 9 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. 10 */ 11 12 /* 13 * HISTORY: 14 * 15 * REV# DATE NAME DESCRIPTION 16 * 1.05 05/01/1999 ERICH CHEN First released for 3.x.x (CAM) 17 * 1.06 07/29/1999 ERICH CHEN Modify for NEW PCI 18 * 1.07 12/12/1999 ERICH CHEN Modify for 3.3.x ,DCB no free 19 * 1.08 06/12/2000 ERICH CHEN Modify for 4.x.x 20 */ 21 22 /* 23 * 24 * 25 * Redistribution and use in source and binary forms, with or without 26 * modification, are permitted provided that the following conditions 27 * are met: 28 * 1. Redistributions of source code must retain the above copyright 29 * notice, this list of conditions and the following disclaimer. 30 * 2. Redistributions in binary form must reproduce the above copyright 31 * notice, this list of conditions and the following disclaimer in the 32 * documentation and/or other materials provided with the distribution. 33 * 3. The name of the author may not be used to endorse or promote products 34 * derived from this software without specific prior written permission. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 37 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 38 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 39 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 40 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 41 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 42 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 43 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 44 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 45 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 46 * 47 * $FreeBSD: src/sys/dev/trm/trm.c,v 1.2.2.2 2002/12/19 20:34:45 cognet Exp $ 48 * $DragonFly: src/sys/dev/disk/trm/trm.c,v 1.11 2006/08/03 16:40:47 swildner Exp $ 49 */ 50 51 /* 52 * Imported into FreeBSD source repository, and updated to compile under 53 * FreeBSD-3.0-DEVELOPMENT, by Stefan Esser <se@FreeBSD.Org>, 1996-12-17 54 */ 55 56 /* 57 * Updated to compile under FreeBSD 5.0-CURRENT by Olivier Houchard 58 * <doginou@ci0.org>, 2002-03-04 59 */ 60 61 #include <sys/param.h> 62 63 #include <sys/systm.h> 64 #include <sys/malloc.h> 65 #include <sys/queue.h> 66 #if defined(__FreeBSD__) && __FreeBSD_version >= 500000 67 #include <sys/bio.h> 68 #endif 69 #include <sys/buf.h> 70 #include <sys/bus.h> 71 #include <sys/kernel.h> 72 #include <sys/thread2.h> 73 74 #include <vm/vm.h> 75 #include <vm/pmap.h> 76 77 #include <bus/pci/pcivar.h> 78 #include <bus/pci/pcireg.h> 79 #include <machine/resource.h> 80 #include <machine/bus_pio.h> 81 #include <machine/bus.h> 82 #include <machine/clock.h> 83 #include <sys/rman.h> 84 85 #include <bus/cam/cam.h> 86 #include <bus/cam/cam_ccb.h> 87 #include <bus/cam/cam_sim.h> 88 #include <bus/cam/cam_xpt_sim.h> 89 #include <bus/cam/cam_debug.h> 90 91 #include <bus/cam/scsi/scsi_all.h> 92 93 #include "trm.h" 94 95 #define trm_reg_read8(reg) bus_space_read_1(pACB->tag, pACB->bsh, reg) 96 #define trm_reg_read16(reg) bus_space_read_2(pACB->tag, pACB->bsh, reg) 97 #define trm_reg_read32(reg) bus_space_read_4(pACB->tag, pACB->bsh, reg) 98 #define trm_reg_write8(value,reg) bus_space_write_1(pACB->tag, pACB->bsh,\ 99 reg, value) 100 #define trm_reg_write16(value,reg) bus_space_write_2(pACB->tag, pACB->bsh,\ 101 reg, value) 102 #define trm_reg_write32(value,reg) bus_space_write_4(pACB->tag, pACB->bsh,\ 103 reg, value) 104 105 #define PCI_Vendor_ID_TEKRAM 0x1DE1 106 #define PCI_Device_ID_TRM_S1040 0x0391 107 #define PCI_DEVICEID_TRMS1040 0x03911DE1 108 109 #ifdef trm_DEBUG1 110 #define TRM_DPRINTF(fmt, arg...) printf("trm: " fmt, ##arg) 111 #else 112 #define TRM_DPRINTF(fmt, arg...) {} 113 #endif /* TRM_DEBUG */ 114 115 static void trm_check_eeprom(PNVRAMTYPE pEEpromBuf,PACB pACB); 116 static void TRM_read_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 117 static u_int8_t TRM_get_data(PACB pACB, u_int8_t bAddr); 118 static void TRM_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 119 static void TRM_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData); 120 static void TRM_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr); 121 static void TRM_wait_30us(PACB pACB); 122 123 static void trm_Interrupt(void *vpACB); 124 static void trm_DataOutPhase0(PACB pACB, PSRB pSRB, 125 u_int8_t * pscsi_status); 126 static void trm_DataInPhase0(PACB pACB, PSRB pSRB, 127 u_int8_t * pscsi_status); 128 static void trm_CommandPhase0(PACB pACB, PSRB pSRB, 129 u_int8_t * pscsi_status); 130 static void trm_StatusPhase0(PACB pACB, PSRB pSRB, 131 u_int8_t * pscsi_status); 132 static void trm_MsgOutPhase0(PACB pACB, PSRB pSRB, 133 u_int8_t * pscsi_status); 134 static void trm_MsgInPhase0(PACB pACB, PSRB pSRB, 135 u_int8_t * pscsi_status); 136 static void trm_DataOutPhase1(PACB pACB, PSRB pSRB, 137 u_int8_t * pscsi_status); 138 static void trm_DataInPhase1(PACB pACB, PSRB pSRB, 139 u_int8_t * pscsi_status); 140 static void trm_CommandPhase1(PACB pACB, PSRB pSRB, 141 u_int8_t * pscsi_status); 142 static void trm_StatusPhase1(PACB pACB, PSRB pSRB, 143 u_int8_t * pscsi_status); 144 static void trm_MsgOutPhase1(PACB pACB, PSRB pSRB, 145 u_int8_t * pscsi_status); 146 static void trm_MsgInPhase1(PACB pACB, PSRB pSRB, 147 u_int8_t * pscsi_status); 148 static void trm_Nop0(PACB pACB, PSRB pSRB, u_int8_t * pscsi_status); 149 static void trm_Nop1(PACB pACB, PSRB pSRB, u_int8_t * pscsi_status); 150 static void trm_SetXferRate(PACB pACB, PSRB pSRB,PDCB pDCB); 151 static void trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir); 152 static void trm_Disconnect(PACB pACB); 153 static void trm_Reselect(PACB pACB); 154 static void trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB); 155 static void trm_DoingSRB_Done(PACB pACB); 156 static void trm_ScsiRstDetect(PACB pACB); 157 static void trm_ResetSCSIBus(PACB pACB); 158 static void trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB); 159 static void trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB); 160 static void trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB); 161 static void trm_SendSRB(PACB pACB, PSRB pSRB); 162 static int trm_probe(device_t tag); 163 static int trm_attach(device_t tag); 164 static void trm_reset(PACB pACB); 165 166 static u_int16_t trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB); 167 168 static int trm_initAdapter(PACB pACB, u_int16_t unit, 169 device_t pci_config_id); 170 static void trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit, 171 u_int32_t i, u_int32_t j); 172 static void trm_initSRB(PSRB psrb); 173 static void trm_linkSRB(PACB pACB); 174 static void trm_initACB(PACB pACB, u_int16_t unit); 175 /* CAM SIM entry points */ 176 #define ccb_trmsrb_ptr spriv_ptr0 177 #define ccb_trmacb_ptr spriv_ptr1 178 static void trm_action(struct cam_sim *psim, union ccb *pccb); 179 static void trm_poll(struct cam_sim *psim); 180 181 182 static void * trm_SCSI_phase0[] = { 183 trm_DataOutPhase0, /* phase:0 */ 184 trm_DataInPhase0, /* phase:1 */ 185 trm_CommandPhase0, /* phase:2 */ 186 trm_StatusPhase0, /* phase:3 */ 187 trm_Nop0, /* phase:4 */ 188 trm_Nop1, /* phase:5 */ 189 trm_MsgOutPhase0, /* phase:6 */ 190 trm_MsgInPhase0, /* phase:7 */ 191 }; 192 193 /* 194 * 195 * stateV = (void *) trm_SCSI_phase1[phase] 196 * 197 */ 198 static void * trm_SCSI_phase1[] = { 199 trm_DataOutPhase1, /* phase:0 */ 200 trm_DataInPhase1, /* phase:1 */ 201 trm_CommandPhase1, /* phase:2 */ 202 trm_StatusPhase1, /* phase:3 */ 203 trm_Nop0, /* phase:4 */ 204 trm_Nop1, /* phase:5 */ 205 trm_MsgOutPhase1, /* phase:6 */ 206 trm_MsgInPhase1, /* phase:7 */ 207 }; 208 209 210 NVRAMTYPE trm_eepromBuf[MAX_ADAPTER_NUM]; 211 /* 212 *Fast20: 000 50ns, 20.0 Mbytes/s 213 * 001 75ns, 13.3 Mbytes/s 214 * 010 100ns, 10.0 Mbytes/s 215 * 011 125ns, 8.0 Mbytes/s 216 * 100 150ns, 6.6 Mbytes/s 217 * 101 175ns, 5.7 Mbytes/s 218 * 110 200ns, 5.0 Mbytes/s 219 * 111 250ns, 4.0 Mbytes/s 220 * 221 *Fast40: 000 25ns, 40.0 Mbytes/s 222 * 001 50ns, 20.0 Mbytes/s 223 * 010 75ns, 13.3 Mbytes/s 224 * 011 100ns, 10.0 Mbytes/s 225 * 100 125ns, 8.0 Mbytes/s 226 * 101 150ns, 6.6 Mbytes/s 227 * 110 175ns, 5.7 Mbytes/s 228 * 111 200ns, 5.0 Mbytes/s 229 */ 230 /* real period: */ 231 u_int8_t dc395x_trm_clock_period[] = { 232 12,/* 48 ns 20 MB/sec */ 233 18,/* 72 ns 13.3 MB/sec */ 234 25,/* 100 ns 10.0 MB/sec */ 235 31,/* 124 ns 8.0 MB/sec */ 236 37,/* 148 ns 6.6 MB/sec */ 237 43,/* 172 ns 5.7 MB/sec */ 238 50,/* 200 ns 5.0 MB/sec */ 239 62 /* 248 ns 4.0 MB/sec */ 240 }; 241 242 u_int8_t dc395x_trm_tinfo_sync_period[] = { 243 12,/* 20.0 MB/sec */ 244 18,/* 13.3 MB/sec */ 245 25,/* 10.0 MB/sec */ 246 31,/* 8.0 MB/sec */ 247 37,/* 6.6 MB/sec */ 248 43,/* 5.7 MB/sec */ 249 50,/* 5.0 MB/sec */ 250 62,/* 4.0 MB/sec */ 251 }; 252 253 static PSRB 254 trm_GetSRB(PACB pACB) 255 { 256 PSRB pSRB; 257 258 crit_enter(); 259 pSRB = pACB->pFreeSRB; 260 if (pSRB) { 261 pACB->pFreeSRB = pSRB->pNextSRB; 262 pSRB->pNextSRB = NULL; 263 } 264 crit_exit(); 265 return (pSRB); 266 } 267 268 static void 269 trm_RewaitSRB0(PDCB pDCB, PSRB pSRB) 270 { 271 PSRB psrb1; 272 273 crit_enter(); 274 if ((psrb1 = pDCB->pWaitingSRB)) { 275 pSRB->pNextSRB = psrb1; 276 pDCB->pWaitingSRB = pSRB; 277 } else { 278 pSRB->pNextSRB = NULL; 279 pDCB->pWaitingSRB = pSRB; 280 pDCB->pWaitLastSRB = pSRB; 281 } 282 crit_exit(); 283 } 284 285 static void 286 trm_RewaitSRB(PDCB pDCB, PSRB pSRB) 287 { 288 PSRB psrb1; 289 u_int8_t bval; 290 291 crit_enter(); 292 pDCB->GoingSRBCnt--; 293 psrb1 = pDCB->pGoingSRB; 294 if (pSRB == psrb1) 295 pDCB->pGoingSRB = psrb1->pNextSRB; 296 else { 297 while (pSRB != psrb1->pNextSRB) 298 psrb1 = psrb1->pNextSRB; 299 psrb1->pNextSRB = pSRB->pNextSRB; 300 if (pSRB == pDCB->pGoingLastSRB) 301 pDCB->pGoingLastSRB = psrb1; 302 } 303 if ((psrb1 = pDCB->pWaitingSRB)) { 304 pSRB->pNextSRB = psrb1; 305 pDCB->pWaitingSRB = pSRB; 306 } else { 307 pSRB->pNextSRB = NULL; 308 pDCB->pWaitingSRB = pSRB; 309 pDCB->pWaitLastSRB = pSRB; 310 } 311 bval = pSRB->TagNumber; 312 pDCB->TagMask &= (~(1 << bval)); /* Free TAG number */ 313 crit_exit(); 314 } 315 316 static void 317 trm_DoWaitingSRB(PACB pACB) 318 { 319 PDCB ptr, ptr1; 320 PSRB pSRB; 321 322 crit_enter(); 323 if (!(pACB->pActiveDCB) && 324 !(pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 325 ptr = pACB->pDCBRunRobin; 326 if (!ptr) { 327 ptr = pACB->pLinkDCB; 328 pACB->pDCBRunRobin = ptr; 329 } 330 ptr1 = ptr; 331 for (;ptr1 ;) { 332 pACB->pDCBRunRobin = ptr1->pNextDCB; 333 if (!(ptr1->MaxCommand > ptr1->GoingSRBCnt) 334 || !(pSRB = ptr1->pWaitingSRB)) { 335 if (pACB->pDCBRunRobin == ptr) 336 break; 337 ptr1 = ptr1->pNextDCB; 338 } else { 339 if (!trm_StartSCSI(pACB, ptr1, pSRB)) { 340 /* 341 * If trm_StartSCSI return 0 : 342 * current interrupt status is interrupt enable 343 * It's said that SCSI processor is unoccupied 344 */ 345 ptr1->GoingSRBCnt++; 346 if (ptr1->pWaitLastSRB == pSRB) { 347 ptr1->pWaitingSRB = NULL; 348 ptr1->pWaitLastSRB = NULL; 349 } else 350 ptr1->pWaitingSRB = pSRB->pNextSRB; 351 pSRB->pNextSRB = NULL; 352 if (ptr1->pGoingSRB) 353 ptr1->pGoingLastSRB->pNextSRB = pSRB; 354 else 355 ptr1->pGoingSRB = pSRB; 356 ptr1->pGoingLastSRB = pSRB; 357 } 358 break; 359 } 360 } 361 } 362 crit_exit(); 363 return; 364 } 365 366 static void 367 trm_SRBwaiting(PDCB pDCB, PSRB pSRB) 368 { 369 370 if (pDCB->pWaitingSRB) { 371 pDCB->pWaitLastSRB->pNextSRB = pSRB; 372 pDCB->pWaitLastSRB = pSRB; 373 pSRB->pNextSRB = NULL; 374 } else { 375 pDCB->pWaitingSRB = pSRB; 376 pDCB->pWaitLastSRB = pSRB; 377 } 378 } 379 380 static void 381 trm_ExecuteSRB(void *arg, bus_dma_segment_t *dm_segs, int nseg, int vp) 382 { 383 PACB pACB; 384 PSRB pSRB; 385 union ccb *ccb; 386 u_long totalxferlen=0; 387 388 pSRB = (PSRB)arg; 389 ccb = pSRB->pccb; 390 pACB = (PACB)ccb->ccb_h.ccb_trmacb_ptr; 391 TRM_DPRINTF("trm_ExecuteSRB..........\n"); 392 if (nseg != 0) { 393 PSEG psg; 394 bus_dma_segment_t *end_seg; 395 bus_dmasync_op_t op; 396 397 /* Copy the segments into our SG list */ 398 end_seg = dm_segs + nseg; 399 psg = (PSEG) &pSRB->SegmentX[0]; 400 pSRB->SRBSGListPointer= psg; 401 while (dm_segs < end_seg) { 402 psg->address = vp?(u_long)vtophys(dm_segs->ds_addr) 403 :(u_long)dm_segs->ds_addr; 404 psg->length = (u_long)dm_segs->ds_len; 405 totalxferlen += dm_segs->ds_len; 406 psg++; 407 dm_segs++; 408 } 409 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 410 op = BUS_DMASYNC_PREREAD; 411 } else { 412 op = BUS_DMASYNC_PREWRITE; 413 } 414 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 415 } 416 pSRB->RetryCnt = 0; 417 pSRB->SRBTotalXferLength=totalxferlen; 418 pSRB->SRBSGCount = nseg; 419 pSRB->SRBSGIndex = 0; 420 pSRB->AdaptStatus = 0; 421 pSRB->TargetStatus = 0; 422 pSRB->MsgCnt = 0; 423 pSRB->SRBStatus = 0; 424 pSRB->SRBFlag = 0; 425 pSRB->SRBState = 0; 426 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 427 428 crit_enter(); 429 if (ccb->ccb_h.status != CAM_REQ_INPROG) { 430 if (nseg != 0) 431 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 432 pSRB->pNextSRB = pACB->pFreeSRB; 433 pACB->pFreeSRB = pSRB; 434 xpt_done(ccb); 435 crit_exit(); 436 return; 437 } 438 ccb->ccb_h.status |= CAM_SIM_QUEUED; 439 #if 0 440 /* XXX Need a timeout handler */ 441 callout_reset(&ccb->ccb_h.timeout_ch, (ccb->ccb_h.timeout * hz) / 1000, 442 trmtimeout, srb); 443 #endif 444 trm_SendSRB(pACB, pSRB); 445 crit_exit(); 446 return; 447 } 448 449 static void 450 trm_SendSRB(PACB pACB, PSRB pSRB) 451 { 452 PDCB pDCB; 453 454 crit_enter(); 455 pDCB = pSRB->pSRBDCB; 456 if (!(pDCB->MaxCommand > pDCB->GoingSRBCnt) || (pACB->pActiveDCB) 457 || (pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 458 TRM_DPRINTF("pDCB->MaxCommand=%d \n",pDCB->MaxCommand); 459 TRM_DPRINTF("pDCB->GoingSRBCnt=%d \n",pDCB->GoingSRBCnt); 460 TRM_DPRINTF("pACB->pActiveDCB=%8x \n",(u_int)pACB->pActiveDCB); 461 TRM_DPRINTF("pACB->ACBFlag=%x \n",pACB->ACBFlag); 462 trm_SRBwaiting(pDCB, pSRB); 463 goto SND_EXIT; 464 } 465 466 if (pDCB->pWaitingSRB) { 467 trm_SRBwaiting(pDCB, pSRB); 468 pSRB = pDCB->pWaitingSRB; 469 pDCB->pWaitingSRB = pSRB->pNextSRB; 470 pSRB->pNextSRB = NULL; 471 } 472 473 if (!trm_StartSCSI(pACB, pDCB, pSRB)) { 474 /* 475 * If trm_StartSCSI return 0 : 476 * current interrupt status is interrupt enable 477 * It's said that SCSI processor is unoccupied 478 */ 479 pDCB->GoingSRBCnt++; /* stack waiting SRB*/ 480 if (pDCB->pGoingSRB) { 481 pDCB->pGoingLastSRB->pNextSRB = pSRB; 482 pDCB->pGoingLastSRB = pSRB; 483 } else { 484 pDCB->pGoingSRB = pSRB; 485 pDCB->pGoingLastSRB = pSRB; 486 } 487 } else { 488 /* 489 * If trm_StartSCSI return 1 : 490 * current interrupt status is interrupt disreenable 491 * It's said that SCSI processor has more one SRB need to do 492 */ 493 trm_RewaitSRB0(pDCB, pSRB); 494 } 495 SND_EXIT: 496 crit_exit(); 497 /* 498 * enable interrupt 499 */ 500 return; 501 } 502 503 504 static void 505 trm_action(struct cam_sim *psim, union ccb *pccb) 506 { 507 PACB pACB; 508 u_int target_id,target_lun; 509 510 CAM_DEBUG(pccb->ccb_h.path, CAM_DEBUG_TRACE, ("trm_action\n")); 511 512 pACB = (PACB) cam_sim_softc(psim); 513 target_id = pccb->ccb_h.target_id; 514 target_lun = pccb->ccb_h.target_lun; 515 516 switch (pccb->ccb_h.func_code) { 517 case XPT_NOOP: 518 TRM_DPRINTF(" XPT_NOOP \n"); 519 pccb->ccb_h.status = CAM_REQ_INVALID; 520 xpt_done(pccb); 521 break; 522 /* 523 * Execute the requested I/O operation 524 */ 525 case XPT_SCSI_IO: { 526 PDCB pDCB = NULL; 527 PSRB pSRB; 528 struct ccb_scsiio *pcsio; 529 530 pcsio = &pccb->csio; 531 TRM_DPRINTF(" XPT_SCSI_IO \n"); 532 TRM_DPRINTF("trm: target_id= %d target_lun= %d \n" 533 ,target_id, target_lun); 534 TRM_DPRINTF( 535 "pACB->scan_devices[target_id][target_lun]= %d \n" 536 ,pACB->scan_devices[target_id][target_lun]); 537 pDCB = pACB->pDCB[target_id][target_lun]; 538 /* 539 * Assign an SRB and connect it with this ccb. 540 */ 541 pSRB = trm_GetSRB(pACB); 542 if (!pSRB) { 543 /* Freeze SIMQ */ 544 pccb->ccb_h.status = CAM_RESRC_UNAVAIL; 545 xpt_done(pccb); 546 return; 547 } 548 pSRB->pSRBDCB = pDCB; 549 pccb->ccb_h.ccb_trmsrb_ptr = pSRB; 550 pccb->ccb_h.ccb_trmacb_ptr = pACB; 551 pSRB->pccb = pccb; 552 pSRB->ScsiCmdLen = pcsio->cdb_len; 553 /* 554 * move layer of CAM command block to layer of SCSI 555 * Request Block for SCSI processor command doing 556 */ 557 bcopy(pcsio->cdb_io.cdb_bytes,pSRB->CmdBlock 558 ,pcsio->cdb_len); 559 if ((pccb->ccb_h.flags & CAM_DIR_MASK) 560 != CAM_DIR_NONE) { 561 if ((pccb->ccb_h.flags & 562 CAM_SCATTER_VALID) == 0) { 563 if ((pccb->ccb_h.flags 564 & CAM_DATA_PHYS) == 0) { 565 int error; 566 567 crit_enter(); 568 error = bus_dmamap_load( 569 pACB->buffer_dmat, 570 pSRB->dmamap, 571 pcsio->data_ptr, 572 pcsio->dxfer_len, 573 trm_ExecuteSRB, 574 pSRB, 575 0); 576 if (error == EINPROGRESS) { 577 xpt_freeze_simq( 578 pACB->psim, 579 1); 580 pccb->ccb_h.status |= 581 CAM_RELEASE_SIMQ; 582 } 583 crit_exit(); 584 } else { 585 struct bus_dma_segment seg; 586 587 /* Pointer to physical buffer */ 588 seg.ds_addr = 589 (bus_addr_t)pcsio->data_ptr; 590 seg.ds_len = pcsio->dxfer_len; 591 trm_ExecuteSRB(pSRB, &seg, 1, 592 0); 593 } 594 } else { 595 /* CAM_SCATTER_VALID */ 596 struct bus_dma_segment *segs; 597 598 if ((pccb->ccb_h.flags & 599 CAM_SG_LIST_PHYS) == 0 || 600 (pccb->ccb_h.flags 601 & CAM_DATA_PHYS) != 0) { 602 pSRB->pNextSRB = pACB->pFreeSRB; 603 pACB->pFreeSRB = pSRB; 604 pccb->ccb_h.status = 605 CAM_PROVIDE_FAIL; 606 xpt_done(pccb); 607 return; 608 } 609 610 /* cam SG list is physical, 611 * cam data is virtual 612 */ 613 segs = (struct bus_dma_segment *) 614 pcsio->data_ptr; 615 trm_ExecuteSRB(pSRB, segs, 616 pcsio->sglist_cnt, 1); 617 } /* CAM_SCATTER_VALID */ 618 } else 619 trm_ExecuteSRB(pSRB, NULL, 0, 0); 620 } 621 break; 622 case XPT_GDEV_TYPE: 623 TRM_DPRINTF(" XPT_GDEV_TYPE \n"); 624 pccb->ccb_h.status = CAM_REQ_INVALID; 625 xpt_done(pccb); 626 break; 627 case XPT_GDEVLIST: 628 TRM_DPRINTF(" XPT_GDEVLIST \n"); 629 pccb->ccb_h.status = CAM_REQ_INVALID; 630 xpt_done(pccb); 631 break; 632 /* 633 * Path routing inquiry 634 * Path Inquiry CCB 635 */ 636 case XPT_PATH_INQ: { 637 struct ccb_pathinq *cpi = &pccb->cpi; 638 639 TRM_DPRINTF(" XPT_PATH_INQ \n"); 640 cpi->version_num = 1; 641 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE|PI_WIDE_16; 642 cpi->target_sprt = 0; 643 cpi->hba_misc = 0; 644 cpi->hba_eng_cnt = 0; 645 cpi->max_target = 15 ; 646 cpi->max_lun = pACB->max_lun; /* 7 or 0 */ 647 cpi->initiator_id = pACB->AdaptSCSIID; 648 cpi->bus_id = cam_sim_bus(psim); 649 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 650 strncpy(cpi->hba_vid, "Tekram_TRM", HBA_IDLEN); 651 strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 652 cpi->unit_number = cam_sim_unit(psim); 653 cpi->ccb_h.status = CAM_REQ_CMP; 654 xpt_done(pccb); 655 } 656 break; 657 /* 658 * Release a frozen SIM queue 659 * Release SIM Queue 660 */ 661 case XPT_REL_SIMQ: 662 TRM_DPRINTF(" XPT_REL_SIMQ \n"); 663 pccb->ccb_h.status = CAM_REQ_INVALID; 664 xpt_done(pccb); 665 break; 666 /* 667 * Set Asynchronous Callback Parameters 668 * Set Asynchronous Callback CCB 669 */ 670 case XPT_SASYNC_CB: 671 TRM_DPRINTF(" XPT_SASYNC_CB \n"); 672 pccb->ccb_h.status = CAM_REQ_INVALID; 673 xpt_done(pccb); 674 break; 675 /* 676 * Set device type information 677 * Set Device Type CCB 678 */ 679 case XPT_SDEV_TYPE: 680 TRM_DPRINTF(" XPT_SDEV_TYPE \n"); 681 pccb->ccb_h.status = CAM_REQ_INVALID; 682 xpt_done(pccb); 683 break; 684 /* 685 * (Re)Scan the SCSI Bus 686 * Rescan the given bus, or bus/target/lun 687 */ 688 case XPT_SCAN_BUS: 689 TRM_DPRINTF(" XPT_SCAN_BUS \n"); 690 pccb->ccb_h.status = CAM_REQ_INVALID; 691 xpt_done(pccb); 692 break; 693 /* 694 * Get EDT entries matching the given pattern 695 */ 696 case XPT_DEV_MATCH: 697 TRM_DPRINTF(" XPT_DEV_MATCH \n"); 698 pccb->ccb_h.status = CAM_REQ_INVALID; 699 xpt_done(pccb); 700 break; 701 /* 702 * Turn on debugging for a bus, target or lun 703 */ 704 case XPT_DEBUG: 705 TRM_DPRINTF(" XPT_DEBUG \n"); 706 pccb->ccb_h.status = CAM_REQ_INVALID; 707 xpt_done(pccb); 708 break; 709 /* 710 * XPT_ABORT = 0x10, Abort the specified CCB 711 * Abort XPT request CCB 712 */ 713 case XPT_ABORT: 714 TRM_DPRINTF(" XPT_ABORT \n"); 715 pccb->ccb_h.status = CAM_REQ_INVALID; 716 xpt_done(pccb); 717 break; 718 /* 719 * Reset the specified SCSI bus 720 * Reset SCSI Bus CCB 721 */ 722 case XPT_RESET_BUS: { 723 int i; 724 725 TRM_DPRINTF(" XPT_RESET_BUS \n"); 726 trm_reset(pACB); 727 pACB->ACBFlag=0; 728 for (i=0; i<500; i++) 729 DELAY(1000); 730 pccb->ccb_h.status = CAM_REQ_CMP; 731 xpt_done(pccb); 732 } 733 break; 734 /* 735 * Bus Device Reset the specified SCSI device 736 * Reset SCSI Device CCB 737 */ 738 case XPT_RESET_DEV: 739 /* 740 * Don't (yet?) support vendor 741 * specific commands. 742 */ 743 TRM_DPRINTF(" XPT_RESET_DEV \n"); 744 pccb->ccb_h.status = CAM_REQ_INVALID; 745 xpt_done(pccb); 746 break; 747 /* 748 * Terminate the I/O process 749 * Terminate I/O Process Request CCB 750 */ 751 case XPT_TERM_IO: 752 TRM_DPRINTF(" XPT_TERM_IO \n"); 753 pccb->ccb_h.status = CAM_REQ_INVALID; 754 xpt_done(pccb); 755 break; 756 /* 757 * Scan Logical Unit 758 */ 759 case XPT_SCAN_LUN: 760 TRM_DPRINTF(" XPT_SCAN_LUN \n"); 761 pccb->ccb_h.status = CAM_REQ_INVALID; 762 xpt_done(pccb); 763 break; 764 765 /* 766 * Get/Set transfer rate/width/disconnection/tag queueing 767 * settings 768 * (GET) default/user transfer settings for the target 769 */ 770 case XPT_GET_TRAN_SETTINGS: { 771 struct ccb_trans_settings *cts; 772 struct trm_transinfo *tinfo; 773 PDCB pDCB; 774 775 TRM_DPRINTF(" XPT_GET_TRAN_SETTINGS \n"); 776 cts = &pccb->cts; 777 pDCB = pACB->pDCB[target_id][target_lun]; 778 crit_enter(); 779 /* 780 * disable interrupt 781 */ 782 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) { 783 /* current transfer settings */ 784 if (pDCB->tinfo.disc_tag & TRM_CUR_DISCENB) 785 cts->flags = CCB_TRANS_DISC_ENB; 786 else 787 cts->flags = 0;/* no tag & disconnect */ 788 if (pDCB->tinfo.disc_tag & TRM_CUR_TAGENB) 789 cts->flags |= CCB_TRANS_TAG_ENB; 790 tinfo = &pDCB->tinfo.current; 791 TRM_DPRINTF("CURRENT: cts->flags= %2x \n", 792 cts->flags); 793 } else { 794 /* default(user) transfer settings */ 795 if (pDCB->tinfo.disc_tag & TRM_USR_DISCENB) 796 cts->flags = CCB_TRANS_DISC_ENB; 797 else 798 cts->flags = 0; 799 if (pDCB->tinfo.disc_tag & TRM_USR_TAGENB) 800 cts->flags |= CCB_TRANS_TAG_ENB; 801 tinfo = &pDCB->tinfo.user; 802 TRM_DPRINTF("USER: cts->flags= %2x \n", 803 cts->flags); 804 } 805 cts->sync_period = tinfo->period; 806 cts->sync_offset = tinfo->offset; 807 cts->bus_width = tinfo->width; 808 TRM_DPRINTF("pDCB->SyncPeriod: %d \n", 809 pDCB->SyncPeriod); 810 TRM_DPRINTF("period: %d \n", tinfo->period); 811 TRM_DPRINTF("offset: %d \n", tinfo->offset); 812 TRM_DPRINTF("width: %d \n", tinfo->width); 813 814 crit_exit(); 815 cts->valid = CCB_TRANS_SYNC_RATE_VALID | 816 CCB_TRANS_SYNC_OFFSET_VALID | 817 CCB_TRANS_BUS_WIDTH_VALID | 818 CCB_TRANS_DISC_VALID | 819 CCB_TRANS_TQ_VALID; 820 pccb->ccb_h.status = CAM_REQ_CMP; 821 xpt_done(pccb); 822 } 823 break; 824 /* 825 * Get/Set transfer rate/width/disconnection/tag queueing 826 * settings 827 * (Set) transfer rate/width negotiation settings 828 */ 829 case XPT_SET_TRAN_SETTINGS: { 830 struct ccb_trans_settings *cts; 831 u_int update_type; 832 PDCB pDCB; 833 834 TRM_DPRINTF(" XPT_SET_TRAN_SETTINGS \n"); 835 cts = &pccb->cts; 836 update_type = 0; 837 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) 838 update_type |= TRM_TRANS_GOAL; 839 if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) 840 update_type |= TRM_TRANS_USER; 841 crit_enter(); 842 pDCB = pACB->pDCB[target_id][target_lun]; 843 844 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) { 845 /*ccb disc enables */ 846 if (update_type & TRM_TRANS_GOAL) { 847 if ((cts->flags & CCB_TRANS_DISC_ENB) 848 != 0) 849 pDCB->tinfo.disc_tag 850 |= TRM_CUR_DISCENB; 851 else 852 pDCB->tinfo.disc_tag &= 853 ~TRM_CUR_DISCENB; 854 } 855 if (update_type & TRM_TRANS_USER) { 856 if ((cts->flags & CCB_TRANS_DISC_ENB) 857 != 0) 858 pDCB->tinfo.disc_tag 859 |= TRM_USR_DISCENB; 860 else 861 pDCB->tinfo.disc_tag &= 862 ~TRM_USR_DISCENB; 863 } 864 } 865 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) { 866 /* if ccb tag q active */ 867 if (update_type & TRM_TRANS_GOAL) { 868 if ((cts->flags & CCB_TRANS_TAG_ENB) 869 != 0) 870 pDCB->tinfo.disc_tag |= 871 TRM_CUR_TAGENB; 872 else 873 pDCB->tinfo.disc_tag &= 874 ~TRM_CUR_TAGENB; 875 } 876 if (update_type & TRM_TRANS_USER) { 877 if ((cts->flags & CCB_TRANS_TAG_ENB) 878 != 0) 879 pDCB->tinfo.disc_tag |= 880 TRM_USR_TAGENB; 881 else 882 pDCB->tinfo.disc_tag &= 883 ~TRM_USR_TAGENB; 884 } 885 } 886 /* Minimum sync period factor */ 887 888 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) { 889 /* if ccb sync active */ 890 /* TRM-S1040 MinSyncPeriod = 4 clocks/byte */ 891 if ((cts->sync_period != 0) && 892 (cts->sync_period < 125)) 893 cts->sync_period = 125; 894 /* 1/(125*4) minsync 2 MByte/sec */ 895 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) 896 != 0) { 897 if (cts->sync_offset == 0) 898 cts->sync_period = 0; 899 /* TRM-S1040 MaxSyncOffset = 15 bytes*/ 900 if (cts->sync_offset > 15) 901 cts->sync_offset = 15; 902 } 903 } 904 if ((update_type & TRM_TRANS_USER) != 0) { 905 pDCB->tinfo.user.period = cts->sync_period; 906 pDCB->tinfo.user.offset = cts->sync_offset; 907 pDCB->tinfo.user.width = cts->bus_width; 908 } 909 if ((update_type & TRM_TRANS_GOAL) != 0) { 910 pDCB->tinfo.goal.period = cts->sync_period; 911 pDCB->tinfo.goal.offset = cts->sync_offset; 912 pDCB->tinfo.goal.width = cts->bus_width; 913 } 914 crit_exit(); 915 pccb->ccb_h.status = CAM_REQ_CMP; 916 xpt_done(pccb); 917 break; 918 } 919 /* 920 * Calculate the geometry parameters for a device give 921 * the sector size and volume size. 922 */ 923 case XPT_CALC_GEOMETRY: { 924 struct ccb_calc_geometry *ccg; 925 u_int32_t size_mb; 926 u_int32_t secs_per_cylinder; 927 int extended; 928 929 TRM_DPRINTF(" XPT_CALC_GEOMETRY \n"); 930 ccg = &pccb->ccg; 931 size_mb = ccg->volume_size / 932 ((1024L * 1024L) / ccg->block_size); 933 extended = 1; 934 if (size_mb > 1024 && extended) { 935 ccg->heads = 255; 936 ccg->secs_per_track = 63; 937 } else { 938 ccg->heads = 64; 939 ccg->secs_per_track = 32; 940 } 941 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 942 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 943 pccb->ccb_h.status = CAM_REQ_CMP; 944 xpt_done(pccb); 945 } 946 break; 947 case XPT_ENG_INQ: 948 TRM_DPRINTF(" XPT_ENG_INQ \n"); 949 pccb->ccb_h.status = CAM_REQ_INVALID; 950 xpt_done(pccb); 951 break; 952 /* 953 * HBA execute engine request 954 * This structure must match SCSIIO size 955 */ 956 case XPT_ENG_EXEC: 957 TRM_DPRINTF(" XPT_ENG_EXEC \n"); 958 pccb->ccb_h.status = CAM_REQ_INVALID; 959 xpt_done(pccb); 960 break; 961 /* 962 * XPT_EN_LUN = 0x30, Enable LUN as a target 963 * Target mode structures. 964 */ 965 case XPT_EN_LUN: 966 /* 967 * Don't (yet?) support vendor 968 * specific commands. 969 */ 970 TRM_DPRINTF(" XPT_EN_LUN \n"); 971 pccb->ccb_h.status = CAM_REQ_INVALID; 972 xpt_done(pccb); 973 break; 974 /* 975 * Execute target I/O request 976 */ 977 case XPT_TARGET_IO: 978 /* 979 * Don't (yet?) support vendor 980 * specific commands. 981 */ 982 TRM_DPRINTF(" XPT_TARGET_IO \n"); 983 pccb->ccb_h.status = CAM_REQ_INVALID; 984 xpt_done(pccb); 985 break; 986 /* 987 * Accept Host Target Mode CDB 988 */ 989 case XPT_ACCEPT_TARGET_IO: 990 /* 991 * Don't (yet?) support vendor 992 * specific commands. 993 */ 994 TRM_DPRINTF(" XPT_ACCEPT_TARGET_IO \n"); 995 pccb->ccb_h.status = CAM_REQ_INVALID; 996 xpt_done(pccb); 997 break; 998 /* 999 * Continue Host Target I/O Connection 1000 */ 1001 case XPT_CONT_TARGET_IO: 1002 /* 1003 * Don't (yet?) support vendor 1004 * specific commands. 1005 */ 1006 TRM_DPRINTF(" XPT_CONT_TARGET_IO \n"); 1007 pccb->ccb_h.status = CAM_REQ_INVALID; 1008 xpt_done(pccb); 1009 break; 1010 /* 1011 * Notify Host Target driver of event 1012 */ 1013 case XPT_IMMED_NOTIFY: 1014 TRM_DPRINTF(" XPT_IMMED_NOTIFY \n"); 1015 pccb->ccb_h.status = CAM_REQ_INVALID; 1016 xpt_done(pccb); 1017 break; 1018 /* 1019 * Acknowledgement of event 1020 */ 1021 case XPT_NOTIFY_ACK: 1022 TRM_DPRINTF(" XPT_NOTIFY_ACK \n"); 1023 pccb->ccb_h.status = CAM_REQ_INVALID; 1024 xpt_done(pccb); 1025 break; 1026 /* 1027 * XPT_VUNIQUE = 0x80 1028 */ 1029 case XPT_VUNIQUE: 1030 pccb->ccb_h.status = CAM_REQ_INVALID; 1031 xpt_done(pccb); 1032 break; 1033 default: 1034 pccb->ccb_h.status = CAM_REQ_INVALID; 1035 xpt_done(pccb); 1036 break; 1037 } 1038 } 1039 1040 static void 1041 trm_poll(struct cam_sim *psim) 1042 { 1043 1044 } 1045 1046 static void 1047 trm_ResetDevParam(PACB pACB) 1048 { 1049 PDCB pDCB, pdcb; 1050 PNVRAMTYPE pEEpromBuf; 1051 u_int8_t PeriodIndex; 1052 1053 pDCB = pACB->pLinkDCB; 1054 if (pDCB == NULL) 1055 return; 1056 pdcb = pDCB; 1057 do { 1058 pDCB->SyncMode &= ~(SYNC_NEGO_DONE+ WIDE_NEGO_DONE); 1059 pDCB->SyncPeriod = 0; 1060 pDCB->SyncOffset = 0; 1061 pEEpromBuf = &trm_eepromBuf[pACB->AdapterUnit]; 1062 pDCB->DevMode = 1063 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarCfg0; 1064 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 1065 PeriodIndex = 1066 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarPeriod & 0x07; 1067 pDCB->MaxNegoPeriod = dc395x_trm_clock_period[PeriodIndex]; 1068 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 1069 (pACB->Config & HCC_WIDE_CARD)) 1070 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 1071 pDCB = pDCB->pNextDCB; 1072 } 1073 while (pdcb != pDCB); 1074 } 1075 1076 static void 1077 trm_RecoverSRB(PACB pACB) 1078 { 1079 PDCB pDCB, pdcb; 1080 PSRB psrb, psrb2; 1081 u_int16_t cnt, i; 1082 1083 pDCB = pACB->pLinkDCB; 1084 if (pDCB == NULL) 1085 return; 1086 pdcb = pDCB; 1087 do { 1088 cnt = pdcb->GoingSRBCnt; 1089 psrb = pdcb->pGoingSRB; 1090 for (i = 0; i < cnt; i++) { 1091 psrb2 = psrb; 1092 psrb = psrb->pNextSRB; 1093 if (pdcb->pWaitingSRB) { 1094 psrb2->pNextSRB = pdcb->pWaitingSRB; 1095 pdcb->pWaitingSRB = psrb2; 1096 } else { 1097 pdcb->pWaitingSRB = psrb2; 1098 pdcb->pWaitLastSRB = psrb2; 1099 psrb2->pNextSRB = NULL; 1100 } 1101 } 1102 pdcb->GoingSRBCnt = 0; 1103 pdcb->pGoingSRB = NULL; 1104 pdcb->TagMask = 0; 1105 pdcb = pdcb->pNextDCB; 1106 } 1107 while (pdcb != pDCB); 1108 } 1109 1110 static void 1111 trm_reset(PACB pACB) 1112 { 1113 u_int16_t i; 1114 1115 TRM_DPRINTF("trm: RESET"); 1116 crit_enter(); 1117 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 1118 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 1119 1120 trm_ResetSCSIBus(pACB); 1121 for (i = 0; i < 500; i++) 1122 DELAY(1000); 1123 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 1124 /* Enable DMA interrupt */ 1125 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 1126 /* Clear DMA FIFO */ 1127 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1128 /* Clear SCSI FIFO */ 1129 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1130 trm_ResetDevParam(pACB); 1131 trm_DoingSRB_Done(pACB); 1132 pACB->pActiveDCB = NULL; 1133 pACB->ACBFlag = 0;/* RESET_DETECT, RESET_DONE ,RESET_DEV */ 1134 trm_DoWaitingSRB(pACB); 1135 /* Tell the XPT layer that a bus reset occured */ 1136 if (pACB->ppath != NULL) 1137 xpt_async(AC_BUS_RESET, pACB->ppath, NULL); 1138 crit_exit(); 1139 return; 1140 } 1141 1142 static u_int16_t 1143 trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB) 1144 { 1145 u_int16_t return_code; 1146 u_int8_t tag_number, scsicommand, i,command,identify_message; 1147 u_int8_t * ptr; 1148 u_long tag_mask; 1149 union ccb *pccb; 1150 struct ccb_scsiio *pcsio; 1151 1152 pccb = pSRB->pccb; 1153 pcsio = &pccb->csio; 1154 pSRB->TagNumber = 31; 1155 1156 trm_reg_write8(pACB->AdaptSCSIID, TRMREG_SCSI_HOSTID); 1157 trm_reg_write8(pDCB->TargetID, TRMREG_SCSI_TARGETID); 1158 trm_reg_write8(pDCB->SyncPeriod, TRMREG_SCSI_SYNC); 1159 trm_reg_write8(pDCB->SyncOffset, TRMREG_SCSI_OFFSET); 1160 pSRB->ScsiPhase = PH_BUS_FREE;/* initial phase */ 1161 /* Flush FIFO */ 1162 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1163 1164 identify_message = pDCB->IdentifyMsg; 1165 1166 if ((pSRB->CmdBlock[0] == INQUIRY) || 1167 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1168 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1169 if (((pDCB->SyncMode & WIDE_NEGO_ENABLE) && 1170 !(pDCB->SyncMode & WIDE_NEGO_DONE)) \ 1171 || ((pDCB->SyncMode & SYNC_NEGO_ENABLE) && 1172 !(pDCB->SyncMode & SYNC_NEGO_DONE))) { 1173 if (!(pDCB->IdentifyMsg & 7) || 1174 (pSRB->CmdBlock[0] != INQUIRY)) { 1175 scsicommand = SCMD_SEL_ATNSTOP; 1176 pSRB->SRBState = SRB_MSGOUT; 1177 goto polling; 1178 } 1179 } 1180 /* 1181 * Send identify message 1182 */ 1183 trm_reg_write8((identify_message & 0xBF) ,TRMREG_SCSI_FIFO); 1184 scsicommand = SCMD_SEL_ATN; 1185 pSRB->SRBState = SRB_START_; 1186 } else { 1187 /* not inquiry,request sense,auto request sense */ 1188 /* 1189 * Send identify message 1190 */ 1191 trm_reg_write8(identify_message,TRMREG_SCSI_FIFO); 1192 scsicommand = SCMD_SEL_ATN; 1193 pSRB->SRBState = SRB_START_; 1194 if (pDCB->SyncMode & EN_TAG_QUEUING) { 1195 /* Send Tag message */ 1196 /* 1197 * Get tag id 1198 */ 1199 tag_mask = 1; 1200 tag_number = 0; 1201 while (tag_mask & pDCB->TagMask) { 1202 tag_mask = tag_mask << 1; 1203 tag_number++; 1204 } 1205 /* 1206 * Send Tag id 1207 */ 1208 trm_reg_write8(MSG_SIMPLE_QTAG, TRMREG_SCSI_FIFO); 1209 trm_reg_write8(tag_number, TRMREG_SCSI_FIFO); 1210 pDCB->TagMask |= tag_mask; 1211 pSRB->TagNumber = tag_number; 1212 scsicommand = SCMD_SEL_ATN3; 1213 pSRB->SRBState = SRB_START_; 1214 } 1215 } 1216 polling: 1217 /* 1218 * Send CDB ..command block ......... 1219 */ 1220 if (pSRB->SRBFlag & AUTO_REQSENSE) { 1221 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1222 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1223 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1224 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1225 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1226 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1227 } else { 1228 ptr = (u_int8_t *) pSRB->CmdBlock; 1229 for (i = 0; i < pSRB->ScsiCmdLen ; i++) { 1230 command = *ptr++; 1231 trm_reg_write8(command,TRMREG_SCSI_FIFO); 1232 } 1233 } 1234 if (trm_reg_read16(TRMREG_SCSI_STATUS) & SCSIINTERRUPT) { 1235 /* 1236 * If trm_StartSCSI return 1 : 1237 * current interrupt status is interrupt disreenable 1238 * It's said that SCSI processor has more one SRB need to do, 1239 * SCSI processor has been occupied by one SRB. 1240 */ 1241 pSRB->SRBState = SRB_READY; 1242 pDCB->TagMask &= ~(1 << pSRB->TagNumber); 1243 return_code = 1; 1244 } else { 1245 /* 1246 * If trm_StartSCSI return 0 : 1247 * current interrupt status is interrupt enable 1248 * It's said that SCSI processor is unoccupied 1249 */ 1250 pSRB->ScsiPhase = SCSI_NOP1; /* SCSI bus free Phase */ 1251 pACB->pActiveDCB = pDCB; 1252 pDCB->pActiveSRB = pSRB; 1253 return_code = 0; 1254 trm_reg_write16(DO_DATALATCH | DO_HWRESELECT, 1255 TRMREG_SCSI_CONTROL);/* it's important for atn stop*/ 1256 /* 1257 * SCSI cammand 1258 */ 1259 trm_reg_write8(scsicommand,TRMREG_SCSI_COMMAND); 1260 } 1261 return (return_code); 1262 } 1263 1264 static void 1265 trm_Interrupt(void *vpACB) 1266 { 1267 PACB pACB; 1268 PDCB pDCB; 1269 PSRB pSRB; 1270 u_int16_t phase; 1271 void (*stateV)(PACB, PSRB, u_int8_t *); 1272 u_int8_t scsi_status=0, scsi_intstatus; 1273 1274 pACB = vpACB; 1275 1276 if (pACB == NULL) { 1277 TRM_DPRINTF("trm_Interrupt: pACB NULL return......"); 1278 return; 1279 } 1280 1281 scsi_status = trm_reg_read16(TRMREG_SCSI_STATUS); 1282 if (!(scsi_status & SCSIINTERRUPT)) { 1283 TRM_DPRINTF("trm_Interrupt: TRMREG_SCSI_STATUS scsi_status = NULL ,return......"); 1284 return; 1285 } 1286 TRM_DPRINTF("scsi_status=%2x,",scsi_status); 1287 1288 scsi_intstatus = trm_reg_read8(TRMREG_SCSI_INTSTATUS); 1289 1290 TRM_DPRINTF("scsi_intstatus=%2x,",scsi_intstatus); 1291 1292 if (scsi_intstatus & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1293 trm_Disconnect(pACB); 1294 return; 1295 } 1296 1297 if (scsi_intstatus & INT_RESELECTED) { 1298 trm_Reselect(pACB); 1299 return; 1300 } 1301 if (scsi_intstatus & INT_SCSIRESET) { 1302 trm_ScsiRstDetect(pACB); 1303 return; 1304 } 1305 1306 if (scsi_intstatus & (INT_BUSSERVICE | INT_CMDDONE)) { 1307 pDCB = pACB->pActiveDCB; 1308 pSRB = pDCB->pActiveSRB; 1309 if (pDCB) { 1310 if (pDCB->DCBFlag & ABORT_DEV_) 1311 trm_EnableMsgOutAbort1(pACB, pSRB); 1312 } 1313 phase = (u_int16_t) pSRB->ScsiPhase; /* phase: */ 1314 stateV = (void *) trm_SCSI_phase0[phase]; 1315 stateV(pACB, pSRB, &scsi_status); 1316 pSRB->ScsiPhase = scsi_status & PHASEMASK; 1317 /* phase:0,1,2,3,4,5,6,7 */ 1318 phase = (u_int16_t) scsi_status & PHASEMASK; 1319 stateV = (void *) trm_SCSI_phase1[phase]; 1320 stateV(pACB, pSRB, &scsi_status); 1321 } 1322 } 1323 1324 static void 1325 trm_MsgOutPhase0(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1326 { 1327 1328 if (pSRB->SRBState & (SRB_UNEXPECT_RESEL+SRB_ABORT_SENT)) 1329 *pscsi_status = PH_BUS_FREE; 1330 /*.. initial phase*/ 1331 } 1332 1333 static void 1334 trm_MsgOutPhase1(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1335 { 1336 u_int8_t bval; 1337 u_int16_t i, cnt; 1338 u_int8_t * ptr; 1339 PDCB pDCB; 1340 1341 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1342 pDCB = pACB->pActiveDCB; 1343 if (!(pSRB->SRBState & SRB_MSGOUT)) { 1344 cnt = pSRB->MsgCnt; 1345 if (cnt) { 1346 ptr = (u_int8_t *) pSRB->MsgOutBuf; 1347 for (i = 0; i < cnt; i++) { 1348 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1349 ptr++; 1350 } 1351 pSRB->MsgCnt = 0; 1352 if ((pDCB->DCBFlag & ABORT_DEV_) && 1353 (pSRB->MsgOutBuf[0] == MSG_ABORT)) { 1354 pSRB->SRBState = SRB_ABORT_SENT; 1355 } 1356 } else { 1357 bval = MSG_ABORT; 1358 if ((pSRB->CmdBlock[0] == INQUIRY) || 1359 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1360 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1361 if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1362 goto mop1; 1363 } 1364 } 1365 trm_reg_write8(bval, TRMREG_SCSI_FIFO); 1366 } 1367 } else { 1368 mop1: /* message out phase */ 1369 if (!(pSRB->SRBState & SRB_DO_WIDE_NEGO) 1370 && (pDCB->SyncMode & WIDE_NEGO_ENABLE)) { 1371 /* 1372 * WIDE DATA TRANSFER REQUEST code (03h) 1373 */ 1374 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | EN_ATN_STOP); 1375 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1376 TRMREG_SCSI_FIFO); 1377 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1378 /* (01h) */ 1379 trm_reg_write8(2,TRMREG_SCSI_FIFO); 1380 /* Message length (02h) */ 1381 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1382 /* wide data xfer (03h) */ 1383 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1384 /* width:0(8bit),1(16bit),2(32bit) */ 1385 pSRB->SRBState |= SRB_DO_WIDE_NEGO; 1386 } else if (!(pSRB->SRBState & SRB_DO_SYNC_NEGO) 1387 && (pDCB->SyncMode & SYNC_NEGO_ENABLE)) { 1388 /* 1389 * SYNCHRONOUS DATA TRANSFER REQUEST code (01h) 1390 */ 1391 if (!(pDCB->SyncMode & WIDE_NEGO_DONE)) 1392 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1393 TRMREG_SCSI_FIFO); 1394 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1395 /* (01h) */ 1396 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1397 /* Message length (03h) */ 1398 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1399 /* SYNCHRONOUS DATA TRANSFER REQUEST code (01h) */ 1400 trm_reg_write8(pDCB->MaxNegoPeriod,TRMREG_SCSI_FIFO); 1401 /* Transfer peeriod factor */ 1402 trm_reg_write8(SYNC_NEGO_OFFSET,TRMREG_SCSI_FIFO); 1403 /* REQ/ACK offset */ 1404 pSRB->SRBState |= SRB_DO_SYNC_NEGO; 1405 } 1406 } 1407 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1408 /* it's important for atn stop */ 1409 /* 1410 * SCSI cammand 1411 */ 1412 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1413 } 1414 1415 static void 1416 trm_CommandPhase0(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1417 { 1418 1419 } 1420 1421 static void 1422 trm_CommandPhase1(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1423 { 1424 PDCB pDCB; 1425 u_int8_t * ptr; 1426 u_int16_t i, cnt; 1427 union ccb *pccb; 1428 struct ccb_scsiio *pcsio; 1429 1430 pccb = pSRB->pccb; 1431 pcsio = &pccb->csio; 1432 1433 trm_reg_write16(DO_CLRATN | DO_CLRFIFO , TRMREG_SCSI_CONTROL); 1434 if (!(pSRB->SRBFlag & AUTO_REQSENSE)) { 1435 cnt = (u_int16_t) pSRB->ScsiCmdLen; 1436 ptr = (u_int8_t *) pSRB->CmdBlock; 1437 for (i = 0; i < cnt; i++) { 1438 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1439 ptr++; 1440 } 1441 } else { 1442 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1443 pDCB = pACB->pActiveDCB; 1444 /* target id */ 1445 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1446 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1447 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1448 /* sizeof(struct scsi_sense_data) */ 1449 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1450 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1451 } 1452 pSRB->SRBState = SRB_COMMAND; 1453 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1454 /* it's important for atn stop*/ 1455 /* 1456 * SCSI cammand 1457 */ 1458 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1459 } 1460 1461 static void 1462 trm_DataOutPhase0(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1463 { 1464 PDCB pDCB; 1465 u_int8_t TempDMAstatus,SGIndexTemp; 1466 u_int16_t scsi_status; 1467 PSEG pseg; 1468 u_long TempSRBXferredLength,dLeftCounter=0; 1469 1470 pDCB = pSRB->pSRBDCB; 1471 scsi_status = *pscsi_status; 1472 1473 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1474 if (scsi_status & PARITYERROR) 1475 pSRB->SRBStatus |= PARITY_ERROR; 1476 if (!(scsi_status & SCSIXFERDONE)) { 1477 /* 1478 * when data transfer from DMA FIFO to SCSI FIFO 1479 * if there was some data left in SCSI FIFO 1480 */ 1481 dLeftCounter = (u_long) 1482 (trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x1F); 1483 if (pDCB->SyncPeriod & WIDE_SYNC) { 1484 /* 1485 * if WIDE scsi SCSI FIFOCNT unit is word 1486 * so need to * 2 1487 */ 1488 dLeftCounter <<= 1; 1489 } 1490 } 1491 /* 1492 * caculate all the residue data that not yet tranfered 1493 * SCSI transfer counter + left in SCSI FIFO data 1494 * 1495 * .....TRM_SCSI_COUNTER (24bits) 1496 * The counter always decrement by one for every SCSI byte 1497 *transfer. 1498 * .....TRM_SCSI_FIFOCNT (5bits) 1499 * The counter is SCSI FIFO offset counter 1500 */ 1501 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1502 if (dLeftCounter == 1) { 1503 dLeftCounter = 0; 1504 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1505 } 1506 if ((dLeftCounter == 0) || 1507 (scsi_status & SCSIXFERCNT_2_ZERO)) { 1508 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1509 while (!(TempDMAstatus & DMAXFERCOMP)) { 1510 TempDMAstatus = 1511 trm_reg_read8(TRMREG_DMA_STATUS); 1512 } 1513 pSRB->SRBTotalXferLength = 0; 1514 } else { 1515 /* Update SG list */ 1516 /* 1517 * if transfer not yet complete 1518 * there were some data residue in SCSI FIFO or 1519 * SCSI transfer counter not empty 1520 */ 1521 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1522 /* 1523 * data that had transferred length 1524 */ 1525 TempSRBXferredLength = 1526 pSRB->SRBTotalXferLength - dLeftCounter; 1527 /* 1528 * next time to be transferred length 1529 */ 1530 pSRB->SRBTotalXferLength = dLeftCounter; 1531 /* 1532 * parsing from last time disconnect SRBSGIndex 1533 */ 1534 pseg = 1535 pSRB->SRBSGListPointer + pSRB->SRBSGIndex; 1536 for (SGIndexTemp = pSRB->SRBSGIndex; 1537 SGIndexTemp < pSRB->SRBSGCount; 1538 SGIndexTemp++) { 1539 /* 1540 * find last time which SG transfer be 1541 * disconnect 1542 */ 1543 if (TempSRBXferredLength >= 1544 pseg->length) 1545 TempSRBXferredLength -= 1546 pseg->length; 1547 else { 1548 /* 1549 * update last time disconnected SG 1550 * list 1551 */ 1552 pseg->length -= 1553 TempSRBXferredLength; 1554 /* residue data length */ 1555 pseg->address += 1556 TempSRBXferredLength; 1557 /* residue data pointer */ 1558 pSRB->SRBSGIndex = SGIndexTemp; 1559 break; 1560 } 1561 pseg++; 1562 } 1563 } 1564 } 1565 } 1566 trm_reg_write8(STOPDMAXFER ,TRMREG_DMA_CONTROL); 1567 } 1568 1569 1570 static void 1571 trm_DataOutPhase1(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1572 { 1573 u_int16_t ioDir; 1574 /* 1575 * do prepare befor transfer when data out phase 1576 */ 1577 1578 ioDir = XFERDATAOUT; 1579 trm_DataIO_transfer(pACB, pSRB, ioDir); 1580 } 1581 1582 static void 1583 trm_DataInPhase0(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1584 { 1585 u_int8_t bval,SGIndexTemp; 1586 u_int16_t scsi_status; 1587 PSEG pseg; 1588 u_long TempSRBXferredLength,dLeftCounter = 0; 1589 1590 scsi_status = *pscsi_status; 1591 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1592 if (scsi_status & PARITYERROR) 1593 pSRB->SRBStatus |= PARITY_ERROR; 1594 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1595 if ((dLeftCounter == 0) || (scsi_status & SCSIXFERCNT_2_ZERO)) { 1596 bval = trm_reg_read8(TRMREG_DMA_STATUS); 1597 while (!(bval & DMAXFERCOMP)) 1598 bval = trm_reg_read8(TRMREG_DMA_STATUS); 1599 pSRB->SRBTotalXferLength = 0; 1600 } else { 1601 /* 1602 * parsing the case: 1603 * when a transfer not yet complete 1604 * but be disconnected by uper layer 1605 * if transfer not yet complete 1606 * there were some data residue in SCSI FIFO or 1607 * SCSI transfer counter not empty 1608 */ 1609 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1610 /* 1611 * data that had transferred length 1612 */ 1613 TempSRBXferredLength = 1614 pSRB->SRBTotalXferLength - dLeftCounter; 1615 /* 1616 * next time to be transferred length 1617 */ 1618 pSRB->SRBTotalXferLength = dLeftCounter; 1619 /* 1620 * parsing from last time disconnect SRBSGIndex 1621 */ 1622 pseg = pSRB->SRBSGListPointer + pSRB->SRBSGIndex; 1623 for (SGIndexTemp = pSRB->SRBSGIndex; 1624 SGIndexTemp < pSRB->SRBSGCount; 1625 SGIndexTemp++) { 1626 /* 1627 * find last time which SG transfer be disconnect 1628 */ 1629 if (TempSRBXferredLength >= pseg->length) 1630 TempSRBXferredLength -= pseg->length; 1631 else { 1632 /* 1633 * update last time disconnected SG list 1634 */ 1635 pseg->length -= TempSRBXferredLength; 1636 /* residue data length */ 1637 pseg->address += TempSRBXferredLength; 1638 /* residue data pointer */ 1639 pSRB->SRBSGIndex = SGIndexTemp; 1640 break; 1641 } 1642 pseg++; 1643 } 1644 } 1645 } 1646 } 1647 } 1648 1649 static void 1650 trm_DataInPhase1(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1651 { 1652 u_int16_t ioDir; 1653 /* 1654 * do prepare befor transfer when data in phase 1655 */ 1656 1657 ioDir = XFERDATAIN; 1658 trm_DataIO_transfer(pACB, pSRB, ioDir); 1659 } 1660 1661 static void 1662 trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir) 1663 { 1664 u_int8_t bval; 1665 PDCB pDCB; 1666 1667 pDCB = pSRB->pSRBDCB; 1668 if (pSRB->SRBSGIndex < pSRB->SRBSGCount) { 1669 if (pSRB->SRBTotalXferLength != 0) { 1670 pSRB->SRBSGPhyAddr = vtophys(pSRB->SRBSGListPointer); 1671 /* 1672 * load what physical address of Scatter/Gather list 1673 table want to be transfer 1674 */ 1675 pSRB->SRBState = SRB_DATA_XFER; 1676 trm_reg_write32(0, TRMREG_DMA_XHIGHADDR); 1677 trm_reg_write32( 1678 (pSRB->SRBSGPhyAddr + 1679 ((u_long)pSRB->SRBSGIndex << 3)), 1680 TRMREG_DMA_XLOWADDR); 1681 /* 1682 * load how many bytes in the Scatter/Gather 1683 * list table 1684 */ 1685 trm_reg_write32( 1686 ((u_long)(pSRB->SRBSGCount - pSRB->SRBSGIndex) << 3), 1687 TRMREG_DMA_XCNT); 1688 /* 1689 * load total transfer length (24bits) max value 1690 * 16Mbyte 1691 */ 1692 trm_reg_write32(pSRB->SRBTotalXferLength, 1693 TRMREG_SCSI_COUNTER); 1694 /* Start DMA transfer */ 1695 trm_reg_write16(ioDir, TRMREG_DMA_COMMAND); 1696 /* Start SCSI transfer */ 1697 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1698 /* it's important for atn stop */ 1699 /* 1700 * SCSI cammand 1701 */ 1702 bval = (ioDir == XFERDATAOUT) ? 1703 SCMD_DMA_OUT : SCMD_DMA_IN; 1704 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1705 } else { 1706 /* xfer pad */ 1707 if (pSRB->SRBSGCount) { 1708 pSRB->AdaptStatus = H_OVER_UNDER_RUN; 1709 pSRB->SRBStatus |= OVER_RUN; 1710 } 1711 if (pDCB->SyncPeriod & WIDE_SYNC) 1712 trm_reg_write32(2,TRMREG_SCSI_COUNTER); 1713 else 1714 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 1715 if (ioDir == XFERDATAOUT) 1716 trm_reg_write16(0, TRMREG_SCSI_FIFO); 1717 else 1718 trm_reg_read16(TRMREG_SCSI_FIFO); 1719 pSRB->SRBState |= SRB_XFERPAD; 1720 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1721 /* it's important for atn stop */ 1722 /* 1723 * SCSI cammand 1724 */ 1725 bval = (ioDir == XFERDATAOUT) ? 1726 SCMD_FIFO_OUT : SCMD_FIFO_IN; 1727 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1728 } 1729 } 1730 } 1731 1732 static void 1733 trm_StatusPhase0(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1734 { 1735 1736 pSRB->TargetStatus = trm_reg_read8(TRMREG_SCSI_FIFO); 1737 pSRB->SRBState = SRB_COMPLETED; 1738 *pscsi_status = PH_BUS_FREE; 1739 /*.. initial phase*/ 1740 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1741 /* it's important for atn stop */ 1742 /* 1743 * SCSI cammand 1744 */ 1745 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1746 } 1747 1748 1749 1750 static void 1751 trm_StatusPhase1(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1752 { 1753 1754 if (trm_reg_read16(TRMREG_DMA_COMMAND) & 0x0001) { 1755 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1756 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1757 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1758 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1759 } else { 1760 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1761 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1762 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1763 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1764 } 1765 pSRB->SRBState = SRB_STATUS; 1766 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1767 /* it's important for atn stop */ 1768 /* 1769 * SCSI cammand 1770 */ 1771 trm_reg_write8(SCMD_COMP, TRMREG_SCSI_COMMAND); 1772 } 1773 1774 /* 1775 *scsiiom 1776 * trm_MsgInPhase0: one of trm_SCSI_phase0[] vectors 1777 * stateV = (void *) trm_SCSI_phase0[phase] 1778 * if phase =7 1779 * extended message codes: 1780 * 1781 * code description 1782 * 1783 * 02h Reserved 1784 * 00h MODIFY DATA POINTER 1785 * 01h SYNCHRONOUS DATA TRANSFER REQUEST 1786 * 03h WIDE DATA TRANSFER REQUEST 1787 * 04h - 7Fh Reserved 1788 * 80h - FFh Vendor specific 1789 * 1790 */ 1791 1792 static void 1793 trm_MsgInPhase0(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1794 { 1795 u_int8_t message_in_code,bIndex,message_in_tag_id; 1796 PDCB pDCB; 1797 PSRB pSRBTemp; 1798 1799 pDCB = pACB->pActiveDCB; 1800 1801 message_in_code = trm_reg_read8(TRMREG_SCSI_FIFO); 1802 if (!(pSRB->SRBState & SRB_EXTEND_MSGIN)) { 1803 if (message_in_code == MSG_DISCONNECT) { 1804 pSRB->SRBState = SRB_DISCONNECT; 1805 goto min6; 1806 } else if (message_in_code == MSG_SAVE_PTR) { 1807 goto min6; 1808 } else if ((message_in_code == MSG_EXTENDED) || 1809 ((message_in_code >= MSG_SIMPLE_QTAG) && 1810 (message_in_code <= MSG_ORDER_QTAG))) { 1811 pSRB->SRBState |= SRB_EXTEND_MSGIN; 1812 pSRB->MsgInBuf[0] = message_in_code; 1813 /* extended message (01h) */ 1814 pSRB->MsgCnt = 1; 1815 pSRB->pMsgPtr = &pSRB->MsgInBuf[1]; 1816 /* extended message length (n) */ 1817 goto min6; 1818 } else if (message_in_code == MSG_REJECT_) { 1819 /* Reject message */ 1820 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 1821 /* do wide nego reject */ 1822 pDCB = pSRB->pSRBDCB; 1823 pDCB->SyncMode |= WIDE_NEGO_DONE; 1824 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | 1825 EN_ATN_STOP | WIDE_NEGO_ENABLE); 1826 pSRB->SRBState &= ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 1827 if ((pDCB->SyncMode & SYNC_NEGO_ENABLE) 1828 && !(pDCB->SyncMode & SYNC_NEGO_DONE)) { 1829 /* Set ATN, in case ATN was clear */ 1830 pSRB->SRBState |= SRB_MSGOUT; 1831 trm_reg_write16( 1832 DO_SETATN, 1833 TRMREG_SCSI_CONTROL); 1834 } else { 1835 /* Clear ATN */ 1836 trm_reg_write16( 1837 DO_CLRATN, 1838 TRMREG_SCSI_CONTROL); 1839 } 1840 } else if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1841 /* do sync nego reject */ 1842 trm_reg_write16(DO_CLRATN,TRMREG_SCSI_CONTROL); 1843 if (pSRB->SRBState & SRB_DO_SYNC_NEGO) { 1844 pDCB = pSRB->pSRBDCB; 1845 pDCB->SyncMode &= 1846 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 1847 pDCB->SyncPeriod = 0; 1848 pDCB->SyncOffset = 0; 1849 goto re_prog; 1850 } 1851 } 1852 goto min6; 1853 } else if (message_in_code == MSG_IGNOREWIDE) { 1854 trm_reg_write32(1, TRMREG_SCSI_COUNTER); 1855 trm_reg_read8(TRMREG_SCSI_FIFO); 1856 goto min6; 1857 } else { 1858 /* Restore data pointer message */ 1859 /* Save data pointer message */ 1860 /* Completion message */ 1861 /* NOP message */ 1862 goto min6; 1863 } 1864 } else { 1865 /* 1866 * Parsing incomming extented messages 1867 */ 1868 *pSRB->pMsgPtr = message_in_code; 1869 pSRB->MsgCnt++; 1870 pSRB->pMsgPtr++; 1871 TRM_DPRINTF("pSRB->MsgInBuf[0]=%2x \n ",pSRB->MsgInBuf[0]); 1872 TRM_DPRINTF("pSRB->MsgInBuf[1]=%2x \n ",pSRB->MsgInBuf[1]); 1873 TRM_DPRINTF("pSRB->MsgInBuf[2]=%2x \n ",pSRB->MsgInBuf[2]); 1874 TRM_DPRINTF("pSRB->MsgInBuf[3]=%2x \n ",pSRB->MsgInBuf[3]); 1875 TRM_DPRINTF("pSRB->MsgInBuf[4]=%2x \n ",pSRB->MsgInBuf[4]); 1876 if ((pSRB->MsgInBuf[0] >= MSG_SIMPLE_QTAG) 1877 && (pSRB->MsgInBuf[0] <= MSG_ORDER_QTAG)) { 1878 /* 1879 * is QUEUE tag message : 1880 * 1881 * byte 0: 1882 * HEAD QUEUE TAG (20h) 1883 * ORDERED QUEUE TAG (21h) 1884 * SIMPLE QUEUE TAG (22h) 1885 * byte 1: 1886 * Queue tag (00h - FFh) 1887 */ 1888 if (pSRB->MsgCnt == 2) { 1889 pSRB->SRBState = 0; 1890 message_in_tag_id = pSRB->MsgInBuf[1]; 1891 pSRB = pDCB->pGoingSRB; 1892 pSRBTemp = pDCB->pGoingLastSRB; 1893 if (pSRB) { 1894 for (;;) { 1895 if (pSRB->TagNumber != 1896 message_in_tag_id) { 1897 if (pSRB == pSRBTemp) { 1898 goto mingx0; 1899 } 1900 pSRB = pSRB->pNextSRB; 1901 } else 1902 break; 1903 } 1904 if (pDCB->DCBFlag & ABORT_DEV_) { 1905 pSRB->SRBState = SRB_ABORT_SENT; 1906 trm_EnableMsgOutAbort1( 1907 pACB, pSRB); 1908 } 1909 if (!(pSRB->SRBState & SRB_DISCONNECT)) 1910 goto mingx0; 1911 pDCB->pActiveSRB = pSRB; 1912 pSRB->SRBState = SRB_DATA_XFER; 1913 } else { 1914 mingx0: 1915 pSRB = pACB->pTmpSRB; 1916 pSRB->SRBState = SRB_UNEXPECT_RESEL; 1917 pDCB->pActiveSRB = pSRB; 1918 pSRB->MsgOutBuf[0] = MSG_ABORT_TAG; 1919 trm_EnableMsgOutAbort2( 1920 pACB, 1921 pSRB); 1922 } 1923 } 1924 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 1925 (pSRB->MsgInBuf[2] == 3) && (pSRB->MsgCnt == 4)) { 1926 /* 1927 * is Wide data xfer Extended message : 1928 * ====================================== 1929 * WIDE DATA TRANSFER REQUEST 1930 * ====================================== 1931 * byte 0 : Extended message (01h) 1932 * byte 1 : Extended message length (02h) 1933 * byte 2 : WIDE DATA TRANSFER code (03h) 1934 * byte 3 : Transfer width exponent 1935 */ 1936 pDCB = pSRB->pSRBDCB; 1937 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_WIDE_NEGO); 1938 if ((pSRB->MsgInBuf[1] != 2)) { 1939 /* Length is wrong, reject it */ 1940 pDCB->SyncMode &= 1941 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 1942 pSRB->MsgCnt = 1; 1943 pSRB->MsgInBuf[0] = MSG_REJECT_; 1944 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 1945 goto min6; 1946 } 1947 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 1948 /* Do wide negoniation */ 1949 if (pSRB->MsgInBuf[3] > 2) { 1950 /* > 32 bit */ 1951 /* reject_msg: */ 1952 pDCB->SyncMode &= 1953 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 1954 pSRB->MsgCnt = 1; 1955 pSRB->MsgInBuf[0] = MSG_REJECT_; 1956 trm_reg_write16(DO_SETATN, 1957 TRMREG_SCSI_CONTROL); 1958 goto min6; 1959 } 1960 if (pSRB->MsgInBuf[3] == 2) { 1961 pSRB->MsgInBuf[3] = 1; 1962 /* do 16 bits */ 1963 } else { 1964 if (!(pDCB->SyncMode 1965 & WIDE_NEGO_DONE)) { 1966 pSRB->SRBState &= 1967 ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 1968 pDCB->SyncMode |= 1969 WIDE_NEGO_DONE; 1970 pDCB->SyncMode &= 1971 ~(SYNC_NEGO_DONE | 1972 EN_ATN_STOP | 1973 WIDE_NEGO_ENABLE); 1974 if (pSRB->MsgInBuf[3] != 0) { 1975 /* is Wide data xfer */ 1976 pDCB->SyncPeriod |= 1977 WIDE_SYNC; 1978 pDCB->tinfo.current.width 1979 = MSG_EXT_WDTR_BUS_16_BIT; 1980 pDCB->tinfo.goal.width 1981 = MSG_EXT_WDTR_BUS_16_BIT; 1982 } 1983 } 1984 } 1985 } else 1986 pSRB->MsgInBuf[3] = 0; 1987 pSRB->SRBState |= SRB_MSGOUT; 1988 trm_reg_write16(DO_SETATN,TRMREG_SCSI_CONTROL); 1989 goto min6; 1990 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 1991 (pSRB->MsgInBuf[2] == 1) && (pSRB->MsgCnt == 5)) { 1992 /* 1993 * is 8bit transfer Extended message : 1994 * ================================= 1995 * SYNCHRONOUS DATA TRANSFER REQUEST 1996 * ================================= 1997 * byte 0 : Extended message (01h) 1998 * byte 1 : Extended message length (03) 1999 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h) 2000 * byte 3 : Transfer period factor 2001 * byte 4 : REQ/ACK offset 2002 */ 2003 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_SYNC_NEGO); 2004 if ((pSRB->MsgInBuf[1] != 3) || 2005 (pSRB->MsgInBuf[2] != 1)) { 2006 /* reject_msg: */ 2007 pSRB->MsgCnt = 1; 2008 pSRB->MsgInBuf[0] = MSG_REJECT_; 2009 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2010 } else if (!(pSRB->MsgInBuf[3]) || !(pSRB->MsgInBuf[4])) { 2011 /* set async */ 2012 pDCB = pSRB->pSRBDCB; 2013 /* disable sync & sync nego */ 2014 pDCB->SyncMode &= 2015 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 2016 pDCB->SyncPeriod = 0; 2017 pDCB->SyncOffset = 0; 2018 pDCB->tinfo.goal.period = 0; 2019 pDCB->tinfo.goal.offset = 0; 2020 pDCB->tinfo.current.period = 0; 2021 pDCB->tinfo.current.offset = 0; 2022 pDCB->tinfo.current.width = 2023 MSG_EXT_WDTR_BUS_8_BIT; 2024 goto re_prog; 2025 } else { 2026 /* set sync */ 2027 pDCB = pSRB->pSRBDCB; 2028 pDCB->SyncMode |= 2029 SYNC_NEGO_ENABLE+SYNC_NEGO_DONE; 2030 pDCB->MaxNegoPeriod = pSRB->MsgInBuf[3]; 2031 /* Transfer period factor */ 2032 pDCB->SyncOffset = pSRB->MsgInBuf[4]; 2033 /* REQ/ACK offset */ 2034 for (bIndex = 0; bIndex < 7; bIndex++) { 2035 if (pSRB->MsgInBuf[3] <= 2036 dc395x_trm_clock_period[bIndex]) { 2037 break; 2038 } 2039 } 2040 pDCB->tinfo.goal.period = 2041 dc395x_trm_tinfo_sync_period[bIndex]; 2042 pDCB->tinfo.current.period = 2043 dc395x_trm_tinfo_sync_period[bIndex]; 2044 pDCB->tinfo.goal.offset = pDCB->SyncOffset; 2045 pDCB->tinfo.current.offset = pDCB->SyncOffset; 2046 pDCB->SyncPeriod |= (bIndex | ALT_SYNC); 2047 re_prog: 2048 /* 2049 * 2050 * program SCSI control register 2051 * 2052 */ 2053 trm_reg_write8(pDCB->SyncPeriod, 2054 TRMREG_SCSI_SYNC); 2055 trm_reg_write8(pDCB->SyncOffset, 2056 TRMREG_SCSI_OFFSET); 2057 trm_SetXferRate(pACB,pSRB,pDCB); 2058 } 2059 } 2060 } 2061 min6: 2062 *pscsi_status = PH_BUS_FREE; 2063 /* .. initial phase */ 2064 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2065 /* it's important for atn stop */ 2066 /* 2067 * SCSI cammand 2068 */ 2069 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2070 } 2071 2072 static void 2073 trm_MsgInPhase1(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 2074 { 2075 2076 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 2077 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 2078 if (!(pSRB->SRBState & SRB_MSGIN)) { 2079 pSRB->SRBState &= SRB_DISCONNECT; 2080 pSRB->SRBState |= SRB_MSGIN; 2081 } 2082 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2083 /* it's important for atn stop*/ 2084 /* 2085 * SCSI cammand 2086 */ 2087 trm_reg_write8(SCMD_FIFO_IN, TRMREG_SCSI_COMMAND); 2088 } 2089 2090 static void 2091 trm_Nop0(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 2092 { 2093 2094 } 2095 2096 static void 2097 trm_Nop1(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 2098 { 2099 2100 } 2101 2102 static void 2103 trm_SetXferRate(PACB pACB,PSRB pSRB, PDCB pDCB) 2104 { 2105 u_int16_t cnt, i; 2106 u_int8_t bval; 2107 PDCB pDCBTemp; 2108 u_int target_id,target_lun; 2109 2110 /* 2111 * set all lun device's period , offset 2112 */ 2113 target_id = pSRB->pccb->ccb_h.target_id; 2114 target_lun = pSRB->pccb->ccb_h.target_lun; 2115 TRM_DPRINTF("trm_SetXferRate:target_id= %d ,target_lun= %d \n" 2116 ,target_id,target_lun); 2117 if (!(pDCB->IdentifyMsg & 0x07)) { 2118 if (!pACB->scan_devices[target_id][target_lun]) { 2119 pDCBTemp = pACB->pLinkDCB; 2120 cnt = pACB->DeviceCnt; 2121 bval = pDCB->TargetID; 2122 for (i = 0; i < cnt; i++) { 2123 if (pDCBTemp->TargetID == bval) { 2124 pDCBTemp->SyncPeriod = pDCB->SyncPeriod; 2125 pDCBTemp->SyncOffset = pDCB->SyncOffset; 2126 pDCBTemp->SyncMode = pDCB->SyncMode; 2127 } 2128 pDCBTemp = pDCBTemp->pNextDCB; 2129 } 2130 } 2131 } 2132 return; 2133 } 2134 2135 /* 2136 * scsiiom 2137 * trm_Interrupt 2138 * 2139 * 2140 * ---SCSI bus phase 2141 * 2142 * PH_DATA_OUT 0x00 Data out phase 2143 * PH_DATA_IN 0x01 Data in phase 2144 * PH_COMMAND 0x02 Command phase 2145 * PH_STATUS 0x03 Status phase 2146 * PH_BUS_FREE 0x04 Invalid phase used as bus free 2147 * PH_BUS_FREE 0x05 Invalid phase used as bus free 2148 * PH_MSG_OUT 0x06 Message out phase 2149 * PH_MSG_IN 0x07 Message in phase 2150 * 2151 */ 2152 static void 2153 trm_Disconnect(PACB pACB) 2154 { 2155 PDCB pDCB; 2156 PSRB pSRB, psrb; 2157 u_int16_t i,j, cnt; 2158 u_int8_t bval; 2159 u_int target_id,target_lun; 2160 2161 TRM_DPRINTF("trm_Disconnect...............\n "); 2162 2163 crit_enter(); 2164 pDCB = pACB->pActiveDCB; 2165 if (!pDCB) { 2166 TRM_DPRINTF(" Exception Disconnect DCB=NULL..............\n "); 2167 j = 400; 2168 while (--j) 2169 DELAY(1); 2170 /* 1 msec */ 2171 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), 2172 TRMREG_SCSI_CONTROL); 2173 crit_exit(); 2174 return; 2175 } 2176 pSRB = pDCB->pActiveSRB; 2177 /* bug pSRB=0 */ 2178 target_id = pSRB->pccb->ccb_h.target_id; 2179 target_lun = pSRB->pccb->ccb_h.target_lun; 2180 TRM_DPRINTF(":pDCB->pActiveSRB= %8x \n ",(u_int) pDCB->pActiveSRB); 2181 pACB->pActiveDCB = 0; 2182 pSRB->ScsiPhase = PH_BUS_FREE; 2183 /* SCSI bus free Phase */ 2184 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), TRMREG_SCSI_CONTROL); 2185 if (pSRB->SRBState & SRB_UNEXPECT_RESEL) { 2186 pSRB->SRBState = 0; 2187 trm_DoWaitingSRB(pACB); 2188 } else if (pSRB->SRBState & SRB_ABORT_SENT) { 2189 pDCB->TagMask = 0; 2190 pDCB->DCBFlag = 0; 2191 cnt = pDCB->GoingSRBCnt; 2192 pDCB->GoingSRBCnt = 0; 2193 pSRB = pDCB->pGoingSRB; 2194 for (i = 0; i < cnt; i++) { 2195 psrb = pSRB->pNextSRB; 2196 pSRB->pNextSRB = pACB->pFreeSRB; 2197 pACB->pFreeSRB = pSRB; 2198 pSRB = psrb; 2199 } 2200 pDCB->pGoingSRB = 0; 2201 trm_DoWaitingSRB(pACB); 2202 } else { 2203 if ((pSRB->SRBState & (SRB_START_+SRB_MSGOUT)) || 2204 !(pSRB->SRBState & (SRB_DISCONNECT+SRB_COMPLETED))) { 2205 /* Selection time out */ 2206 if (!(pACB->scan_devices[target_id][target_lun])) { 2207 pSRB->SRBState = SRB_READY; 2208 trm_RewaitSRB(pDCB, pSRB); 2209 } else { 2210 pSRB->TargetStatus = SCSI_STAT_SEL_TIMEOUT; 2211 goto disc1; 2212 } 2213 } else if (pSRB->SRBState & SRB_DISCONNECT) { 2214 /* 2215 * SRB_DISCONNECT 2216 */ 2217 trm_DoWaitingSRB(pACB); 2218 } else if (pSRB->SRBState & SRB_COMPLETED) { 2219 disc1: 2220 /* 2221 * SRB_COMPLETED 2222 */ 2223 if (pDCB->MaxCommand > 1) { 2224 bval = pSRB->TagNumber; 2225 pDCB->TagMask &= (~(1 << bval)); 2226 /* free tag mask */ 2227 } 2228 pDCB->pActiveSRB = 0; 2229 pSRB->SRBState = SRB_FREE; 2230 trm_SRBdone(pACB, pDCB, pSRB); 2231 } 2232 } 2233 crit_exit(); 2234 return; 2235 } 2236 2237 static void 2238 trm_Reselect(PACB pACB) 2239 { 2240 PDCB pDCB; 2241 PSRB pSRB; 2242 u_int16_t RselTarLunId; 2243 2244 TRM_DPRINTF("trm_Reselect................. \n"); 2245 pDCB = pACB->pActiveDCB; 2246 if (pDCB) { 2247 /* Arbitration lost but Reselection win */ 2248 pSRB = pDCB->pActiveSRB; 2249 pSRB->SRBState = SRB_READY; 2250 trm_RewaitSRB(pDCB, pSRB); 2251 } 2252 /* Read Reselected Target Id and LUN */ 2253 RselTarLunId = trm_reg_read16(TRMREG_SCSI_TARGETID) & 0x1FFF; 2254 pDCB = pACB->pLinkDCB; 2255 while (RselTarLunId != *((u_int16_t *) &pDCB->TargetID)) { 2256 /* get pDCB of the reselect id */ 2257 pDCB = pDCB->pNextDCB; 2258 } 2259 2260 pACB->pActiveDCB = pDCB; 2261 if (pDCB->SyncMode & EN_TAG_QUEUING) { 2262 pSRB = pACB->pTmpSRB; 2263 pDCB->pActiveSRB = pSRB; 2264 } else { 2265 pSRB = pDCB->pActiveSRB; 2266 if (!pSRB || !(pSRB->SRBState & SRB_DISCONNECT)) { 2267 /* 2268 * abort command 2269 */ 2270 pSRB = pACB->pTmpSRB; 2271 pSRB->SRBState = SRB_UNEXPECT_RESEL; 2272 pDCB->pActiveSRB = pSRB; 2273 trm_EnableMsgOutAbort1(pACB, pSRB); 2274 } else { 2275 if (pDCB->DCBFlag & ABORT_DEV_) { 2276 pSRB->SRBState = SRB_ABORT_SENT; 2277 trm_EnableMsgOutAbort1(pACB, pSRB); 2278 } else 2279 pSRB->SRBState = SRB_DATA_XFER; 2280 } 2281 } 2282 pSRB->ScsiPhase = PH_BUS_FREE; 2283 /* SCSI bus free Phase */ 2284 /* 2285 * Program HA ID, target ID, period and offset 2286 */ 2287 trm_reg_write8((u_int8_t) RselTarLunId,TRMREG_SCSI_TARGETID); 2288 /* target ID */ 2289 trm_reg_write8(pACB->AdaptSCSIID,TRMREG_SCSI_HOSTID); 2290 /* host ID */ 2291 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC); 2292 /* period */ 2293 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET); 2294 /* offset */ 2295 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2296 /* it's important for atn stop*/ 2297 /* 2298 * SCSI cammand 2299 */ 2300 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2301 /* to rls the /ACK signal */ 2302 } 2303 2304 static void 2305 trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB) 2306 { 2307 PSRB psrb; 2308 u_int8_t bval, bval1,status; 2309 union ccb *pccb; 2310 struct ccb_scsiio *pcsio; 2311 PSCSI_INQDATA ptr; 2312 u_int target_id,target_lun; 2313 PDCB pTempDCB; 2314 2315 pccb = pSRB->pccb; 2316 if (pccb == NULL) 2317 return; 2318 pcsio = &pccb->csio; 2319 target_id = pSRB->pccb->ccb_h.target_id; 2320 target_lun = pSRB->pccb->ccb_h.target_lun; 2321 if ((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2322 bus_dmasync_op_t op; 2323 if ((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 2324 op = BUS_DMASYNC_POSTREAD; 2325 else 2326 op = BUS_DMASYNC_POSTWRITE; 2327 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 2328 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 2329 } 2330 /* 2331 * 2332 * target status 2333 * 2334 */ 2335 status = pSRB->TargetStatus; 2336 pcsio->scsi_status=SCSI_STAT_GOOD; 2337 pccb->ccb_h.status = CAM_REQ_CMP; 2338 if (pSRB->SRBFlag & AUTO_REQSENSE) { 2339 /* 2340 * status of auto request sense 2341 */ 2342 pSRB->SRBFlag &= ~AUTO_REQSENSE; 2343 pSRB->AdaptStatus = 0; 2344 pSRB->TargetStatus = SCSI_STATUS_CHECK_COND; 2345 2346 if (status == SCSI_STATUS_CHECK_COND) { 2347 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2348 goto ckc_e; 2349 } 2350 *((u_long *) &(pSRB->CmdBlock[0])) = pSRB->Segment0[0]; 2351 *((u_long *) &(pSRB->CmdBlock[4])) = pSRB->Segment0[1]; 2352 pSRB->SRBTotalXferLength = pSRB->Segment1[1]; 2353 pSRB->SegmentX[0].address = pSRB->SgSenseTemp.address; 2354 pSRB->SegmentX[0].length = pSRB->SgSenseTemp.length; 2355 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2356 pccb->ccb_h.status = CAM_AUTOSNS_VALID; 2357 goto ckc_e; 2358 } 2359 /* 2360 * target status 2361 */ 2362 if (status) { 2363 if (status == SCSI_STATUS_CHECK_COND) { 2364 if ((pcsio->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) { 2365 TRM_DPRINTF("trm_RequestSense..................\n"); 2366 trm_RequestSense(pACB, pDCB, pSRB); 2367 return; 2368 } 2369 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2370 pccb->ccb_h.status = CAM_AUTOSNS_VALID | 2371 CAM_SCSI_STATUS_ERROR; 2372 goto ckc_e; 2373 } else if (status == SCSI_STAT_QUEUEFULL) { 2374 bval = (u_int8_t) pDCB->GoingSRBCnt; 2375 bval--; 2376 pDCB->MaxCommand = bval; 2377 trm_RewaitSRB(pDCB, pSRB); 2378 pSRB->AdaptStatus = 0; 2379 pSRB->TargetStatus = 0; 2380 pcsio->scsi_status = SCSI_STAT_QUEUEFULL; 2381 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2382 goto ckc_e; 2383 } else if (status == SCSI_STAT_SEL_TIMEOUT) { 2384 pSRB->AdaptStatus = H_SEL_TIMEOUT; 2385 pSRB->TargetStatus = 0; 2386 pcsio->scsi_status = SCSI_STAT_SEL_TIMEOUT; 2387 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2388 } else if (status == SCSI_STAT_BUSY) { 2389 TRM_DPRINTF("trm: target busy at %s %d\n", 2390 __FILE__, __LINE__); 2391 pcsio->scsi_status = SCSI_STAT_BUSY; 2392 pccb->ccb_h.status = CAM_SCSI_BUSY; 2393 /* The device busy, try again later? */ 2394 } else if (status == SCSI_STAT_RESCONFLICT) { 2395 TRM_DPRINTF("trm: target reserved at %s %d\n", 2396 __FILE__, __LINE__); 2397 pcsio->scsi_status = SCSI_STAT_RESCONFLICT; 2398 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; /*XXX*/ 2399 } else { 2400 pSRB->AdaptStatus = 0; 2401 if (pSRB->RetryCnt) { 2402 pSRB->RetryCnt--; 2403 pSRB->TargetStatus = 0; 2404 pSRB->SRBSGIndex = 0; 2405 pSRB->SRBSGListPointer = (PSEG) 2406 &pSRB->SegmentX[0]; 2407 if (trm_StartSCSI(pACB, pDCB, pSRB)) { 2408 /* 2409 * If trm_StartSCSI return 1 : 2410 * current interrupt status is interrupt 2411 * disreenable 2412 * It's said that SCSI processor has more 2413 * one SRB need to do 2414 */ 2415 trm_RewaitSRB(pDCB, pSRB); 2416 } 2417 return; 2418 } else { 2419 TRM_DPRINTF("trm: driver stuffup at %s %d\n", 2420 __FILE__, __LINE__); 2421 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2422 } 2423 } 2424 } else { 2425 /* 2426 * process initiator status.......................... 2427 * Adapter (initiator) status 2428 */ 2429 status = pSRB->AdaptStatus; 2430 if (status & H_OVER_UNDER_RUN) { 2431 pSRB->TargetStatus = 0; 2432 pccb->ccb_h.status = CAM_DATA_RUN_ERR; 2433 /* Illegal length (over/under run) */ 2434 } else if (pSRB->SRBStatus & PARITY_ERROR) { 2435 TRM_DPRINTF("trm: driver stuffup %s %d\n", 2436 __FILE__, __LINE__); 2437 pDCB->tinfo.goal.period = 0; 2438 pDCB->tinfo.goal.offset = 0; 2439 /* Driver failed to perform operation */ 2440 pccb->ccb_h.status = CAM_UNCOR_PARITY; 2441 } else { 2442 /* no error */ 2443 pSRB->AdaptStatus = 0; 2444 pSRB->TargetStatus = 0; 2445 pccb->ccb_h.status = CAM_REQ_CMP; 2446 /* there is no error, (sense is invalid) */ 2447 } 2448 } 2449 ckc_e: 2450 if (pACB->scan_devices[target_id][target_lun]) { 2451 /* 2452 * if SCSI command in "scan devices" duty 2453 */ 2454 if (pSRB->CmdBlock[0] == TEST_UNIT_READY) 2455 pACB->scan_devices[target_id][target_lun] = 0; 2456 /* SCSI command phase :test unit ready */ 2457 else if (pSRB->CmdBlock[0] == INQUIRY) { 2458 /* 2459 * SCSI command phase :inquiry scsi device data 2460 * (type,capacity,manufacture.... 2461 */ 2462 if (pccb->ccb_h.status == CAM_SEL_TIMEOUT) 2463 goto NO_DEV; 2464 ptr = (PSCSI_INQDATA) pcsio->data_ptr; 2465 /* page fault */ 2466 TRM_DPRINTF("trm_SRBdone..PSCSI_INQDATA:%2x \n", 2467 ptr->DevType); 2468 bval1 = ptr->DevType & SCSI_DEVTYPE; 2469 if (bval1 == SCSI_NODEV) { 2470 NO_DEV: 2471 TRM_DPRINTF("trm_SRBdone NO Device:target_id= %d ,target_lun= %d \n", 2472 target_id, 2473 target_lun); 2474 crit_enter(); 2475 pACB->scan_devices[target_id][target_lun] = 0; 2476 /* no device set scan device flag =0*/ 2477 /* pDCB Q link */ 2478 /* move the head of DCB to tempDCB*/ 2479 pTempDCB=pACB->pLinkDCB; 2480 /* search current DCB for pass link */ 2481 while (pTempDCB->pNextDCB != pDCB) { 2482 pTempDCB = pTempDCB->pNextDCB; 2483 } 2484 /* 2485 * when the current DCB found than connect 2486 * current DCB tail 2487 */ 2488 /* to the DCB tail that before current DCB */ 2489 pTempDCB->pNextDCB = pDCB->pNextDCB; 2490 /* 2491 * if there was only one DCB ,connect his tail 2492 * to his head 2493 */ 2494 if (pACB->pLinkDCB == pDCB) 2495 pACB->pLinkDCB = pTempDCB->pNextDCB; 2496 if (pACB->pDCBRunRobin == pDCB) 2497 pACB->pDCBRunRobin = pTempDCB->pNextDCB; 2498 pACB->DeviceCnt--; 2499 if (pACB->DeviceCnt == 0) { 2500 pACB->pLinkDCB = NULL; 2501 pACB->pDCBRunRobin = NULL; 2502 } 2503 crit_exit(); 2504 } else { 2505 #ifdef trm_DEBUG1 2506 int j; 2507 for (j = 0; j < 28; j++) { 2508 TRM_DPRINTF("ptr=%2x ", 2509 ((u_int8_t *)ptr)[j]); 2510 } 2511 #endif 2512 pDCB->DevType = bval1; 2513 if (bval1 == SCSI_DASD || 2514 bval1 == SCSI_OPTICAL) { 2515 if ((((ptr->Vers & 0x07) >= 2) || 2516 ((ptr->RDF & 0x0F) == 2)) && 2517 (ptr->Flags & SCSI_INQ_CMDQUEUE) && 2518 (pDCB->DevMode & TAG_QUEUING_) && 2519 (pDCB->DevMode & EN_DISCONNECT_)) { 2520 if (pDCB->DevMode & 2521 TAG_QUEUING_) { 2522 pDCB->MaxCommand = 2523 pACB->TagMaxNum; 2524 pDCB->SyncMode |= 2525 EN_TAG_QUEUING; 2526 pDCB->TagMask = 0; 2527 pDCB->tinfo.disc_tag |= 2528 TRM_CUR_TAGENB; 2529 } else { 2530 pDCB->SyncMode |= 2531 EN_ATN_STOP; 2532 pDCB->tinfo.disc_tag &= 2533 ~TRM_CUR_TAGENB; 2534 } 2535 } 2536 } 2537 } 2538 /* pSRB->CmdBlock[0] == INQUIRY */ 2539 } 2540 /* pACB->scan_devices[target_id][target_lun] */ 2541 } 2542 crit_enter(); 2543 /* ReleaseSRB(pDCB, pSRB); */ 2544 if (pSRB == pDCB->pGoingSRB) 2545 pDCB->pGoingSRB = pSRB->pNextSRB; 2546 else { 2547 psrb = pDCB->pGoingSRB; 2548 while (psrb->pNextSRB != pSRB) { 2549 psrb = psrb->pNextSRB; 2550 } 2551 psrb->pNextSRB = pSRB->pNextSRB; 2552 if (pSRB == pDCB->pGoingLastSRB) { 2553 pDCB->pGoingLastSRB = psrb; 2554 } 2555 } 2556 pSRB->pNextSRB = pACB->pFreeSRB; 2557 pACB->pFreeSRB = pSRB; 2558 pDCB->GoingSRBCnt--; 2559 trm_DoWaitingSRB(pACB); 2560 2561 crit_exit(); 2562 /* Notify cmd done */ 2563 xpt_done (pccb); 2564 } 2565 2566 static void 2567 trm_DoingSRB_Done(PACB pACB) 2568 { 2569 PDCB pDCB, pdcb; 2570 PSRB psrb, psrb2; 2571 u_int16_t cnt, i; 2572 union ccb *pccb; 2573 2574 pDCB = pACB->pLinkDCB; 2575 if (pDCB == NULL) 2576 return; 2577 pdcb = pDCB; 2578 do { 2579 cnt = pdcb->GoingSRBCnt; 2580 psrb = pdcb->pGoingSRB; 2581 for (i = 0; i < cnt; i++) { 2582 psrb2 = psrb->pNextSRB; 2583 pccb = psrb->pccb; 2584 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2585 /* ReleaseSRB(pDCB, pSRB); */ 2586 psrb->pNextSRB = pACB->pFreeSRB; 2587 pACB->pFreeSRB = psrb; 2588 xpt_done(pccb); 2589 psrb = psrb2; 2590 } 2591 pdcb->GoingSRBCnt = 0; 2592 pdcb->pGoingSRB = NULL; 2593 pdcb->TagMask = 0; 2594 pdcb = pdcb->pNextDCB; 2595 } 2596 while (pdcb != pDCB); 2597 } 2598 2599 static void 2600 trm_ResetSCSIBus(PACB pACB) 2601 { 2602 crit_enter(); 2603 pACB->ACBFlag |= RESET_DEV; 2604 2605 trm_reg_write16(DO_RSTSCSI,TRMREG_SCSI_CONTROL); 2606 while (!(trm_reg_read16(TRMREG_SCSI_INTSTATUS) & INT_SCSIRESET)); 2607 crit_exit(); 2608 return; 2609 } 2610 2611 static void 2612 trm_ScsiRstDetect(PACB pACB) 2613 { 2614 u_long wlval; 2615 2616 TRM_DPRINTF("trm_ScsiRstDetect \n"); 2617 wlval = 1000; 2618 while (--wlval) 2619 DELAY(1000); 2620 crit_enter(); 2621 trm_reg_write8(STOPDMAXFER,TRMREG_DMA_CONTROL); 2622 2623 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 2624 2625 if (pACB->ACBFlag & RESET_DEV) 2626 pACB->ACBFlag |= RESET_DONE; 2627 else { 2628 pACB->ACBFlag |= RESET_DETECT; 2629 trm_ResetDevParam(pACB); 2630 /* trm_DoingSRB_Done(pACB); ???? */ 2631 trm_RecoverSRB(pACB); 2632 pACB->pActiveDCB = NULL; 2633 pACB->ACBFlag = 0; 2634 trm_DoWaitingSRB(pACB); 2635 } 2636 crit_exit(); 2637 return; 2638 } 2639 2640 static void 2641 trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB) 2642 { 2643 union ccb *pccb; 2644 struct ccb_scsiio *pcsio; 2645 2646 pccb = pSRB->pccb; 2647 pcsio = &pccb->csio; 2648 2649 pSRB->SRBFlag |= AUTO_REQSENSE; 2650 pSRB->Segment0[0] = *((u_long *) &(pSRB->CmdBlock[0])); 2651 pSRB->Segment0[1] = *((u_long *) &(pSRB->CmdBlock[4])); 2652 pSRB->Segment1[0] = (u_long) ((pSRB->ScsiCmdLen << 8) + 2653 pSRB->SRBSGCount); 2654 pSRB->Segment1[1] = pSRB->SRBTotalXferLength; /* ?????????? */ 2655 2656 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2657 pSRB->AdaptStatus = 0; 2658 pSRB->TargetStatus = 0; 2659 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2660 2661 pSRB->SRBTotalXferLength = sizeof(pcsio->sense_data); 2662 pSRB->SgSenseTemp.address = pSRB->SegmentX[0].address; 2663 pSRB->SgSenseTemp.length = pSRB->SegmentX[0].length; 2664 pSRB->SegmentX[0].address = (u_long) vtophys(&pcsio->sense_data); 2665 pSRB->SegmentX[0].length = (u_long) pcsio->sense_len; 2666 pSRB->SRBSGListPointer = &pSRB->SegmentX[0]; 2667 pSRB->SRBSGCount = 1; 2668 pSRB->SRBSGIndex = 0; 2669 2670 *((u_long *) &(pSRB->CmdBlock[0])) = 0x00000003; 2671 pSRB->CmdBlock[1] = pDCB->IdentifyMsg << 5; 2672 *((u_int16_t *) &(pSRB->CmdBlock[4])) = pcsio->sense_len; 2673 pSRB->ScsiCmdLen = 6; 2674 2675 if (trm_StartSCSI(pACB, pDCB, pSRB)) 2676 /* 2677 * If trm_StartSCSI return 1 : 2678 * current interrupt status is interrupt disreenable 2679 * It's said that SCSI processor has more one SRB need to do 2680 */ 2681 trm_RewaitSRB(pDCB, pSRB); 2682 } 2683 2684 static void 2685 trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB) 2686 { 2687 2688 pSRB->MsgCnt = 1; 2689 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2690 } 2691 2692 static void 2693 trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB) 2694 { 2695 2696 pSRB->MsgOutBuf[0] = MSG_ABORT; 2697 trm_EnableMsgOutAbort2(pACB, pSRB); 2698 } 2699 2700 static void 2701 trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit,u_int32_t i,u_int32_t j) 2702 { 2703 PNVRAMTYPE pEEpromBuf; 2704 u_int8_t bval,PeriodIndex; 2705 u_int target_id,target_lun; 2706 PDCB pTempDCB; 2707 2708 target_id = i; 2709 target_lun = j; 2710 2711 crit_enter(); 2712 if (pACB->pLinkDCB == 0) { 2713 pACB->pLinkDCB = pDCB; 2714 /* 2715 * RunRobin impersonate the role 2716 * that let each device had good proportion 2717 * about SCSI command proceeding 2718 */ 2719 pACB->pDCBRunRobin = pDCB; 2720 pDCB->pNextDCB = pDCB; 2721 } else { 2722 pTempDCB=pACB->pLinkDCB; 2723 /* search the last nod of DCB link */ 2724 while (pTempDCB->pNextDCB != pACB->pLinkDCB) 2725 pTempDCB = pTempDCB->pNextDCB; 2726 /* connect current DCB with last DCB tail */ 2727 pTempDCB->pNextDCB = pDCB; 2728 /* connect current DCB tail to this DCB Q head */ 2729 pDCB->pNextDCB=pACB->pLinkDCB; 2730 } 2731 crit_exit(); 2732 2733 pACB->DeviceCnt++; 2734 pDCB->pDCBACB = pACB; 2735 pDCB->TargetID = target_id; 2736 pDCB->TargetLUN = target_lun; 2737 pDCB->pWaitingSRB = NULL; 2738 pDCB->pGoingSRB = NULL; 2739 pDCB->GoingSRBCnt = 0; 2740 pDCB->pActiveSRB = NULL; 2741 pDCB->TagMask = 0; 2742 pDCB->MaxCommand = 1; 2743 pDCB->DCBFlag = 0; 2744 /* $$$$$$$ */ 2745 pEEpromBuf = &trm_eepromBuf[unit]; 2746 pDCB->DevMode = pEEpromBuf->NvramTarget[target_id].NvmTarCfg0; 2747 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 2748 /* $$$$$$$ */ 2749 /* 2750 * disconnect enable ? 2751 */ 2752 if (pDCB->DevMode & NTC_DO_DISCONNECT) { 2753 bval = 0xC0; 2754 pDCB->tinfo.disc_tag |= TRM_USR_DISCENB ; 2755 } else { 2756 bval = 0x80; 2757 pDCB->tinfo.disc_tag &= ~(TRM_USR_DISCENB); 2758 } 2759 bval |= target_lun; 2760 pDCB->IdentifyMsg = bval; 2761 /* $$$$$$$ */ 2762 /* 2763 * tag Qing enable ? 2764 */ 2765 if (pDCB->DevMode & TAG_QUEUING_) { 2766 pDCB->tinfo.disc_tag |= TRM_USR_TAGENB ; 2767 } else 2768 pDCB->tinfo.disc_tag &= ~(TRM_USR_TAGENB); 2769 /* $$$$$$$ */ 2770 /* 2771 * wide nego ,sync nego enable ? 2772 */ 2773 pDCB->SyncPeriod = 0; 2774 pDCB->SyncOffset = 0; 2775 PeriodIndex = pEEpromBuf->NvramTarget[target_id].NvmTarPeriod & 0x07; 2776 pDCB->MaxNegoPeriod = dc395x_trm_clock_period[ PeriodIndex ] ; 2777 pDCB->SyncMode = 0; 2778 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 2779 (pACB->Config & HCC_WIDE_CARD)) 2780 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 2781 /* enable wide nego */ 2782 if (pDCB->DevMode & NTC_DO_SYNC_NEGO) 2783 pDCB->SyncMode |= SYNC_NEGO_ENABLE; 2784 /* enable sync nego */ 2785 /* $$$$$$$ */ 2786 /* 2787 * Fill in tinfo structure. 2788 */ 2789 pDCB->tinfo.user.period = pDCB->MaxNegoPeriod; 2790 pDCB->tinfo.user.offset = (pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 15 : 0; 2791 pDCB->tinfo.user.width = (pDCB->SyncMode & WIDE_NEGO_ENABLE) ? 2792 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT; 2793 2794 pDCB->tinfo.current.period = 0; 2795 pDCB->tinfo.current.offset = 0; 2796 pDCB->tinfo.current.width = MSG_EXT_WDTR_BUS_8_BIT; 2797 } 2798 2799 static void 2800 trm_initSRB(PSRB psrb) 2801 { 2802 2803 psrb->PhysSRB = vtophys(psrb); 2804 } 2805 2806 static void 2807 trm_linkSRB(PACB pACB) 2808 { 2809 u_int16_t i; 2810 2811 for (i = 0; i < MAX_SRB_CNT; i++) { 2812 if (i != MAX_SRB_CNT - 1) 2813 /* 2814 * link all SRB 2815 */ 2816 pACB->SRB_array[i].pNextSRB = &pACB->SRB_array[i+1]; 2817 else 2818 /* 2819 * load NULL to NextSRB of the last SRB 2820 */ 2821 pACB->SRB_array[i].pNextSRB = NULL; 2822 /* 2823 * convert and save physical address of SRB to pSRB->PhysSRB 2824 */ 2825 trm_initSRB((PSRB) &pACB->SRB_array[i]); 2826 } 2827 } 2828 2829 2830 static void 2831 trm_initACB(PACB pACB, u_int16_t unit) 2832 { 2833 PNVRAMTYPE pEEpromBuf; 2834 u_int16_t i,j; 2835 2836 pEEpromBuf = &trm_eepromBuf[unit]; 2837 pACB->max_id = 15; 2838 2839 if (pEEpromBuf->NvramChannelCfg & NAC_SCANLUN) 2840 pACB->max_lun = 7; 2841 else 2842 pACB->max_lun = 0; 2843 2844 TRM_DPRINTF("trm: pACB->max_id= %d pACB->max_lun= %d \n", 2845 pACB->max_id, pACB->max_lun); 2846 2847 pACB->pLinkDCB = NULL; 2848 pACB->pDCBRunRobin = NULL; 2849 pACB->pActiveDCB = NULL; 2850 pACB->pFreeSRB = pACB->SRB_array; 2851 pACB->AdapterUnit = unit; 2852 pACB->AdaptSCSIID = pEEpromBuf->NvramScsiId; 2853 pACB->AdaptSCSILUN = 0; 2854 pACB->DeviceCnt = 0; 2855 pACB->TagMaxNum = 2 << pEEpromBuf->NvramMaxTag ; 2856 pACB->ACBFlag = 0; 2857 /* 2858 * link all device's SRB Q of this adapter 2859 */ 2860 trm_linkSRB(pACB); 2861 /* 2862 * temp SRB for Q tag used or abord command used 2863 */ 2864 pACB->pTmpSRB = &pACB->TmpSRB; 2865 /* 2866 * convert and save physical address of SRB to pSRB->PhysSRB 2867 */ 2868 trm_initSRB(pACB->pTmpSRB); 2869 /* allocate DCB array for scan device */ 2870 for (i = 0; i < (pACB->max_id +1); i++) { 2871 if (pACB->AdaptSCSIID != i) { 2872 for (j = 0; j < (pACB->max_lun +1); j++) { 2873 pACB->scan_devices[i][j] = 1; 2874 pACB->pDCB[i][j]= (PDCB) malloc ( 2875 sizeof (struct _DCB), M_DEVBUF, M_WAITOK); 2876 trm_initDCB(pACB, 2877 pACB->pDCB[i][j], unit, i, j); 2878 TRM_DPRINTF("pDCB= %8x \n", 2879 (u_int)pACB->pDCB[i][j]); 2880 } 2881 } 2882 } 2883 TRM_DPRINTF("sizeof(struct _DCB)= %8x \n",sizeof(struct _DCB)); 2884 TRM_DPRINTF("sizeof(struct _ACB)= %8x \n",sizeof(struct _ACB)); 2885 TRM_DPRINTF("sizeof(struct _SRB)= %8x \n",sizeof(struct _SRB)); 2886 } 2887 2888 static void 2889 TRM_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB) 2890 { 2891 u_int8_t *bpEeprom = (u_int8_t *) pEEpromBuf; 2892 u_int8_t bAddr; 2893 2894 /* Enable SEEPROM */ 2895 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 2896 TRMREG_GEN_CONTROL); 2897 /* 2898 * Write enable 2899 */ 2900 TRM_write_cmd(pACB, 0x04, 0xFF); 2901 trm_reg_write8(0, TRMREG_GEN_NVRAM); 2902 TRM_wait_30us(pACB); 2903 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) { 2904 TRM_set_data(pACB, bAddr, *bpEeprom); 2905 } 2906 /* 2907 * Write disable 2908 */ 2909 TRM_write_cmd(pACB, 0x04, 0x00); 2910 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 2911 TRM_wait_30us(pACB); 2912 /* Disable SEEPROM */ 2913 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 2914 TRMREG_GEN_CONTROL); 2915 return; 2916 } 2917 2918 static void 2919 TRM_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData) 2920 { 2921 int i; 2922 u_int8_t bSendData; 2923 /* 2924 * Send write command & address 2925 */ 2926 2927 TRM_write_cmd(pACB, 0x05, bAddr); 2928 /* 2929 * Write data 2930 */ 2931 for (i = 0; i < 8; i++, bData <<= 1) { 2932 bSendData = NVR_SELECT; 2933 if (bData & 0x80) 2934 /* Start from bit 7 */ 2935 bSendData |= NVR_BITOUT; 2936 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 2937 TRM_wait_30us(pACB); 2938 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 2939 TRM_wait_30us(pACB); 2940 } 2941 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 2942 TRM_wait_30us(pACB); 2943 /* 2944 * Disable chip select 2945 */ 2946 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 2947 TRM_wait_30us(pACB); 2948 trm_reg_write8(NVR_SELECT ,TRMREG_GEN_NVRAM); 2949 TRM_wait_30us(pACB); 2950 /* 2951 * Wait for write ready 2952 */ 2953 while (1) { 2954 trm_reg_write8((NVR_SELECT | NVR_CLOCK), TRMREG_GEN_NVRAM); 2955 TRM_wait_30us(pACB); 2956 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 2957 TRM_wait_30us(pACB); 2958 if (trm_reg_read8(TRMREG_GEN_NVRAM) & NVR_BITIN) { 2959 break; 2960 } 2961 } 2962 /* 2963 * Disable chip select 2964 */ 2965 trm_reg_write8(0, TRMREG_GEN_NVRAM); 2966 return; 2967 } 2968 2969 static void 2970 TRM_read_all(PNVRAMTYPE pEEpromBuf, PACB pACB) 2971 { 2972 u_int8_t *bpEeprom = (u_int8_t*) pEEpromBuf; 2973 u_int8_t bAddr; 2974 2975 /* 2976 * Enable SEEPROM 2977 */ 2978 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 2979 TRMREG_GEN_CONTROL); 2980 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) 2981 *bpEeprom = TRM_get_data(pACB, bAddr); 2982 /* 2983 * Disable SEEPROM 2984 */ 2985 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 2986 TRMREG_GEN_CONTROL); 2987 return; 2988 } 2989 2990 static u_int8_t 2991 TRM_get_data(PACB pACB, u_int8_t bAddr) 2992 { 2993 int i; 2994 u_int8_t bReadData, bData = 0; 2995 /* 2996 * Send read command & address 2997 */ 2998 2999 TRM_write_cmd(pACB, 0x06, bAddr); 3000 3001 for (i = 0; i < 8; i++) { 3002 /* 3003 * Read data 3004 */ 3005 trm_reg_write8((NVR_SELECT | NVR_CLOCK) , TRMREG_GEN_NVRAM); 3006 TRM_wait_30us(pACB); 3007 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 3008 /* 3009 * Get data bit while falling edge 3010 */ 3011 bReadData = trm_reg_read8(TRMREG_GEN_NVRAM); 3012 bData <<= 1; 3013 if (bReadData & NVR_BITIN) { 3014 bData |= 1; 3015 } 3016 TRM_wait_30us(pACB); 3017 } 3018 /* 3019 * Disable chip select 3020 */ 3021 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3022 return (bData); 3023 } 3024 3025 static void 3026 TRM_wait_30us(PACB pACB) 3027 { 3028 3029 /* ScsiPortStallExecution(30); wait 30 us */ 3030 trm_reg_write8(5, TRMREG_GEN_TIMER); 3031 while (!(trm_reg_read8(TRMREG_GEN_STATUS) & GTIMEOUT)); 3032 return; 3033 } 3034 3035 static void 3036 TRM_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr) 3037 { 3038 int i; 3039 u_int8_t bSendData; 3040 3041 for (i = 0; i < 3; i++, bCmd <<= 1) { 3042 /* 3043 * Program SB+OP code 3044 */ 3045 bSendData = NVR_SELECT; 3046 if (bCmd & 0x04) 3047 bSendData |= NVR_BITOUT; 3048 /* start from bit 2 */ 3049 trm_reg_write8(bSendData, TRMREG_GEN_NVRAM); 3050 TRM_wait_30us(pACB); 3051 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3052 TRM_wait_30us(pACB); 3053 } 3054 for (i = 0; i < 7; i++, bAddr <<= 1) { 3055 /* 3056 * Program address 3057 */ 3058 bSendData = NVR_SELECT; 3059 if (bAddr & 0x40) 3060 /* Start from bit 6 */ 3061 bSendData |= NVR_BITOUT; 3062 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 3063 TRM_wait_30us(pACB); 3064 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3065 TRM_wait_30us(pACB); 3066 } 3067 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 3068 TRM_wait_30us(pACB); 3069 } 3070 3071 static void 3072 trm_check_eeprom(PNVRAMTYPE pEEpromBuf, PACB pACB) 3073 { 3074 u_int16_t *wpEeprom = (u_int16_t *) pEEpromBuf; 3075 u_int16_t wAddr, wCheckSum; 3076 u_long dAddr, *dpEeprom; 3077 3078 TRM_read_all(pEEpromBuf,pACB); 3079 wCheckSum = 0; 3080 for (wAddr = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3081 wAddr < 64; wAddr++, wpEeprom++) { 3082 wCheckSum += *wpEeprom; 3083 } 3084 if (wCheckSum != 0x1234) { 3085 /* 3086 * Checksum error, load default 3087 */ 3088 pEEpromBuf->NvramSubVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3089 pEEpromBuf->NvramSubVendorID[1] = 3090 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3091 pEEpromBuf->NvramSubSysID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3092 pEEpromBuf->NvramSubSysID[1] = 3093 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3094 pEEpromBuf->NvramSubClass = 0x00; 3095 pEEpromBuf->NvramVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3096 pEEpromBuf->NvramVendorID[1] = 3097 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3098 pEEpromBuf->NvramDeviceID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3099 pEEpromBuf->NvramDeviceID[1] = 3100 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3101 pEEpromBuf->NvramReserved = 0x00; 3102 3103 for (dAddr = 0, dpEeprom = (u_long *) pEEpromBuf->NvramTarget; 3104 dAddr < 16; dAddr++, dpEeprom++) { 3105 *dpEeprom = 0x00000077; 3106 /* NvmTarCfg3,NvmTarCfg2,NvmTarPeriod,NvmTarCfg0 */ 3107 } 3108 3109 *dpEeprom++ = 0x04000F07; 3110 /* NvramMaxTag,NvramDelayTime,NvramChannelCfg,NvramScsiId */ 3111 *dpEeprom++ = 0x00000015; 3112 /* NvramReserved1,NvramBootLun,NvramBootTarget,NvramReserved0 */ 3113 for (dAddr = 0; dAddr < 12; dAddr++, dpEeprom++) 3114 *dpEeprom = 0x00; 3115 pEEpromBuf->NvramCheckSum = 0x00; 3116 for (wAddr = 0, wCheckSum = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3117 wAddr < 63; wAddr++, wpEeprom++) 3118 wCheckSum += *wpEeprom; 3119 *wpEeprom = 0x1234 - wCheckSum; 3120 TRM_write_all(pEEpromBuf,pACB); 3121 } 3122 return; 3123 } 3124 static int 3125 trm_initAdapter(PACB pACB, u_int16_t unit, device_t pci_config_id) 3126 { 3127 PNVRAMTYPE pEEpromBuf; 3128 u_int16_t wval; 3129 u_int8_t bval; 3130 3131 pEEpromBuf = &trm_eepromBuf[unit]; 3132 3133 /* 250ms selection timeout */ 3134 trm_reg_write8(SEL_TIMEOUT, TRMREG_SCSI_TIMEOUT); 3135 /* Mask all the interrupt */ 3136 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 3137 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 3138 /* Reset SCSI module */ 3139 trm_reg_write16(DO_RSTMODULE, TRMREG_SCSI_CONTROL); 3140 /* program configuration 0 */ 3141 pACB->Config = HCC_AUTOTERM | HCC_PARITY; 3142 if (trm_reg_read8(TRMREG_GEN_STATUS) & WIDESCSI) 3143 pACB->Config |= HCC_WIDE_CARD; 3144 if (pEEpromBuf->NvramChannelCfg & NAC_POWERON_SCSI_RESET) 3145 pACB->Config |= HCC_SCSI_RESET; 3146 if (pACB->Config & HCC_PARITY) 3147 bval = PHASELATCH | INITIATOR | BLOCKRST | PARITYCHECK; 3148 else 3149 bval = PHASELATCH | INITIATOR | BLOCKRST ; 3150 trm_reg_write8(bval,TRMREG_SCSI_CONFIG0); 3151 /* program configuration 1 */ 3152 trm_reg_write8(0x13, TRMREG_SCSI_CONFIG1); 3153 /* program Host ID */ 3154 bval = pEEpromBuf->NvramScsiId; 3155 trm_reg_write8(bval, TRMREG_SCSI_HOSTID); 3156 /* set ansynchronous transfer */ 3157 trm_reg_write8(0x00, TRMREG_SCSI_OFFSET); 3158 /* Trun LED control off*/ 3159 wval = trm_reg_read16(TRMREG_GEN_CONTROL) & 0x7F; 3160 trm_reg_write16(wval, TRMREG_GEN_CONTROL); 3161 /* DMA config */ 3162 wval = trm_reg_read16(TRMREG_DMA_CONFIG) | DMA_ENHANCE; 3163 trm_reg_write16(wval, TRMREG_DMA_CONFIG); 3164 /* Clear pending interrupt status */ 3165 trm_reg_read8(TRMREG_SCSI_INTSTATUS); 3166 /* Enable SCSI interrupt */ 3167 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 3168 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 3169 return (0); 3170 } 3171 3172 static PACB 3173 trm_init(u_int16_t unit, device_t pci_config_id) 3174 { 3175 PACB pACB; 3176 int rid = PCIR_MAPS; 3177 3178 pACB = (PACB) device_get_softc(pci_config_id); 3179 if (!pACB) { 3180 printf("trm%d: cannot allocate ACB !\n", unit); 3181 return (NULL); 3182 } 3183 bzero (pACB, sizeof (struct _ACB)); 3184 pACB->iores = bus_alloc_resource(pci_config_id, SYS_RES_IOPORT, 3185 &rid, 0, ~0, 1, RF_ACTIVE); 3186 if (pACB->iores == NULL) { 3187 printf("trm_init: bus_alloc_resource failed!\n"); 3188 return (NULL); 3189 } 3190 pACB->tag = rman_get_bustag(pACB->iores); 3191 pACB->bsh = rman_get_bushandle(pACB->iores); 3192 if (bus_dma_tag_create(/*parent_dmat*/ NULL, 3193 /*alignment*/ 1, 3194 /*boundary*/ 0, 3195 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 3196 /*highaddr*/ BUS_SPACE_MAXADDR, 3197 /*filter*/ NULL, 3198 /*filterarg*/ NULL, 3199 /*maxsize*/ MAXBSIZE, 3200 /*nsegments*/ TRM_NSEG, 3201 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3202 /*flags*/ BUS_DMA_ALLOCNOW, 3203 &pACB->buffer_dmat) != 0) 3204 goto bad; 3205 trm_check_eeprom(&trm_eepromBuf[unit],pACB); 3206 trm_initACB(pACB, unit); 3207 if (trm_initAdapter(pACB, unit, pci_config_id)) { 3208 printf("trm_initAdapter: initial ERROR\n"); 3209 goto bad; 3210 } 3211 return (pACB); 3212 bad: 3213 if (pACB->iores) 3214 bus_release_resource(pci_config_id, SYS_RES_IOPORT, PCIR_MAPS, 3215 pACB->iores); 3216 if (pACB->buffer_dmat) 3217 bus_dma_tag_destroy(pACB->buffer_dmat); 3218 return (NULL); 3219 } 3220 3221 static int 3222 trm_attach(device_t pci_config_id) 3223 { 3224 struct cam_devq *device_Q; 3225 u_long device_id; 3226 PACB pACB = 0; 3227 int rid = 0; 3228 int unit = device_get_unit(pci_config_id); 3229 3230 device_id = pci_get_devid(pci_config_id); 3231 /* 3232 * These cards do not allow memory mapped accesses 3233 */ 3234 if (device_id == PCI_DEVICEID_TRMS1040) { 3235 if ((pACB=trm_init((u_int16_t) unit, 3236 pci_config_id)) == NULL) { 3237 printf("trm%d: trm_init error!\n",unit); 3238 return (ENXIO); 3239 } 3240 } else 3241 return (ENXIO); 3242 /* After setting up the adapter, map our interrupt */ 3243 /* 3244 * Now let the CAM generic SCSI layer find the SCSI devices on the bus 3245 * start queue to reset to the idle loop. 3246 * Create device queue of SIM(s) 3247 * (MAX_START_JOB - 1) : max_sim_transactions 3248 */ 3249 pACB->irq = bus_alloc_resource(pci_config_id, SYS_RES_IRQ, &rid, 0, 3250 ~0, 1, RF_SHAREABLE | RF_ACTIVE); 3251 if (pACB->irq == NULL || 3252 bus_setup_intr(pci_config_id, pACB->irq, 3253 0, trm_Interrupt, pACB, 3254 &pACB->ih, NULL)) { 3255 printf("trm%d: register Interrupt handler error!\n", unit); 3256 goto bad; 3257 } 3258 device_Q = cam_simq_alloc(MAX_START_JOB); 3259 if (device_Q == NULL){ 3260 printf("trm%d: device_Q == NULL !\n",unit); 3261 goto bad; 3262 } 3263 /* 3264 * Now tell the generic SCSI layer 3265 * about our bus. 3266 * If this is the xpt layer creating a sim, then it's OK 3267 * to wait for an allocation. 3268 * XXX Should we pass in a flag to indicate that wait is OK? 3269 * 3270 * SIM allocation 3271 * 3272 * SCSI Interface Modules 3273 * The sim driver creates a sim for each controller. The sim device 3274 * queue is separately created in order to allow resource sharing betwee 3275 * sims. For instance, a driver may create one sim for each channel of 3276 * a multi-channel controller and use the same queue for each channel. 3277 * In this way, the queue resources are shared across all the channels 3278 * of the multi-channel controller. 3279 * trm_action : sim_action_func 3280 * trm_poll : sim_poll_func 3281 * "trm" : sim_name ,if sim_name = "xpt" ..M_DEVBUF,M_WAITOK 3282 * pACB : *softc if sim_name <> "xpt" ..M_DEVBUF,M_NOWAIT 3283 * pACB->unit : unit 3284 * 1 : max_dev_transactions 3285 * MAX_TAGS : max_tagged_dev_transactions 3286 * 3287 * *******Construct our first channel SIM entry 3288 */ 3289 pACB->psim = cam_sim_alloc(trm_action, 3290 trm_poll, 3291 "trm", 3292 pACB, 3293 unit, 3294 1, 3295 MAX_TAGS_CMD_QUEUE, 3296 device_Q); 3297 cam_simq_release(device_Q); /* SIM allocate fault*/ 3298 if (pACB->psim == NULL) { 3299 printf("trm%d: SIM allocate fault !\n",unit); 3300 goto bad; 3301 } 3302 if (xpt_bus_register(pACB->psim, 0) != CAM_SUCCESS) { 3303 printf("trm%d: xpt_bus_register fault !\n",unit); 3304 goto bad; 3305 } 3306 if (xpt_create_path(&pACB->ppath, 3307 NULL, 3308 cam_sim_path(pACB->psim), 3309 CAM_TARGET_WILDCARD, 3310 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 3311 printf("trm%d: xpt_create_path fault !\n",unit); 3312 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3313 goto bad; 3314 /* 3315 * cam_sim_free(pACB->psim, TRUE); free_devq 3316 * pACB->psim = NULL; 3317 */ 3318 return (ENXIO); 3319 } 3320 return (0); 3321 bad: 3322 if (pACB->iores) 3323 bus_release_resource(pci_config_id, SYS_RES_IOPORT, PCIR_MAPS, 3324 pACB->iores); 3325 if (pACB->buffer_dmat) 3326 bus_dma_tag_destroy(pACB->buffer_dmat); 3327 if (pACB->ih) 3328 bus_teardown_intr(pci_config_id, pACB->irq, pACB->ih); 3329 if (pACB->irq) 3330 bus_release_resource(pci_config_id, SYS_RES_IRQ, 0, pACB->irq); 3331 if (pACB->psim) 3332 cam_sim_free(pACB->psim); 3333 3334 return (ENXIO); 3335 3336 } 3337 3338 /* 3339 * pci_device 3340 * trm_probe (device_t tag, pcidi_t type) 3341 * 3342 */ 3343 static int 3344 trm_probe(device_t tag) 3345 { 3346 3347 if (pci_get_devid(tag) == PCI_DEVICEID_TRMS1040) { 3348 device_set_desc(tag, 3349 "Tekram DC395U/UW/F DC315/U Fast20 Wide SCSI Adapter"); 3350 return (0); 3351 } else 3352 return (ENXIO); 3353 } 3354 3355 static int 3356 trm_detach(device_t dev) 3357 { 3358 PACB pACB = device_get_softc(dev); 3359 3360 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS, pACB->iores); 3361 bus_dma_tag_destroy(pACB->buffer_dmat); 3362 bus_teardown_intr(dev, pACB->irq, pACB->ih); 3363 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq); 3364 xpt_async(AC_LOST_DEVICE, pACB->ppath, NULL); 3365 xpt_free_path(pACB->ppath); 3366 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3367 cam_sim_free(pACB->psim); 3368 return (0); 3369 } 3370 static device_method_t trm_methods[] = { 3371 /* Device interface */ 3372 DEVMETHOD(device_probe, trm_probe), 3373 DEVMETHOD(device_attach, trm_attach), 3374 DEVMETHOD(device_detach, trm_detach), 3375 { 0, 0 } 3376 }; 3377 3378 static driver_t trm_driver = { 3379 "trm", trm_methods, sizeof(struct _ACB) 3380 }; 3381 3382 static devclass_t trm_devclass; 3383 DRIVER_MODULE(trm, pci, trm_driver, trm_devclass, 0, 0); 3384