1 /* 2 * O.S : FreeBSD CAM 3 * FILE NAME : trm.c 4 * BY : C.L. Huang (ching@tekram.com.tw) 5 * Erich Chen (erich@tekram.com.tw) 6 * Description: Device Driver for Tekram DC395U/UW/F ,DC315/U 7 * PCI SCSI Bus Master Host Adapter 8 * (SCSI chip set used Tekram ASIC TRM-S1040) 9 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. 10 */ 11 12 /* 13 * HISTORY: 14 * 15 * REV# DATE NAME DESCRIPTION 16 * 1.05 05/01/1999 ERICH CHEN First released for 3.x.x (CAM) 17 * 1.06 07/29/1999 ERICH CHEN Modify for NEW PCI 18 * 1.07 12/12/1999 ERICH CHEN Modify for 3.3.x ,DCB no free 19 * 1.08 06/12/2000 ERICH CHEN Modify for 4.x.x 20 */ 21 22 /* 23 * 24 * 25 * Redistribution and use in source and binary forms, with or without 26 * modification, are permitted provided that the following conditions 27 * are met: 28 * 1. Redistributions of source code must retain the above copyright 29 * notice, this list of conditions and the following disclaimer. 30 * 2. Redistributions in binary form must reproduce the above copyright 31 * notice, this list of conditions and the following disclaimer in the 32 * documentation and/or other materials provided with the distribution. 33 * 3. The name of the author may not be used to endorse or promote products 34 * derived from this software without specific prior written permission. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 37 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 38 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 39 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 40 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 41 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 42 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 43 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 44 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 45 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 46 * 47 * $FreeBSD: src/sys/dev/trm/trm.c,v 1.2.2.2 2002/12/19 20:34:45 cognet Exp $ 48 * $DragonFly: src/sys/dev/disk/trm/trm.c,v 1.15 2007/12/23 07:00:56 pavalos Exp $ 49 */ 50 51 /* 52 * Imported into FreeBSD source repository, and updated to compile under 53 * FreeBSD-3.0-DEVELOPMENT, by Stefan Esser <se@FreeBSD.Org>, 1996-12-17 54 */ 55 56 /* 57 * Updated to compile under FreeBSD 5.0-CURRENT by Olivier Houchard 58 * <doginou@ci0.org>, 2002-03-04 59 */ 60 61 #include <sys/param.h> 62 63 #include <sys/systm.h> 64 #include <sys/malloc.h> 65 #include <sys/queue.h> 66 #if defined(__FreeBSD__) && __FreeBSD_version >= 500000 67 #include <sys/bio.h> 68 #endif 69 #include <sys/buf.h> 70 #include <sys/bus.h> 71 #include <sys/kernel.h> 72 #include <sys/thread2.h> 73 74 #include <vm/vm.h> 75 #include <vm/pmap.h> 76 77 #include <bus/pci/pcivar.h> 78 #include <bus/pci/pcireg.h> 79 #include <machine/clock.h> 80 #include <sys/rman.h> 81 82 #include <bus/cam/cam.h> 83 #include <bus/cam/cam_ccb.h> 84 #include <bus/cam/cam_sim.h> 85 #include <bus/cam/cam_xpt_sim.h> 86 #include <bus/cam/cam_debug.h> 87 88 #include <bus/cam/scsi/scsi_all.h> 89 90 #include "trm.h" 91 92 #define trm_reg_read8(reg) bus_space_read_1(pACB->tag, pACB->bsh, reg) 93 #define trm_reg_read16(reg) bus_space_read_2(pACB->tag, pACB->bsh, reg) 94 #define trm_reg_read32(reg) bus_space_read_4(pACB->tag, pACB->bsh, reg) 95 #define trm_reg_write8(value,reg) bus_space_write_1(pACB->tag, pACB->bsh,\ 96 reg, value) 97 #define trm_reg_write16(value,reg) bus_space_write_2(pACB->tag, pACB->bsh,\ 98 reg, value) 99 #define trm_reg_write32(value,reg) bus_space_write_4(pACB->tag, pACB->bsh,\ 100 reg, value) 101 102 #define PCI_Vendor_ID_TEKRAM 0x1DE1 103 #define PCI_Device_ID_TRM_S1040 0x0391 104 #define PCI_DEVICEID_TRMS1040 0x03911DE1 105 106 #ifdef trm_DEBUG1 107 #define TRM_DPRINTF(fmt, arg...) kprintf("trm: " fmt, ##arg) 108 #else 109 #define TRM_DPRINTF(fmt, arg...) {} 110 #endif /* TRM_DEBUG */ 111 112 static void trm_check_eeprom(PNVRAMTYPE pEEpromBuf,PACB pACB); 113 static void TRM_read_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 114 static u_int8_t TRM_get_data(PACB pACB, u_int8_t bAddr); 115 static void TRM_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 116 static void TRM_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData); 117 static void TRM_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr); 118 static void TRM_wait_30us(PACB pACB); 119 120 static void trm_Interrupt(void *vpACB); 121 static void trm_DataOutPhase0(PACB pACB, PSRB pSRB, 122 u_int8_t * pscsi_status); 123 static void trm_DataInPhase0(PACB pACB, PSRB pSRB, 124 u_int8_t * pscsi_status); 125 static void trm_CommandPhase0(PACB pACB, PSRB pSRB, 126 u_int8_t * pscsi_status); 127 static void trm_StatusPhase0(PACB pACB, PSRB pSRB, 128 u_int8_t * pscsi_status); 129 static void trm_MsgOutPhase0(PACB pACB, PSRB pSRB, 130 u_int8_t * pscsi_status); 131 static void trm_MsgInPhase0(PACB pACB, PSRB pSRB, 132 u_int8_t * pscsi_status); 133 static void trm_DataOutPhase1(PACB pACB, PSRB pSRB, 134 u_int8_t * pscsi_status); 135 static void trm_DataInPhase1(PACB pACB, PSRB pSRB, 136 u_int8_t * pscsi_status); 137 static void trm_CommandPhase1(PACB pACB, PSRB pSRB, 138 u_int8_t * pscsi_status); 139 static void trm_StatusPhase1(PACB pACB, PSRB pSRB, 140 u_int8_t * pscsi_status); 141 static void trm_MsgOutPhase1(PACB pACB, PSRB pSRB, 142 u_int8_t * pscsi_status); 143 static void trm_MsgInPhase1(PACB pACB, PSRB pSRB, 144 u_int8_t * pscsi_status); 145 static void trm_Nop0(PACB pACB, PSRB pSRB, u_int8_t * pscsi_status); 146 static void trm_Nop1(PACB pACB, PSRB pSRB, u_int8_t * pscsi_status); 147 static void trm_SetXferRate(PACB pACB, PSRB pSRB,PDCB pDCB); 148 static void trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir); 149 static void trm_Disconnect(PACB pACB); 150 static void trm_Reselect(PACB pACB); 151 static void trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB); 152 static void trm_DoingSRB_Done(PACB pACB); 153 static void trm_ScsiRstDetect(PACB pACB); 154 static void trm_ResetSCSIBus(PACB pACB); 155 static void trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB); 156 static void trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB); 157 static void trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB); 158 static void trm_SendSRB(PACB pACB, PSRB pSRB); 159 static int trm_probe(device_t tag); 160 static int trm_attach(device_t tag); 161 static void trm_reset(PACB pACB); 162 163 static u_int16_t trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB); 164 165 static int trm_initAdapter(PACB pACB, u_int16_t unit, 166 device_t pci_config_id); 167 static void trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit, 168 u_int32_t i, u_int32_t j); 169 static void trm_initSRB(PSRB psrb); 170 static void trm_linkSRB(PACB pACB); 171 static void trm_initACB(PACB pACB, u_int16_t unit); 172 /* CAM SIM entry points */ 173 #define ccb_trmsrb_ptr spriv_ptr0 174 #define ccb_trmacb_ptr spriv_ptr1 175 static void trm_action(struct cam_sim *psim, union ccb *pccb); 176 static void trm_poll(struct cam_sim *psim); 177 178 179 static void * trm_SCSI_phase0[] = { 180 trm_DataOutPhase0, /* phase:0 */ 181 trm_DataInPhase0, /* phase:1 */ 182 trm_CommandPhase0, /* phase:2 */ 183 trm_StatusPhase0, /* phase:3 */ 184 trm_Nop0, /* phase:4 */ 185 trm_Nop1, /* phase:5 */ 186 trm_MsgOutPhase0, /* phase:6 */ 187 trm_MsgInPhase0, /* phase:7 */ 188 }; 189 190 /* 191 * 192 * stateV = (void *) trm_SCSI_phase1[phase] 193 * 194 */ 195 static void * trm_SCSI_phase1[] = { 196 trm_DataOutPhase1, /* phase:0 */ 197 trm_DataInPhase1, /* phase:1 */ 198 trm_CommandPhase1, /* phase:2 */ 199 trm_StatusPhase1, /* phase:3 */ 200 trm_Nop0, /* phase:4 */ 201 trm_Nop1, /* phase:5 */ 202 trm_MsgOutPhase1, /* phase:6 */ 203 trm_MsgInPhase1, /* phase:7 */ 204 }; 205 206 207 NVRAMTYPE trm_eepromBuf[MAX_ADAPTER_NUM]; 208 /* 209 *Fast20: 000 50ns, 20.0 Mbytes/s 210 * 001 75ns, 13.3 Mbytes/s 211 * 010 100ns, 10.0 Mbytes/s 212 * 011 125ns, 8.0 Mbytes/s 213 * 100 150ns, 6.6 Mbytes/s 214 * 101 175ns, 5.7 Mbytes/s 215 * 110 200ns, 5.0 Mbytes/s 216 * 111 250ns, 4.0 Mbytes/s 217 * 218 *Fast40: 000 25ns, 40.0 Mbytes/s 219 * 001 50ns, 20.0 Mbytes/s 220 * 010 75ns, 13.3 Mbytes/s 221 * 011 100ns, 10.0 Mbytes/s 222 * 100 125ns, 8.0 Mbytes/s 223 * 101 150ns, 6.6 Mbytes/s 224 * 110 175ns, 5.7 Mbytes/s 225 * 111 200ns, 5.0 Mbytes/s 226 */ 227 /* real period: */ 228 u_int8_t dc395x_trm_clock_period[] = { 229 12,/* 48 ns 20 MB/sec */ 230 18,/* 72 ns 13.3 MB/sec */ 231 25,/* 100 ns 10.0 MB/sec */ 232 31,/* 124 ns 8.0 MB/sec */ 233 37,/* 148 ns 6.6 MB/sec */ 234 43,/* 172 ns 5.7 MB/sec */ 235 50,/* 200 ns 5.0 MB/sec */ 236 62 /* 248 ns 4.0 MB/sec */ 237 }; 238 239 u_int8_t dc395x_trm_tinfo_sync_period[] = { 240 12,/* 20.0 MB/sec */ 241 18,/* 13.3 MB/sec */ 242 25,/* 10.0 MB/sec */ 243 31,/* 8.0 MB/sec */ 244 37,/* 6.6 MB/sec */ 245 43,/* 5.7 MB/sec */ 246 50,/* 5.0 MB/sec */ 247 62,/* 4.0 MB/sec */ 248 }; 249 250 static PSRB 251 trm_GetSRB(PACB pACB) 252 { 253 PSRB pSRB; 254 255 crit_enter(); 256 pSRB = pACB->pFreeSRB; 257 if (pSRB) { 258 pACB->pFreeSRB = pSRB->pNextSRB; 259 pSRB->pNextSRB = NULL; 260 } 261 crit_exit(); 262 return (pSRB); 263 } 264 265 static void 266 trm_RewaitSRB0(PDCB pDCB, PSRB pSRB) 267 { 268 PSRB psrb1; 269 270 crit_enter(); 271 if ((psrb1 = pDCB->pWaitingSRB)) { 272 pSRB->pNextSRB = psrb1; 273 pDCB->pWaitingSRB = pSRB; 274 } else { 275 pSRB->pNextSRB = NULL; 276 pDCB->pWaitingSRB = pSRB; 277 pDCB->pWaitLastSRB = pSRB; 278 } 279 crit_exit(); 280 } 281 282 static void 283 trm_RewaitSRB(PDCB pDCB, PSRB pSRB) 284 { 285 PSRB psrb1; 286 u_int8_t bval; 287 288 crit_enter(); 289 pDCB->GoingSRBCnt--; 290 psrb1 = pDCB->pGoingSRB; 291 if (pSRB == psrb1) 292 pDCB->pGoingSRB = psrb1->pNextSRB; 293 else { 294 while (pSRB != psrb1->pNextSRB) 295 psrb1 = psrb1->pNextSRB; 296 psrb1->pNextSRB = pSRB->pNextSRB; 297 if (pSRB == pDCB->pGoingLastSRB) 298 pDCB->pGoingLastSRB = psrb1; 299 } 300 if ((psrb1 = pDCB->pWaitingSRB)) { 301 pSRB->pNextSRB = psrb1; 302 pDCB->pWaitingSRB = pSRB; 303 } else { 304 pSRB->pNextSRB = NULL; 305 pDCB->pWaitingSRB = pSRB; 306 pDCB->pWaitLastSRB = pSRB; 307 } 308 bval = pSRB->TagNumber; 309 pDCB->TagMask &= (~(1 << bval)); /* Free TAG number */ 310 crit_exit(); 311 } 312 313 static void 314 trm_DoWaitingSRB(PACB pACB) 315 { 316 PDCB ptr, ptr1; 317 PSRB pSRB; 318 319 crit_enter(); 320 if (!(pACB->pActiveDCB) && 321 !(pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 322 ptr = pACB->pDCBRunRobin; 323 if (!ptr) { 324 ptr = pACB->pLinkDCB; 325 pACB->pDCBRunRobin = ptr; 326 } 327 ptr1 = ptr; 328 for (;ptr1 ;) { 329 pACB->pDCBRunRobin = ptr1->pNextDCB; 330 if (!(ptr1->MaxCommand > ptr1->GoingSRBCnt) 331 || !(pSRB = ptr1->pWaitingSRB)) { 332 if (pACB->pDCBRunRobin == ptr) 333 break; 334 ptr1 = ptr1->pNextDCB; 335 } else { 336 if (!trm_StartSCSI(pACB, ptr1, pSRB)) { 337 /* 338 * If trm_StartSCSI return 0 : 339 * current interrupt status is interrupt enable 340 * It's said that SCSI processor is unoccupied 341 */ 342 ptr1->GoingSRBCnt++; 343 if (ptr1->pWaitLastSRB == pSRB) { 344 ptr1->pWaitingSRB = NULL; 345 ptr1->pWaitLastSRB = NULL; 346 } else 347 ptr1->pWaitingSRB = pSRB->pNextSRB; 348 pSRB->pNextSRB = NULL; 349 if (ptr1->pGoingSRB) 350 ptr1->pGoingLastSRB->pNextSRB = pSRB; 351 else 352 ptr1->pGoingSRB = pSRB; 353 ptr1->pGoingLastSRB = pSRB; 354 } 355 break; 356 } 357 } 358 } 359 crit_exit(); 360 return; 361 } 362 363 static void 364 trm_SRBwaiting(PDCB pDCB, PSRB pSRB) 365 { 366 367 if (pDCB->pWaitingSRB) { 368 pDCB->pWaitLastSRB->pNextSRB = pSRB; 369 pDCB->pWaitLastSRB = pSRB; 370 pSRB->pNextSRB = NULL; 371 } else { 372 pDCB->pWaitingSRB = pSRB; 373 pDCB->pWaitLastSRB = pSRB; 374 } 375 } 376 377 static void 378 trm_ExecuteSRB(void *arg, bus_dma_segment_t *dm_segs, int nseg, int vp) 379 { 380 PACB pACB; 381 PSRB pSRB; 382 union ccb *ccb; 383 u_long totalxferlen=0; 384 385 pSRB = (PSRB)arg; 386 ccb = pSRB->pccb; 387 pACB = (PACB)ccb->ccb_h.ccb_trmacb_ptr; 388 TRM_DPRINTF("trm_ExecuteSRB..........\n"); 389 if (nseg != 0) { 390 PSEG psg; 391 bus_dma_segment_t *end_seg; 392 bus_dmasync_op_t op; 393 394 /* Copy the segments into our SG list */ 395 end_seg = dm_segs + nseg; 396 psg = (PSEG) &pSRB->SegmentX[0]; 397 pSRB->SRBSGListPointer= psg; 398 while (dm_segs < end_seg) { 399 psg->address = vp?(u_long)vtophys(dm_segs->ds_addr) 400 :(u_long)dm_segs->ds_addr; 401 psg->length = (u_long)dm_segs->ds_len; 402 totalxferlen += dm_segs->ds_len; 403 psg++; 404 dm_segs++; 405 } 406 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 407 op = BUS_DMASYNC_PREREAD; 408 } else { 409 op = BUS_DMASYNC_PREWRITE; 410 } 411 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 412 } 413 pSRB->RetryCnt = 0; 414 pSRB->SRBTotalXferLength=totalxferlen; 415 pSRB->SRBSGCount = nseg; 416 pSRB->SRBSGIndex = 0; 417 pSRB->AdaptStatus = 0; 418 pSRB->TargetStatus = 0; 419 pSRB->MsgCnt = 0; 420 pSRB->SRBStatus = 0; 421 pSRB->SRBFlag = 0; 422 pSRB->SRBState = 0; 423 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 424 425 crit_enter(); 426 if (ccb->ccb_h.status != CAM_REQ_INPROG) { 427 if (nseg != 0) 428 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 429 pSRB->pNextSRB = pACB->pFreeSRB; 430 pACB->pFreeSRB = pSRB; 431 xpt_done(ccb); 432 crit_exit(); 433 return; 434 } 435 ccb->ccb_h.status |= CAM_SIM_QUEUED; 436 #if 0 437 /* XXX Need a timeout handler */ 438 callout_reset(&ccb->ccb_h.timeout_ch, (ccb->ccb_h.timeout * hz) / 1000, 439 trmtimeout, srb); 440 #endif 441 trm_SendSRB(pACB, pSRB); 442 crit_exit(); 443 return; 444 } 445 446 static void 447 trm_SendSRB(PACB pACB, PSRB pSRB) 448 { 449 PDCB pDCB; 450 451 crit_enter(); 452 pDCB = pSRB->pSRBDCB; 453 if (!(pDCB->MaxCommand > pDCB->GoingSRBCnt) || (pACB->pActiveDCB) 454 || (pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 455 TRM_DPRINTF("pDCB->MaxCommand=%d \n",pDCB->MaxCommand); 456 TRM_DPRINTF("pDCB->GoingSRBCnt=%d \n",pDCB->GoingSRBCnt); 457 TRM_DPRINTF("pACB->pActiveDCB=%8x \n",(u_int)pACB->pActiveDCB); 458 TRM_DPRINTF("pACB->ACBFlag=%x \n",pACB->ACBFlag); 459 trm_SRBwaiting(pDCB, pSRB); 460 goto SND_EXIT; 461 } 462 463 if (pDCB->pWaitingSRB) { 464 trm_SRBwaiting(pDCB, pSRB); 465 pSRB = pDCB->pWaitingSRB; 466 pDCB->pWaitingSRB = pSRB->pNextSRB; 467 pSRB->pNextSRB = NULL; 468 } 469 470 if (!trm_StartSCSI(pACB, pDCB, pSRB)) { 471 /* 472 * If trm_StartSCSI return 0 : 473 * current interrupt status is interrupt enable 474 * It's said that SCSI processor is unoccupied 475 */ 476 pDCB->GoingSRBCnt++; /* stack waiting SRB*/ 477 if (pDCB->pGoingSRB) { 478 pDCB->pGoingLastSRB->pNextSRB = pSRB; 479 pDCB->pGoingLastSRB = pSRB; 480 } else { 481 pDCB->pGoingSRB = pSRB; 482 pDCB->pGoingLastSRB = pSRB; 483 } 484 } else { 485 /* 486 * If trm_StartSCSI return 1 : 487 * current interrupt status is interrupt disreenable 488 * It's said that SCSI processor has more one SRB need to do 489 */ 490 trm_RewaitSRB0(pDCB, pSRB); 491 } 492 SND_EXIT: 493 crit_exit(); 494 /* 495 * enable interrupt 496 */ 497 return; 498 } 499 500 501 static void 502 trm_action(struct cam_sim *psim, union ccb *pccb) 503 { 504 PACB pACB; 505 u_int target_id,target_lun; 506 507 CAM_DEBUG(pccb->ccb_h.path, CAM_DEBUG_TRACE, ("trm_action\n")); 508 509 pACB = (PACB) cam_sim_softc(psim); 510 target_id = pccb->ccb_h.target_id; 511 target_lun = pccb->ccb_h.target_lun; 512 513 switch (pccb->ccb_h.func_code) { 514 case XPT_NOOP: 515 TRM_DPRINTF(" XPT_NOOP \n"); 516 pccb->ccb_h.status = CAM_REQ_INVALID; 517 xpt_done(pccb); 518 break; 519 /* 520 * Execute the requested I/O operation 521 */ 522 case XPT_SCSI_IO: { 523 PDCB pDCB = NULL; 524 PSRB pSRB; 525 struct ccb_scsiio *pcsio; 526 527 pcsio = &pccb->csio; 528 TRM_DPRINTF(" XPT_SCSI_IO \n"); 529 TRM_DPRINTF("trm: target_id= %d target_lun= %d \n" 530 ,target_id, target_lun); 531 TRM_DPRINTF( 532 "pACB->scan_devices[target_id][target_lun]= %d \n" 533 ,pACB->scan_devices[target_id][target_lun]); 534 pDCB = pACB->pDCB[target_id][target_lun]; 535 /* 536 * Assign an SRB and connect it with this ccb. 537 */ 538 pSRB = trm_GetSRB(pACB); 539 if (!pSRB) { 540 /* Freeze SIMQ */ 541 pccb->ccb_h.status = CAM_RESRC_UNAVAIL; 542 xpt_done(pccb); 543 return; 544 } 545 pSRB->pSRBDCB = pDCB; 546 pccb->ccb_h.ccb_trmsrb_ptr = pSRB; 547 pccb->ccb_h.ccb_trmacb_ptr = pACB; 548 pSRB->pccb = pccb; 549 pSRB->ScsiCmdLen = pcsio->cdb_len; 550 /* 551 * move layer of CAM command block to layer of SCSI 552 * Request Block for SCSI processor command doing 553 */ 554 bcopy(pcsio->cdb_io.cdb_bytes,pSRB->CmdBlock 555 ,pcsio->cdb_len); 556 if ((pccb->ccb_h.flags & CAM_DIR_MASK) 557 != CAM_DIR_NONE) { 558 if ((pccb->ccb_h.flags & 559 CAM_SCATTER_VALID) == 0) { 560 if ((pccb->ccb_h.flags 561 & CAM_DATA_PHYS) == 0) { 562 int error; 563 564 crit_enter(); 565 error = bus_dmamap_load( 566 pACB->buffer_dmat, 567 pSRB->dmamap, 568 pcsio->data_ptr, 569 pcsio->dxfer_len, 570 trm_ExecuteSRB, 571 pSRB, 572 0); 573 if (error == EINPROGRESS) { 574 xpt_freeze_simq( 575 pACB->psim, 576 1); 577 pccb->ccb_h.status |= 578 CAM_RELEASE_SIMQ; 579 } 580 crit_exit(); 581 } else { 582 struct bus_dma_segment seg; 583 584 /* Pointer to physical buffer */ 585 seg.ds_addr = 586 (bus_addr_t)pcsio->data_ptr; 587 seg.ds_len = pcsio->dxfer_len; 588 trm_ExecuteSRB(pSRB, &seg, 1, 589 0); 590 } 591 } else { 592 /* CAM_SCATTER_VALID */ 593 struct bus_dma_segment *segs; 594 595 if ((pccb->ccb_h.flags & 596 CAM_SG_LIST_PHYS) == 0 || 597 (pccb->ccb_h.flags 598 & CAM_DATA_PHYS) != 0) { 599 pSRB->pNextSRB = pACB->pFreeSRB; 600 pACB->pFreeSRB = pSRB; 601 pccb->ccb_h.status = 602 CAM_PROVIDE_FAIL; 603 xpt_done(pccb); 604 return; 605 } 606 607 /* cam SG list is physical, 608 * cam data is virtual 609 */ 610 segs = (struct bus_dma_segment *) 611 pcsio->data_ptr; 612 trm_ExecuteSRB(pSRB, segs, 613 pcsio->sglist_cnt, 1); 614 } /* CAM_SCATTER_VALID */ 615 } else 616 trm_ExecuteSRB(pSRB, NULL, 0, 0); 617 } 618 break; 619 case XPT_GDEV_TYPE: 620 TRM_DPRINTF(" XPT_GDEV_TYPE \n"); 621 pccb->ccb_h.status = CAM_REQ_INVALID; 622 xpt_done(pccb); 623 break; 624 case XPT_GDEVLIST: 625 TRM_DPRINTF(" XPT_GDEVLIST \n"); 626 pccb->ccb_h.status = CAM_REQ_INVALID; 627 xpt_done(pccb); 628 break; 629 /* 630 * Path routing inquiry 631 * Path Inquiry CCB 632 */ 633 case XPT_PATH_INQ: { 634 struct ccb_pathinq *cpi = &pccb->cpi; 635 636 TRM_DPRINTF(" XPT_PATH_INQ \n"); 637 cpi->version_num = 1; 638 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE|PI_WIDE_16; 639 cpi->target_sprt = 0; 640 cpi->hba_misc = 0; 641 cpi->hba_eng_cnt = 0; 642 cpi->max_target = 15 ; 643 cpi->max_lun = pACB->max_lun; /* 7 or 0 */ 644 cpi->initiator_id = pACB->AdaptSCSIID; 645 cpi->bus_id = cam_sim_bus(psim); 646 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 647 strncpy(cpi->hba_vid, "Tekram_TRM", HBA_IDLEN); 648 strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 649 cpi->unit_number = cam_sim_unit(psim); 650 #ifdef CAM_NEW_TRAN_CODE 651 cpi->transport = XPORT_SPI; 652 cpi->transport_version = 2; 653 cpi->protocol = PROTO_SCSI; 654 cpi->protocol_version = SCSI_REV_2; 655 #endif 656 cpi->ccb_h.status = CAM_REQ_CMP; 657 xpt_done(pccb); 658 } 659 break; 660 /* 661 * Release a frozen SIM queue 662 * Release SIM Queue 663 */ 664 case XPT_REL_SIMQ: 665 TRM_DPRINTF(" XPT_REL_SIMQ \n"); 666 pccb->ccb_h.status = CAM_REQ_INVALID; 667 xpt_done(pccb); 668 break; 669 /* 670 * Set Asynchronous Callback Parameters 671 * Set Asynchronous Callback CCB 672 */ 673 case XPT_SASYNC_CB: 674 TRM_DPRINTF(" XPT_SASYNC_CB \n"); 675 pccb->ccb_h.status = CAM_REQ_INVALID; 676 xpt_done(pccb); 677 break; 678 /* 679 * Set device type information 680 * Set Device Type CCB 681 */ 682 case XPT_SDEV_TYPE: 683 TRM_DPRINTF(" XPT_SDEV_TYPE \n"); 684 pccb->ccb_h.status = CAM_REQ_INVALID; 685 xpt_done(pccb); 686 break; 687 /* 688 * (Re)Scan the SCSI Bus 689 * Rescan the given bus, or bus/target/lun 690 */ 691 case XPT_SCAN_BUS: 692 TRM_DPRINTF(" XPT_SCAN_BUS \n"); 693 pccb->ccb_h.status = CAM_REQ_INVALID; 694 xpt_done(pccb); 695 break; 696 /* 697 * Get EDT entries matching the given pattern 698 */ 699 case XPT_DEV_MATCH: 700 TRM_DPRINTF(" XPT_DEV_MATCH \n"); 701 pccb->ccb_h.status = CAM_REQ_INVALID; 702 xpt_done(pccb); 703 break; 704 /* 705 * Turn on debugging for a bus, target or lun 706 */ 707 case XPT_DEBUG: 708 TRM_DPRINTF(" XPT_DEBUG \n"); 709 pccb->ccb_h.status = CAM_REQ_INVALID; 710 xpt_done(pccb); 711 break; 712 /* 713 * XPT_ABORT = 0x10, Abort the specified CCB 714 * Abort XPT request CCB 715 */ 716 case XPT_ABORT: 717 TRM_DPRINTF(" XPT_ABORT \n"); 718 pccb->ccb_h.status = CAM_REQ_INVALID; 719 xpt_done(pccb); 720 break; 721 /* 722 * Reset the specified SCSI bus 723 * Reset SCSI Bus CCB 724 */ 725 case XPT_RESET_BUS: { 726 int i; 727 728 TRM_DPRINTF(" XPT_RESET_BUS \n"); 729 trm_reset(pACB); 730 pACB->ACBFlag=0; 731 for (i=0; i<500; i++) 732 DELAY(1000); 733 pccb->ccb_h.status = CAM_REQ_CMP; 734 xpt_done(pccb); 735 } 736 break; 737 /* 738 * Bus Device Reset the specified SCSI device 739 * Reset SCSI Device CCB 740 */ 741 case XPT_RESET_DEV: 742 /* 743 * Don't (yet?) support vendor 744 * specific commands. 745 */ 746 TRM_DPRINTF(" XPT_RESET_DEV \n"); 747 pccb->ccb_h.status = CAM_REQ_INVALID; 748 xpt_done(pccb); 749 break; 750 /* 751 * Terminate the I/O process 752 * Terminate I/O Process Request CCB 753 */ 754 case XPT_TERM_IO: 755 TRM_DPRINTF(" XPT_TERM_IO \n"); 756 pccb->ccb_h.status = CAM_REQ_INVALID; 757 xpt_done(pccb); 758 break; 759 /* 760 * Scan Logical Unit 761 */ 762 case XPT_SCAN_LUN: 763 TRM_DPRINTF(" XPT_SCAN_LUN \n"); 764 pccb->ccb_h.status = CAM_REQ_INVALID; 765 xpt_done(pccb); 766 break; 767 768 /* 769 * Get/Set transfer rate/width/disconnection/tag queueing 770 * settings 771 * (GET) default/user transfer settings for the target 772 */ 773 case XPT_GET_TRAN_SETTINGS: { 774 struct ccb_trans_settings *cts = &pccb->cts; 775 struct trm_transinfo *tinfo; 776 PDCB pDCB; 777 #ifdef CAM_NEW_TRAN_CODE 778 struct ccb_trans_settings_scsi *scsi = 779 &cts->proto_specific.scsi; 780 struct ccb_trans_settings_spi *spi = 781 &cts->xport_specific.spi; 782 783 cts->protocol = PROTO_SCSI; 784 cts->protocol_version = SCSI_REV_2; 785 cts->transport = XPORT_SPI; 786 cts->transport_version = 2; 787 788 TRM_DPRINTF(" XPT_GET_TRAN_SETTINGS \n"); 789 pDCB = &pACB->DCBarray[target_id][target_lun]; 790 crit_enter(); 791 /* 792 * disable interrupt 793 */ 794 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 795 /* current transfer settings */ 796 if (pDCB->tinfo.disc_tag & TRM_CUR_DISCENB) 797 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 798 else 799 spi->flags = 0;/* no tag & disconnect */ 800 if (pDCB->tinfo.disc_tag & TRM_CUR_TAGENB) 801 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 802 tinfo = &pDCB->tinfo.current; 803 TRM_DPRINTF("CURRENT: cts->flags= %2x \n", 804 cts->flags); 805 } else { 806 /* default(user) transfer settings */ 807 if (pDCB->tinfo.disc_tag & TRM_USR_DISCENB) 808 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 809 else 810 spi->flags = 0; 811 if (pDCB->tinfo.disc_tag & TRM_USR_TAGENB) 812 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 813 tinfo = &pDCB->tinfo.user; 814 TRM_DPRINTF("USER: cts->flags= %2x \n", 815 cts->flags); 816 } 817 spi->sync_period = tinfo->period; 818 spi->sync_offset = tinfo->offset; 819 spi->bus_width = tinfo->width; 820 TRM_DPRINTF("pDCB->SyncPeriod: %d \n", 821 pDCB->SyncPeriod); 822 TRM_DPRINTF("period: %d \n", tinfo->period); 823 TRM_DPRINTF("offset: %d \n", tinfo->offset); 824 TRM_DPRINTF("width: %d \n", tinfo->width); 825 826 crit_exit(); 827 spi->valid = CTS_SPI_VALID_SYNC_RATE | 828 CTS_SPI_VALID_SYNC_OFFSET | 829 CTS_SPI_VALID_BUS_WIDTH | 830 CTS_SPI_VALID_DISC; 831 scsi->valid = CTS_SCSI_VALID_TQ; 832 #else 833 834 TRM_DPRINTF(" XPT_GET_TRAN_SETTINGS \n"); 835 pDCB = pACB->pDCB[target_id][target_lun]; 836 crit_enter(); 837 /* 838 * disable interrupt 839 */ 840 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) { 841 /* current transfer settings */ 842 if (pDCB->tinfo.disc_tag & TRM_CUR_DISCENB) 843 cts->flags = CCB_TRANS_DISC_ENB; 844 else 845 cts->flags = 0;/* no tag & disconnect */ 846 if (pDCB->tinfo.disc_tag & TRM_CUR_TAGENB) 847 cts->flags |= CCB_TRANS_TAG_ENB; 848 tinfo = &pDCB->tinfo.current; 849 TRM_DPRINTF("CURRENT: cts->flags= %2x \n", 850 cts->flags); 851 } else { 852 /* default(user) transfer settings */ 853 if (pDCB->tinfo.disc_tag & TRM_USR_DISCENB) 854 cts->flags = CCB_TRANS_DISC_ENB; 855 else 856 cts->flags = 0; 857 if (pDCB->tinfo.disc_tag & TRM_USR_TAGENB) 858 cts->flags |= CCB_TRANS_TAG_ENB; 859 tinfo = &pDCB->tinfo.user; 860 TRM_DPRINTF("USER: cts->flags= %2x \n", 861 cts->flags); 862 } 863 cts->sync_period = tinfo->period; 864 cts->sync_offset = tinfo->offset; 865 cts->bus_width = tinfo->width; 866 TRM_DPRINTF("pDCB->SyncPeriod: %d \n", 867 pDCB->SyncPeriod); 868 TRM_DPRINTF("period: %d \n", tinfo->period); 869 TRM_DPRINTF("offset: %d \n", tinfo->offset); 870 TRM_DPRINTF("width: %d \n", tinfo->width); 871 872 crit_exit(); 873 cts->valid = CCB_TRANS_SYNC_RATE_VALID | 874 CCB_TRANS_SYNC_OFFSET_VALID | 875 CCB_TRANS_BUS_WIDTH_VALID | 876 CCB_TRANS_DISC_VALID | 877 CCB_TRANS_TQ_VALID; 878 #endif 879 pccb->ccb_h.status = CAM_REQ_CMP; 880 xpt_done(pccb); 881 } 882 break; 883 /* 884 * Get/Set transfer rate/width/disconnection/tag queueing 885 * settings 886 * (Set) transfer rate/width negotiation settings 887 */ 888 case XPT_SET_TRAN_SETTINGS: { 889 struct ccb_trans_settings *cts = &pccb->cts; 890 u_int update_type; 891 PDCB pDCB; 892 #ifdef CAM_NEW_TRAN_CODE 893 struct ccb_trans_settings_scsi *scsi = 894 &cts->proto_specific.scsi; 895 struct ccb_trans_settings_spi *spi = 896 &cts->xport_specific.spi; 897 898 TRM_DPRINTF(" XPT_SET_TRAN_SETTINGS \n"); 899 update_type = 0; 900 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 901 update_type |= TRM_TRANS_GOAL; 902 if (cts->type == CTS_TYPE_USER_SETTINGS) 903 update_type |= TRM_TRANS_USER; 904 crit_enter(); 905 pDCB = &pACB->DCBarray[target_id][target_lun]; 906 907 if ((spi->valid & CTS_SPI_VALID_DISC) != 0) { 908 /*ccb disc enables */ 909 if (update_type & TRM_TRANS_GOAL) { 910 if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB) 911 != 0) 912 pDCB->tinfo.disc_tag 913 |= TRM_CUR_DISCENB; 914 else 915 pDCB->tinfo.disc_tag &= 916 ~TRM_CUR_DISCENB; 917 } 918 if (update_type & TRM_TRANS_USER) { 919 if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB) 920 != 0) 921 pDCB->tinfo.disc_tag 922 |= TRM_USR_DISCENB; 923 else 924 pDCB->tinfo.disc_tag &= 925 ~TRM_USR_DISCENB; 926 } 927 } 928 if ((scsi->valid & CTS_SCSI_VALID_TQ) != 0) { 929 /* if ccb tag q active */ 930 if (update_type & TRM_TRANS_GOAL) { 931 if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) 932 != 0) 933 pDCB->tinfo.disc_tag |= 934 TRM_CUR_TAGENB; 935 else 936 pDCB->tinfo.disc_tag &= 937 ~TRM_CUR_TAGENB; 938 } 939 if (update_type & TRM_TRANS_USER) { 940 if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) 941 != 0) 942 pDCB->tinfo.disc_tag |= 943 TRM_USR_TAGENB; 944 else 945 pDCB->tinfo.disc_tag &= 946 ~TRM_USR_TAGENB; 947 } 948 } 949 /* Minimum sync period factor */ 950 951 if ((spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0) { 952 /* if ccb sync active */ 953 /* TRM-S1040 MinSyncPeriod = 4 clocks/byte */ 954 if ((spi->sync_period != 0) && 955 (spi->sync_period < 125)) 956 spi->sync_period = 125; 957 /* 1/(125*4) minsync 2 MByte/sec */ 958 if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) 959 != 0) { 960 if (spi->sync_offset == 0) 961 spi->sync_period = 0; 962 /* TRM-S1040 MaxSyncOffset = 15 bytes*/ 963 if (spi->sync_offset > 15) 964 spi->sync_offset = 15; 965 } 966 } 967 if ((update_type & TRM_TRANS_USER) != 0) { 968 pDCB->tinfo.user.period = spi->sync_period; 969 pDCB->tinfo.user.offset = spi->sync_offset; 970 pDCB->tinfo.user.width = spi->bus_width; 971 } 972 if ((update_type & TRM_TRANS_GOAL) != 0) { 973 pDCB->tinfo.goal.period = spi->sync_period; 974 pDCB->tinfo.goal.offset = spi->sync_offset; 975 pDCB->tinfo.goal.width = spi->bus_width; 976 } 977 crit_exit(); 978 #else 979 TRM_DPRINTF(" XPT_SET_TRAN_SETTINGS \n"); 980 update_type = 0; 981 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) 982 update_type |= TRM_TRANS_GOAL; 983 if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) 984 update_type |= TRM_TRANS_USER; 985 crit_enter(); 986 pDCB = pACB->pDCB[target_id][target_lun]; 987 988 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) { 989 /*ccb disc enables */ 990 if (update_type & TRM_TRANS_GOAL) { 991 if ((cts->flags & CCB_TRANS_DISC_ENB) 992 != 0) 993 pDCB->tinfo.disc_tag 994 |= TRM_CUR_DISCENB; 995 else 996 pDCB->tinfo.disc_tag &= 997 ~TRM_CUR_DISCENB; 998 } 999 if (update_type & TRM_TRANS_USER) { 1000 if ((cts->flags & CCB_TRANS_DISC_ENB) 1001 != 0) 1002 pDCB->tinfo.disc_tag 1003 |= TRM_USR_DISCENB; 1004 else 1005 pDCB->tinfo.disc_tag &= 1006 ~TRM_USR_DISCENB; 1007 } 1008 } 1009 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) { 1010 /* if ccb tag q active */ 1011 if (update_type & TRM_TRANS_GOAL) { 1012 if ((cts->flags & CCB_TRANS_TAG_ENB) 1013 != 0) 1014 pDCB->tinfo.disc_tag |= 1015 TRM_CUR_TAGENB; 1016 else 1017 pDCB->tinfo.disc_tag &= 1018 ~TRM_CUR_TAGENB; 1019 } 1020 if (update_type & TRM_TRANS_USER) { 1021 if ((cts->flags & CCB_TRANS_TAG_ENB) 1022 != 0) 1023 pDCB->tinfo.disc_tag |= 1024 TRM_USR_TAGENB; 1025 else 1026 pDCB->tinfo.disc_tag &= 1027 ~TRM_USR_TAGENB; 1028 } 1029 } 1030 /* Minimum sync period factor */ 1031 1032 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) { 1033 /* if ccb sync active */ 1034 /* TRM-S1040 MinSyncPeriod = 4 clocks/byte */ 1035 if ((cts->sync_period != 0) && 1036 (cts->sync_period < 125)) 1037 cts->sync_period = 125; 1038 /* 1/(125*4) minsync 2 MByte/sec */ 1039 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) 1040 != 0) { 1041 if (cts->sync_offset == 0) 1042 cts->sync_period = 0; 1043 /* TRM-S1040 MaxSyncOffset = 15 bytes*/ 1044 if (cts->sync_offset > 15) 1045 cts->sync_offset = 15; 1046 } 1047 } 1048 if ((update_type & TRM_TRANS_USER) != 0) { 1049 pDCB->tinfo.user.period = cts->sync_period; 1050 pDCB->tinfo.user.offset = cts->sync_offset; 1051 pDCB->tinfo.user.width = cts->bus_width; 1052 } 1053 if ((update_type & TRM_TRANS_GOAL) != 0) { 1054 pDCB->tinfo.goal.period = cts->sync_period; 1055 pDCB->tinfo.goal.offset = cts->sync_offset; 1056 pDCB->tinfo.goal.width = cts->bus_width; 1057 } 1058 crit_exit(); 1059 #endif 1060 pccb->ccb_h.status = CAM_REQ_CMP; 1061 xpt_done(pccb); 1062 break; 1063 } 1064 /* 1065 * Calculate the geometry parameters for a device give 1066 * the sector size and volume size. 1067 */ 1068 case XPT_CALC_GEOMETRY: { 1069 struct ccb_calc_geometry *ccg; 1070 u_int32_t size_mb; 1071 u_int32_t secs_per_cylinder; 1072 int extended; 1073 1074 TRM_DPRINTF(" XPT_CALC_GEOMETRY \n"); 1075 ccg = &pccb->ccg; 1076 size_mb = ccg->volume_size / 1077 ((1024L * 1024L) / ccg->block_size); 1078 extended = 1; 1079 if (size_mb > 1024 && extended) { 1080 ccg->heads = 255; 1081 ccg->secs_per_track = 63; 1082 } else { 1083 ccg->heads = 64; 1084 ccg->secs_per_track = 32; 1085 } 1086 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 1087 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 1088 pccb->ccb_h.status = CAM_REQ_CMP; 1089 xpt_done(pccb); 1090 } 1091 break; 1092 case XPT_ENG_INQ: 1093 TRM_DPRINTF(" XPT_ENG_INQ \n"); 1094 pccb->ccb_h.status = CAM_REQ_INVALID; 1095 xpt_done(pccb); 1096 break; 1097 /* 1098 * HBA execute engine request 1099 * This structure must match SCSIIO size 1100 */ 1101 case XPT_ENG_EXEC: 1102 TRM_DPRINTF(" XPT_ENG_EXEC \n"); 1103 pccb->ccb_h.status = CAM_REQ_INVALID; 1104 xpt_done(pccb); 1105 break; 1106 /* 1107 * XPT_EN_LUN = 0x30, Enable LUN as a target 1108 * Target mode structures. 1109 */ 1110 case XPT_EN_LUN: 1111 /* 1112 * Don't (yet?) support vendor 1113 * specific commands. 1114 */ 1115 TRM_DPRINTF(" XPT_EN_LUN \n"); 1116 pccb->ccb_h.status = CAM_REQ_INVALID; 1117 xpt_done(pccb); 1118 break; 1119 /* 1120 * Execute target I/O request 1121 */ 1122 case XPT_TARGET_IO: 1123 /* 1124 * Don't (yet?) support vendor 1125 * specific commands. 1126 */ 1127 TRM_DPRINTF(" XPT_TARGET_IO \n"); 1128 pccb->ccb_h.status = CAM_REQ_INVALID; 1129 xpt_done(pccb); 1130 break; 1131 /* 1132 * Accept Host Target Mode CDB 1133 */ 1134 case XPT_ACCEPT_TARGET_IO: 1135 /* 1136 * Don't (yet?) support vendor 1137 * specific commands. 1138 */ 1139 TRM_DPRINTF(" XPT_ACCEPT_TARGET_IO \n"); 1140 pccb->ccb_h.status = CAM_REQ_INVALID; 1141 xpt_done(pccb); 1142 break; 1143 /* 1144 * Continue Host Target I/O Connection 1145 */ 1146 case XPT_CONT_TARGET_IO: 1147 /* 1148 * Don't (yet?) support vendor 1149 * specific commands. 1150 */ 1151 TRM_DPRINTF(" XPT_CONT_TARGET_IO \n"); 1152 pccb->ccb_h.status = CAM_REQ_INVALID; 1153 xpt_done(pccb); 1154 break; 1155 /* 1156 * Notify Host Target driver of event 1157 */ 1158 case XPT_IMMED_NOTIFY: 1159 TRM_DPRINTF(" XPT_IMMED_NOTIFY \n"); 1160 pccb->ccb_h.status = CAM_REQ_INVALID; 1161 xpt_done(pccb); 1162 break; 1163 /* 1164 * Acknowledgement of event 1165 */ 1166 case XPT_NOTIFY_ACK: 1167 TRM_DPRINTF(" XPT_NOTIFY_ACK \n"); 1168 pccb->ccb_h.status = CAM_REQ_INVALID; 1169 xpt_done(pccb); 1170 break; 1171 /* 1172 * XPT_VUNIQUE = 0x80 1173 */ 1174 case XPT_VUNIQUE: 1175 pccb->ccb_h.status = CAM_REQ_INVALID; 1176 xpt_done(pccb); 1177 break; 1178 default: 1179 pccb->ccb_h.status = CAM_REQ_INVALID; 1180 xpt_done(pccb); 1181 break; 1182 } 1183 } 1184 1185 static void 1186 trm_poll(struct cam_sim *psim) 1187 { 1188 1189 } 1190 1191 static void 1192 trm_ResetDevParam(PACB pACB) 1193 { 1194 PDCB pDCB, pdcb; 1195 PNVRAMTYPE pEEpromBuf; 1196 u_int8_t PeriodIndex; 1197 1198 pDCB = pACB->pLinkDCB; 1199 if (pDCB == NULL) 1200 return; 1201 pdcb = pDCB; 1202 do { 1203 pDCB->SyncMode &= ~(SYNC_NEGO_DONE+ WIDE_NEGO_DONE); 1204 pDCB->SyncPeriod = 0; 1205 pDCB->SyncOffset = 0; 1206 pEEpromBuf = &trm_eepromBuf[pACB->AdapterUnit]; 1207 pDCB->DevMode = 1208 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarCfg0; 1209 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 1210 PeriodIndex = 1211 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarPeriod & 0x07; 1212 pDCB->MaxNegoPeriod = dc395x_trm_clock_period[PeriodIndex]; 1213 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 1214 (pACB->Config & HCC_WIDE_CARD)) 1215 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 1216 pDCB = pDCB->pNextDCB; 1217 } 1218 while (pdcb != pDCB); 1219 } 1220 1221 static void 1222 trm_RecoverSRB(PACB pACB) 1223 { 1224 PDCB pDCB, pdcb; 1225 PSRB psrb, psrb2; 1226 u_int16_t cnt, i; 1227 1228 pDCB = pACB->pLinkDCB; 1229 if (pDCB == NULL) 1230 return; 1231 pdcb = pDCB; 1232 do { 1233 cnt = pdcb->GoingSRBCnt; 1234 psrb = pdcb->pGoingSRB; 1235 for (i = 0; i < cnt; i++) { 1236 psrb2 = psrb; 1237 psrb = psrb->pNextSRB; 1238 if (pdcb->pWaitingSRB) { 1239 psrb2->pNextSRB = pdcb->pWaitingSRB; 1240 pdcb->pWaitingSRB = psrb2; 1241 } else { 1242 pdcb->pWaitingSRB = psrb2; 1243 pdcb->pWaitLastSRB = psrb2; 1244 psrb2->pNextSRB = NULL; 1245 } 1246 } 1247 pdcb->GoingSRBCnt = 0; 1248 pdcb->pGoingSRB = NULL; 1249 pdcb->TagMask = 0; 1250 pdcb = pdcb->pNextDCB; 1251 } 1252 while (pdcb != pDCB); 1253 } 1254 1255 static void 1256 trm_reset(PACB pACB) 1257 { 1258 u_int16_t i; 1259 1260 TRM_DPRINTF("trm: RESET"); 1261 crit_enter(); 1262 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 1263 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 1264 1265 trm_ResetSCSIBus(pACB); 1266 for (i = 0; i < 500; i++) 1267 DELAY(1000); 1268 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 1269 /* Enable DMA interrupt */ 1270 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 1271 /* Clear DMA FIFO */ 1272 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1273 /* Clear SCSI FIFO */ 1274 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1275 trm_ResetDevParam(pACB); 1276 trm_DoingSRB_Done(pACB); 1277 pACB->pActiveDCB = NULL; 1278 pACB->ACBFlag = 0;/* RESET_DETECT, RESET_DONE ,RESET_DEV */ 1279 trm_DoWaitingSRB(pACB); 1280 /* Tell the XPT layer that a bus reset occured */ 1281 if (pACB->ppath != NULL) 1282 xpt_async(AC_BUS_RESET, pACB->ppath, NULL); 1283 crit_exit(); 1284 return; 1285 } 1286 1287 static u_int16_t 1288 trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB) 1289 { 1290 u_int16_t return_code; 1291 u_int8_t tag_number, scsicommand, i,command,identify_message; 1292 u_int8_t * ptr; 1293 u_long tag_mask; 1294 union ccb *pccb; 1295 struct ccb_scsiio *pcsio; 1296 1297 pccb = pSRB->pccb; 1298 pcsio = &pccb->csio; 1299 pSRB->TagNumber = 31; 1300 1301 trm_reg_write8(pACB->AdaptSCSIID, TRMREG_SCSI_HOSTID); 1302 trm_reg_write8(pDCB->TargetID, TRMREG_SCSI_TARGETID); 1303 trm_reg_write8(pDCB->SyncPeriod, TRMREG_SCSI_SYNC); 1304 trm_reg_write8(pDCB->SyncOffset, TRMREG_SCSI_OFFSET); 1305 pSRB->ScsiPhase = PH_BUS_FREE;/* initial phase */ 1306 /* Flush FIFO */ 1307 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1308 1309 identify_message = pDCB->IdentifyMsg; 1310 1311 if ((pSRB->CmdBlock[0] == INQUIRY) || 1312 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1313 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1314 if (((pDCB->SyncMode & WIDE_NEGO_ENABLE) && 1315 !(pDCB->SyncMode & WIDE_NEGO_DONE)) \ 1316 || ((pDCB->SyncMode & SYNC_NEGO_ENABLE) && 1317 !(pDCB->SyncMode & SYNC_NEGO_DONE))) { 1318 if (!(pDCB->IdentifyMsg & 7) || 1319 (pSRB->CmdBlock[0] != INQUIRY)) { 1320 scsicommand = SCMD_SEL_ATNSTOP; 1321 pSRB->SRBState = SRB_MSGOUT; 1322 goto polling; 1323 } 1324 } 1325 /* 1326 * Send identify message 1327 */ 1328 trm_reg_write8((identify_message & 0xBF) ,TRMREG_SCSI_FIFO); 1329 scsicommand = SCMD_SEL_ATN; 1330 pSRB->SRBState = SRB_START_; 1331 } else { 1332 /* not inquiry,request sense,auto request sense */ 1333 /* 1334 * Send identify message 1335 */ 1336 trm_reg_write8(identify_message,TRMREG_SCSI_FIFO); 1337 scsicommand = SCMD_SEL_ATN; 1338 pSRB->SRBState = SRB_START_; 1339 if (pDCB->SyncMode & EN_TAG_QUEUING) { 1340 /* Send Tag message */ 1341 /* 1342 * Get tag id 1343 */ 1344 tag_mask = 1; 1345 tag_number = 0; 1346 while (tag_mask & pDCB->TagMask) { 1347 tag_mask = tag_mask << 1; 1348 tag_number++; 1349 } 1350 /* 1351 * Send Tag id 1352 */ 1353 trm_reg_write8(MSG_SIMPLE_QTAG, TRMREG_SCSI_FIFO); 1354 trm_reg_write8(tag_number, TRMREG_SCSI_FIFO); 1355 pDCB->TagMask |= tag_mask; 1356 pSRB->TagNumber = tag_number; 1357 scsicommand = SCMD_SEL_ATN3; 1358 pSRB->SRBState = SRB_START_; 1359 } 1360 } 1361 polling: 1362 /* 1363 * Send CDB ..command block ......... 1364 */ 1365 if (pSRB->SRBFlag & AUTO_REQSENSE) { 1366 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1367 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1368 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1369 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1370 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1371 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1372 } else { 1373 ptr = (u_int8_t *) pSRB->CmdBlock; 1374 for (i = 0; i < pSRB->ScsiCmdLen ; i++) { 1375 command = *ptr++; 1376 trm_reg_write8(command,TRMREG_SCSI_FIFO); 1377 } 1378 } 1379 if (trm_reg_read16(TRMREG_SCSI_STATUS) & SCSIINTERRUPT) { 1380 /* 1381 * If trm_StartSCSI return 1 : 1382 * current interrupt status is interrupt disreenable 1383 * It's said that SCSI processor has more one SRB need to do, 1384 * SCSI processor has been occupied by one SRB. 1385 */ 1386 pSRB->SRBState = SRB_READY; 1387 pDCB->TagMask &= ~(1 << pSRB->TagNumber); 1388 return_code = 1; 1389 } else { 1390 /* 1391 * If trm_StartSCSI return 0 : 1392 * current interrupt status is interrupt enable 1393 * It's said that SCSI processor is unoccupied 1394 */ 1395 pSRB->ScsiPhase = SCSI_NOP1; /* SCSI bus free Phase */ 1396 pACB->pActiveDCB = pDCB; 1397 pDCB->pActiveSRB = pSRB; 1398 return_code = 0; 1399 trm_reg_write16(DO_DATALATCH | DO_HWRESELECT, 1400 TRMREG_SCSI_CONTROL);/* it's important for atn stop*/ 1401 /* 1402 * SCSI cammand 1403 */ 1404 trm_reg_write8(scsicommand,TRMREG_SCSI_COMMAND); 1405 } 1406 return (return_code); 1407 } 1408 1409 static void 1410 trm_Interrupt(void *vpACB) 1411 { 1412 PACB pACB; 1413 PDCB pDCB; 1414 PSRB pSRB; 1415 u_int16_t phase; 1416 void (*stateV)(PACB, PSRB, u_int8_t *); 1417 u_int8_t scsi_status=0, scsi_intstatus; 1418 1419 pACB = vpACB; 1420 1421 if (pACB == NULL) { 1422 TRM_DPRINTF("trm_Interrupt: pACB NULL return......"); 1423 return; 1424 } 1425 1426 scsi_status = trm_reg_read16(TRMREG_SCSI_STATUS); 1427 if (!(scsi_status & SCSIINTERRUPT)) { 1428 TRM_DPRINTF("trm_Interrupt: TRMREG_SCSI_STATUS scsi_status = NULL ,return......"); 1429 return; 1430 } 1431 TRM_DPRINTF("scsi_status=%2x,",scsi_status); 1432 1433 scsi_intstatus = trm_reg_read8(TRMREG_SCSI_INTSTATUS); 1434 1435 TRM_DPRINTF("scsi_intstatus=%2x,",scsi_intstatus); 1436 1437 if (scsi_intstatus & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1438 trm_Disconnect(pACB); 1439 return; 1440 } 1441 1442 if (scsi_intstatus & INT_RESELECTED) { 1443 trm_Reselect(pACB); 1444 return; 1445 } 1446 if (scsi_intstatus & INT_SCSIRESET) { 1447 trm_ScsiRstDetect(pACB); 1448 return; 1449 } 1450 1451 if (scsi_intstatus & (INT_BUSSERVICE | INT_CMDDONE)) { 1452 pDCB = pACB->pActiveDCB; 1453 pSRB = pDCB->pActiveSRB; 1454 if (pDCB) { 1455 if (pDCB->DCBFlag & ABORT_DEV_) 1456 trm_EnableMsgOutAbort1(pACB, pSRB); 1457 } 1458 phase = (u_int16_t) pSRB->ScsiPhase; /* phase: */ 1459 stateV = (void *) trm_SCSI_phase0[phase]; 1460 stateV(pACB, pSRB, &scsi_status); 1461 pSRB->ScsiPhase = scsi_status & PHASEMASK; 1462 /* phase:0,1,2,3,4,5,6,7 */ 1463 phase = (u_int16_t) scsi_status & PHASEMASK; 1464 stateV = (void *) trm_SCSI_phase1[phase]; 1465 stateV(pACB, pSRB, &scsi_status); 1466 } 1467 } 1468 1469 static void 1470 trm_MsgOutPhase0(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1471 { 1472 1473 if (pSRB->SRBState & (SRB_UNEXPECT_RESEL+SRB_ABORT_SENT)) 1474 *pscsi_status = PH_BUS_FREE; 1475 /*.. initial phase*/ 1476 } 1477 1478 static void 1479 trm_MsgOutPhase1(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1480 { 1481 u_int8_t bval; 1482 u_int16_t i, cnt; 1483 u_int8_t * ptr; 1484 PDCB pDCB; 1485 1486 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1487 pDCB = pACB->pActiveDCB; 1488 if (!(pSRB->SRBState & SRB_MSGOUT)) { 1489 cnt = pSRB->MsgCnt; 1490 if (cnt) { 1491 ptr = (u_int8_t *) pSRB->MsgOutBuf; 1492 for (i = 0; i < cnt; i++) { 1493 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1494 ptr++; 1495 } 1496 pSRB->MsgCnt = 0; 1497 if ((pDCB->DCBFlag & ABORT_DEV_) && 1498 (pSRB->MsgOutBuf[0] == MSG_ABORT)) { 1499 pSRB->SRBState = SRB_ABORT_SENT; 1500 } 1501 } else { 1502 bval = MSG_ABORT; 1503 if ((pSRB->CmdBlock[0] == INQUIRY) || 1504 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1505 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1506 if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1507 goto mop1; 1508 } 1509 } 1510 trm_reg_write8(bval, TRMREG_SCSI_FIFO); 1511 } 1512 } else { 1513 mop1: /* message out phase */ 1514 if (!(pSRB->SRBState & SRB_DO_WIDE_NEGO) 1515 && (pDCB->SyncMode & WIDE_NEGO_ENABLE)) { 1516 /* 1517 * WIDE DATA TRANSFER REQUEST code (03h) 1518 */ 1519 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | EN_ATN_STOP); 1520 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1521 TRMREG_SCSI_FIFO); 1522 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1523 /* (01h) */ 1524 trm_reg_write8(2,TRMREG_SCSI_FIFO); 1525 /* Message length (02h) */ 1526 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1527 /* wide data xfer (03h) */ 1528 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1529 /* width:0(8bit),1(16bit),2(32bit) */ 1530 pSRB->SRBState |= SRB_DO_WIDE_NEGO; 1531 } else if (!(pSRB->SRBState & SRB_DO_SYNC_NEGO) 1532 && (pDCB->SyncMode & SYNC_NEGO_ENABLE)) { 1533 /* 1534 * SYNCHRONOUS DATA TRANSFER REQUEST code (01h) 1535 */ 1536 if (!(pDCB->SyncMode & WIDE_NEGO_DONE)) 1537 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1538 TRMREG_SCSI_FIFO); 1539 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1540 /* (01h) */ 1541 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1542 /* Message length (03h) */ 1543 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1544 /* SYNCHRONOUS DATA TRANSFER REQUEST code (01h) */ 1545 trm_reg_write8(pDCB->MaxNegoPeriod,TRMREG_SCSI_FIFO); 1546 /* Transfer peeriod factor */ 1547 trm_reg_write8(SYNC_NEGO_OFFSET,TRMREG_SCSI_FIFO); 1548 /* REQ/ACK offset */ 1549 pSRB->SRBState |= SRB_DO_SYNC_NEGO; 1550 } 1551 } 1552 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1553 /* it's important for atn stop */ 1554 /* 1555 * SCSI cammand 1556 */ 1557 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1558 } 1559 1560 static void 1561 trm_CommandPhase0(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1562 { 1563 1564 } 1565 1566 static void 1567 trm_CommandPhase1(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1568 { 1569 PDCB pDCB; 1570 u_int8_t * ptr; 1571 u_int16_t i, cnt; 1572 union ccb *pccb; 1573 struct ccb_scsiio *pcsio; 1574 1575 pccb = pSRB->pccb; 1576 pcsio = &pccb->csio; 1577 1578 trm_reg_write16(DO_CLRATN | DO_CLRFIFO , TRMREG_SCSI_CONTROL); 1579 if (!(pSRB->SRBFlag & AUTO_REQSENSE)) { 1580 cnt = (u_int16_t) pSRB->ScsiCmdLen; 1581 ptr = (u_int8_t *) pSRB->CmdBlock; 1582 for (i = 0; i < cnt; i++) { 1583 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1584 ptr++; 1585 } 1586 } else { 1587 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1588 pDCB = pACB->pActiveDCB; 1589 /* target id */ 1590 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1591 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1592 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1593 /* sizeof(struct scsi_sense_data) */ 1594 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1595 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1596 } 1597 pSRB->SRBState = SRB_COMMAND; 1598 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1599 /* it's important for atn stop*/ 1600 /* 1601 * SCSI cammand 1602 */ 1603 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1604 } 1605 1606 static void 1607 trm_DataOutPhase0(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1608 { 1609 PDCB pDCB; 1610 u_int8_t TempDMAstatus,SGIndexTemp; 1611 u_int16_t scsi_status; 1612 PSEG pseg; 1613 u_long TempSRBXferredLength,dLeftCounter=0; 1614 1615 pDCB = pSRB->pSRBDCB; 1616 scsi_status = *pscsi_status; 1617 1618 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1619 if (scsi_status & PARITYERROR) 1620 pSRB->SRBStatus |= PARITY_ERROR; 1621 if (!(scsi_status & SCSIXFERDONE)) { 1622 /* 1623 * when data transfer from DMA FIFO to SCSI FIFO 1624 * if there was some data left in SCSI FIFO 1625 */ 1626 dLeftCounter = (u_long) 1627 (trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x1F); 1628 if (pDCB->SyncPeriod & WIDE_SYNC) { 1629 /* 1630 * if WIDE scsi SCSI FIFOCNT unit is word 1631 * so need to * 2 1632 */ 1633 dLeftCounter <<= 1; 1634 } 1635 } 1636 /* 1637 * caculate all the residue data that not yet tranfered 1638 * SCSI transfer counter + left in SCSI FIFO data 1639 * 1640 * .....TRM_SCSI_COUNTER (24bits) 1641 * The counter always decrement by one for every SCSI byte 1642 *transfer. 1643 * .....TRM_SCSI_FIFOCNT (5bits) 1644 * The counter is SCSI FIFO offset counter 1645 */ 1646 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1647 if (dLeftCounter == 1) { 1648 dLeftCounter = 0; 1649 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1650 } 1651 if ((dLeftCounter == 0) || 1652 (scsi_status & SCSIXFERCNT_2_ZERO)) { 1653 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1654 while (!(TempDMAstatus & DMAXFERCOMP)) { 1655 TempDMAstatus = 1656 trm_reg_read8(TRMREG_DMA_STATUS); 1657 } 1658 pSRB->SRBTotalXferLength = 0; 1659 } else { 1660 /* Update SG list */ 1661 /* 1662 * if transfer not yet complete 1663 * there were some data residue in SCSI FIFO or 1664 * SCSI transfer counter not empty 1665 */ 1666 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1667 /* 1668 * data that had transferred length 1669 */ 1670 TempSRBXferredLength = 1671 pSRB->SRBTotalXferLength - dLeftCounter; 1672 /* 1673 * next time to be transferred length 1674 */ 1675 pSRB->SRBTotalXferLength = dLeftCounter; 1676 /* 1677 * parsing from last time disconnect SRBSGIndex 1678 */ 1679 pseg = 1680 pSRB->SRBSGListPointer + pSRB->SRBSGIndex; 1681 for (SGIndexTemp = pSRB->SRBSGIndex; 1682 SGIndexTemp < pSRB->SRBSGCount; 1683 SGIndexTemp++) { 1684 /* 1685 * find last time which SG transfer be 1686 * disconnect 1687 */ 1688 if (TempSRBXferredLength >= 1689 pseg->length) 1690 TempSRBXferredLength -= 1691 pseg->length; 1692 else { 1693 /* 1694 * update last time disconnected SG 1695 * list 1696 */ 1697 pseg->length -= 1698 TempSRBXferredLength; 1699 /* residue data length */ 1700 pseg->address += 1701 TempSRBXferredLength; 1702 /* residue data pointer */ 1703 pSRB->SRBSGIndex = SGIndexTemp; 1704 break; 1705 } 1706 pseg++; 1707 } 1708 } 1709 } 1710 } 1711 trm_reg_write8(STOPDMAXFER ,TRMREG_DMA_CONTROL); 1712 } 1713 1714 1715 static void 1716 trm_DataOutPhase1(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1717 { 1718 u_int16_t ioDir; 1719 /* 1720 * do prepare befor transfer when data out phase 1721 */ 1722 1723 ioDir = XFERDATAOUT; 1724 trm_DataIO_transfer(pACB, pSRB, ioDir); 1725 } 1726 1727 static void 1728 trm_DataInPhase0(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1729 { 1730 u_int8_t bval,SGIndexTemp; 1731 u_int16_t scsi_status; 1732 PSEG pseg; 1733 u_long TempSRBXferredLength,dLeftCounter = 0; 1734 1735 scsi_status = *pscsi_status; 1736 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1737 if (scsi_status & PARITYERROR) 1738 pSRB->SRBStatus |= PARITY_ERROR; 1739 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1740 if ((dLeftCounter == 0) || (scsi_status & SCSIXFERCNT_2_ZERO)) { 1741 bval = trm_reg_read8(TRMREG_DMA_STATUS); 1742 while (!(bval & DMAXFERCOMP)) 1743 bval = trm_reg_read8(TRMREG_DMA_STATUS); 1744 pSRB->SRBTotalXferLength = 0; 1745 } else { 1746 /* 1747 * parsing the case: 1748 * when a transfer not yet complete 1749 * but be disconnected by uper layer 1750 * if transfer not yet complete 1751 * there were some data residue in SCSI FIFO or 1752 * SCSI transfer counter not empty 1753 */ 1754 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1755 /* 1756 * data that had transferred length 1757 */ 1758 TempSRBXferredLength = 1759 pSRB->SRBTotalXferLength - dLeftCounter; 1760 /* 1761 * next time to be transferred length 1762 */ 1763 pSRB->SRBTotalXferLength = dLeftCounter; 1764 /* 1765 * parsing from last time disconnect SRBSGIndex 1766 */ 1767 pseg = pSRB->SRBSGListPointer + pSRB->SRBSGIndex; 1768 for (SGIndexTemp = pSRB->SRBSGIndex; 1769 SGIndexTemp < pSRB->SRBSGCount; 1770 SGIndexTemp++) { 1771 /* 1772 * find last time which SG transfer be disconnect 1773 */ 1774 if (TempSRBXferredLength >= pseg->length) 1775 TempSRBXferredLength -= pseg->length; 1776 else { 1777 /* 1778 * update last time disconnected SG list 1779 */ 1780 pseg->length -= TempSRBXferredLength; 1781 /* residue data length */ 1782 pseg->address += TempSRBXferredLength; 1783 /* residue data pointer */ 1784 pSRB->SRBSGIndex = SGIndexTemp; 1785 break; 1786 } 1787 pseg++; 1788 } 1789 } 1790 } 1791 } 1792 } 1793 1794 static void 1795 trm_DataInPhase1(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1796 { 1797 u_int16_t ioDir; 1798 /* 1799 * do prepare befor transfer when data in phase 1800 */ 1801 1802 ioDir = XFERDATAIN; 1803 trm_DataIO_transfer(pACB, pSRB, ioDir); 1804 } 1805 1806 static void 1807 trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir) 1808 { 1809 u_int8_t bval; 1810 PDCB pDCB; 1811 1812 pDCB = pSRB->pSRBDCB; 1813 if (pSRB->SRBSGIndex < pSRB->SRBSGCount) { 1814 if (pSRB->SRBTotalXferLength != 0) { 1815 pSRB->SRBSGPhyAddr = vtophys(pSRB->SRBSGListPointer); 1816 /* 1817 * load what physical address of Scatter/Gather list 1818 table want to be transfer 1819 */ 1820 pSRB->SRBState = SRB_DATA_XFER; 1821 trm_reg_write32(0, TRMREG_DMA_XHIGHADDR); 1822 trm_reg_write32( 1823 (pSRB->SRBSGPhyAddr + 1824 ((u_long)pSRB->SRBSGIndex << 3)), 1825 TRMREG_DMA_XLOWADDR); 1826 /* 1827 * load how many bytes in the Scatter/Gather 1828 * list table 1829 */ 1830 trm_reg_write32( 1831 ((u_long)(pSRB->SRBSGCount - pSRB->SRBSGIndex) << 3), 1832 TRMREG_DMA_XCNT); 1833 /* 1834 * load total transfer length (24bits) max value 1835 * 16Mbyte 1836 */ 1837 trm_reg_write32(pSRB->SRBTotalXferLength, 1838 TRMREG_SCSI_COUNTER); 1839 /* Start DMA transfer */ 1840 trm_reg_write16(ioDir, TRMREG_DMA_COMMAND); 1841 /* Start SCSI transfer */ 1842 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1843 /* it's important for atn stop */ 1844 /* 1845 * SCSI cammand 1846 */ 1847 bval = (ioDir == XFERDATAOUT) ? 1848 SCMD_DMA_OUT : SCMD_DMA_IN; 1849 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1850 } else { 1851 /* xfer pad */ 1852 if (pSRB->SRBSGCount) { 1853 pSRB->AdaptStatus = H_OVER_UNDER_RUN; 1854 pSRB->SRBStatus |= OVER_RUN; 1855 } 1856 if (pDCB->SyncPeriod & WIDE_SYNC) 1857 trm_reg_write32(2,TRMREG_SCSI_COUNTER); 1858 else 1859 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 1860 if (ioDir == XFERDATAOUT) 1861 trm_reg_write16(0, TRMREG_SCSI_FIFO); 1862 else 1863 trm_reg_read16(TRMREG_SCSI_FIFO); 1864 pSRB->SRBState |= SRB_XFERPAD; 1865 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1866 /* it's important for atn stop */ 1867 /* 1868 * SCSI cammand 1869 */ 1870 bval = (ioDir == XFERDATAOUT) ? 1871 SCMD_FIFO_OUT : SCMD_FIFO_IN; 1872 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1873 } 1874 } 1875 } 1876 1877 static void 1878 trm_StatusPhase0(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1879 { 1880 1881 pSRB->TargetStatus = trm_reg_read8(TRMREG_SCSI_FIFO); 1882 pSRB->SRBState = SRB_COMPLETED; 1883 *pscsi_status = PH_BUS_FREE; 1884 /*.. initial phase*/ 1885 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1886 /* it's important for atn stop */ 1887 /* 1888 * SCSI cammand 1889 */ 1890 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1891 } 1892 1893 1894 1895 static void 1896 trm_StatusPhase1(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1897 { 1898 1899 if (trm_reg_read16(TRMREG_DMA_COMMAND) & 0x0001) { 1900 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1901 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1902 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1903 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1904 } else { 1905 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1906 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1907 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1908 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1909 } 1910 pSRB->SRBState = SRB_STATUS; 1911 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1912 /* it's important for atn stop */ 1913 /* 1914 * SCSI cammand 1915 */ 1916 trm_reg_write8(SCMD_COMP, TRMREG_SCSI_COMMAND); 1917 } 1918 1919 /* 1920 *scsiiom 1921 * trm_MsgInPhase0: one of trm_SCSI_phase0[] vectors 1922 * stateV = (void *) trm_SCSI_phase0[phase] 1923 * if phase =7 1924 * extended message codes: 1925 * 1926 * code description 1927 * 1928 * 02h Reserved 1929 * 00h MODIFY DATA POINTER 1930 * 01h SYNCHRONOUS DATA TRANSFER REQUEST 1931 * 03h WIDE DATA TRANSFER REQUEST 1932 * 04h - 7Fh Reserved 1933 * 80h - FFh Vendor specific 1934 * 1935 */ 1936 1937 static void 1938 trm_MsgInPhase0(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 1939 { 1940 u_int8_t message_in_code,bIndex,message_in_tag_id; 1941 PDCB pDCB; 1942 PSRB pSRBTemp; 1943 1944 pDCB = pACB->pActiveDCB; 1945 1946 message_in_code = trm_reg_read8(TRMREG_SCSI_FIFO); 1947 if (!(pSRB->SRBState & SRB_EXTEND_MSGIN)) { 1948 if (message_in_code == MSG_DISCONNECT) { 1949 pSRB->SRBState = SRB_DISCONNECT; 1950 goto min6; 1951 } else if (message_in_code == MSG_SAVE_PTR) { 1952 goto min6; 1953 } else if ((message_in_code == MSG_EXTENDED) || 1954 ((message_in_code >= MSG_SIMPLE_QTAG) && 1955 (message_in_code <= MSG_ORDER_QTAG))) { 1956 pSRB->SRBState |= SRB_EXTEND_MSGIN; 1957 pSRB->MsgInBuf[0] = message_in_code; 1958 /* extended message (01h) */ 1959 pSRB->MsgCnt = 1; 1960 pSRB->pMsgPtr = &pSRB->MsgInBuf[1]; 1961 /* extended message length (n) */ 1962 goto min6; 1963 } else if (message_in_code == MSG_REJECT_) { 1964 /* Reject message */ 1965 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 1966 /* do wide nego reject */ 1967 pDCB = pSRB->pSRBDCB; 1968 pDCB->SyncMode |= WIDE_NEGO_DONE; 1969 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | 1970 EN_ATN_STOP | WIDE_NEGO_ENABLE); 1971 pSRB->SRBState &= ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 1972 if ((pDCB->SyncMode & SYNC_NEGO_ENABLE) 1973 && !(pDCB->SyncMode & SYNC_NEGO_DONE)) { 1974 /* Set ATN, in case ATN was clear */ 1975 pSRB->SRBState |= SRB_MSGOUT; 1976 trm_reg_write16( 1977 DO_SETATN, 1978 TRMREG_SCSI_CONTROL); 1979 } else { 1980 /* Clear ATN */ 1981 trm_reg_write16( 1982 DO_CLRATN, 1983 TRMREG_SCSI_CONTROL); 1984 } 1985 } else if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1986 /* do sync nego reject */ 1987 trm_reg_write16(DO_CLRATN,TRMREG_SCSI_CONTROL); 1988 if (pSRB->SRBState & SRB_DO_SYNC_NEGO) { 1989 pDCB = pSRB->pSRBDCB; 1990 pDCB->SyncMode &= 1991 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 1992 pDCB->SyncPeriod = 0; 1993 pDCB->SyncOffset = 0; 1994 goto re_prog; 1995 } 1996 } 1997 goto min6; 1998 } else if (message_in_code == MSG_IGNOREWIDE) { 1999 trm_reg_write32(1, TRMREG_SCSI_COUNTER); 2000 trm_reg_read8(TRMREG_SCSI_FIFO); 2001 goto min6; 2002 } else { 2003 /* Restore data pointer message */ 2004 /* Save data pointer message */ 2005 /* Completion message */ 2006 /* NOP message */ 2007 goto min6; 2008 } 2009 } else { 2010 /* 2011 * Parsing incomming extented messages 2012 */ 2013 *pSRB->pMsgPtr = message_in_code; 2014 pSRB->MsgCnt++; 2015 pSRB->pMsgPtr++; 2016 TRM_DPRINTF("pSRB->MsgInBuf[0]=%2x \n ",pSRB->MsgInBuf[0]); 2017 TRM_DPRINTF("pSRB->MsgInBuf[1]=%2x \n ",pSRB->MsgInBuf[1]); 2018 TRM_DPRINTF("pSRB->MsgInBuf[2]=%2x \n ",pSRB->MsgInBuf[2]); 2019 TRM_DPRINTF("pSRB->MsgInBuf[3]=%2x \n ",pSRB->MsgInBuf[3]); 2020 TRM_DPRINTF("pSRB->MsgInBuf[4]=%2x \n ",pSRB->MsgInBuf[4]); 2021 if ((pSRB->MsgInBuf[0] >= MSG_SIMPLE_QTAG) 2022 && (pSRB->MsgInBuf[0] <= MSG_ORDER_QTAG)) { 2023 /* 2024 * is QUEUE tag message : 2025 * 2026 * byte 0: 2027 * HEAD QUEUE TAG (20h) 2028 * ORDERED QUEUE TAG (21h) 2029 * SIMPLE QUEUE TAG (22h) 2030 * byte 1: 2031 * Queue tag (00h - FFh) 2032 */ 2033 if (pSRB->MsgCnt == 2) { 2034 pSRB->SRBState = 0; 2035 message_in_tag_id = pSRB->MsgInBuf[1]; 2036 pSRB = pDCB->pGoingSRB; 2037 pSRBTemp = pDCB->pGoingLastSRB; 2038 if (pSRB) { 2039 for (;;) { 2040 if (pSRB->TagNumber != 2041 message_in_tag_id) { 2042 if (pSRB == pSRBTemp) { 2043 goto mingx0; 2044 } 2045 pSRB = pSRB->pNextSRB; 2046 } else 2047 break; 2048 } 2049 if (pDCB->DCBFlag & ABORT_DEV_) { 2050 pSRB->SRBState = SRB_ABORT_SENT; 2051 trm_EnableMsgOutAbort1( 2052 pACB, pSRB); 2053 } 2054 if (!(pSRB->SRBState & SRB_DISCONNECT)) 2055 goto mingx0; 2056 pDCB->pActiveSRB = pSRB; 2057 pSRB->SRBState = SRB_DATA_XFER; 2058 } else { 2059 mingx0: 2060 pSRB = pACB->pTmpSRB; 2061 pSRB->SRBState = SRB_UNEXPECT_RESEL; 2062 pDCB->pActiveSRB = pSRB; 2063 pSRB->MsgOutBuf[0] = MSG_ABORT_TAG; 2064 trm_EnableMsgOutAbort2( 2065 pACB, 2066 pSRB); 2067 } 2068 } 2069 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 2070 (pSRB->MsgInBuf[2] == 3) && (pSRB->MsgCnt == 4)) { 2071 /* 2072 * is Wide data xfer Extended message : 2073 * ====================================== 2074 * WIDE DATA TRANSFER REQUEST 2075 * ====================================== 2076 * byte 0 : Extended message (01h) 2077 * byte 1 : Extended message length (02h) 2078 * byte 2 : WIDE DATA TRANSFER code (03h) 2079 * byte 3 : Transfer width exponent 2080 */ 2081 pDCB = pSRB->pSRBDCB; 2082 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_WIDE_NEGO); 2083 if ((pSRB->MsgInBuf[1] != 2)) { 2084 /* Length is wrong, reject it */ 2085 pDCB->SyncMode &= 2086 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 2087 pSRB->MsgCnt = 1; 2088 pSRB->MsgInBuf[0] = MSG_REJECT_; 2089 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2090 goto min6; 2091 } 2092 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 2093 /* Do wide negoniation */ 2094 if (pSRB->MsgInBuf[3] > 2) { 2095 /* > 32 bit */ 2096 /* reject_msg: */ 2097 pDCB->SyncMode &= 2098 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 2099 pSRB->MsgCnt = 1; 2100 pSRB->MsgInBuf[0] = MSG_REJECT_; 2101 trm_reg_write16(DO_SETATN, 2102 TRMREG_SCSI_CONTROL); 2103 goto min6; 2104 } 2105 if (pSRB->MsgInBuf[3] == 2) { 2106 pSRB->MsgInBuf[3] = 1; 2107 /* do 16 bits */ 2108 } else { 2109 if (!(pDCB->SyncMode 2110 & WIDE_NEGO_DONE)) { 2111 pSRB->SRBState &= 2112 ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 2113 pDCB->SyncMode |= 2114 WIDE_NEGO_DONE; 2115 pDCB->SyncMode &= 2116 ~(SYNC_NEGO_DONE | 2117 EN_ATN_STOP | 2118 WIDE_NEGO_ENABLE); 2119 if (pSRB->MsgInBuf[3] != 0) { 2120 /* is Wide data xfer */ 2121 pDCB->SyncPeriod |= 2122 WIDE_SYNC; 2123 pDCB->tinfo.current.width 2124 = MSG_EXT_WDTR_BUS_16_BIT; 2125 pDCB->tinfo.goal.width 2126 = MSG_EXT_WDTR_BUS_16_BIT; 2127 } 2128 } 2129 } 2130 } else 2131 pSRB->MsgInBuf[3] = 0; 2132 pSRB->SRBState |= SRB_MSGOUT; 2133 trm_reg_write16(DO_SETATN,TRMREG_SCSI_CONTROL); 2134 goto min6; 2135 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 2136 (pSRB->MsgInBuf[2] == 1) && (pSRB->MsgCnt == 5)) { 2137 /* 2138 * is 8bit transfer Extended message : 2139 * ================================= 2140 * SYNCHRONOUS DATA TRANSFER REQUEST 2141 * ================================= 2142 * byte 0 : Extended message (01h) 2143 * byte 1 : Extended message length (03) 2144 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h) 2145 * byte 3 : Transfer period factor 2146 * byte 4 : REQ/ACK offset 2147 */ 2148 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_SYNC_NEGO); 2149 if ((pSRB->MsgInBuf[1] != 3) || 2150 (pSRB->MsgInBuf[2] != 1)) { 2151 /* reject_msg: */ 2152 pSRB->MsgCnt = 1; 2153 pSRB->MsgInBuf[0] = MSG_REJECT_; 2154 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2155 } else if (!(pSRB->MsgInBuf[3]) || !(pSRB->MsgInBuf[4])) { 2156 /* set async */ 2157 pDCB = pSRB->pSRBDCB; 2158 /* disable sync & sync nego */ 2159 pDCB->SyncMode &= 2160 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 2161 pDCB->SyncPeriod = 0; 2162 pDCB->SyncOffset = 0; 2163 pDCB->tinfo.goal.period = 0; 2164 pDCB->tinfo.goal.offset = 0; 2165 pDCB->tinfo.current.period = 0; 2166 pDCB->tinfo.current.offset = 0; 2167 pDCB->tinfo.current.width = 2168 MSG_EXT_WDTR_BUS_8_BIT; 2169 goto re_prog; 2170 } else { 2171 /* set sync */ 2172 pDCB = pSRB->pSRBDCB; 2173 pDCB->SyncMode |= 2174 SYNC_NEGO_ENABLE+SYNC_NEGO_DONE; 2175 pDCB->MaxNegoPeriod = pSRB->MsgInBuf[3]; 2176 /* Transfer period factor */ 2177 pDCB->SyncOffset = pSRB->MsgInBuf[4]; 2178 /* REQ/ACK offset */ 2179 for (bIndex = 0; bIndex < 7; bIndex++) { 2180 if (pSRB->MsgInBuf[3] <= 2181 dc395x_trm_clock_period[bIndex]) { 2182 break; 2183 } 2184 } 2185 pDCB->tinfo.goal.period = 2186 dc395x_trm_tinfo_sync_period[bIndex]; 2187 pDCB->tinfo.current.period = 2188 dc395x_trm_tinfo_sync_period[bIndex]; 2189 pDCB->tinfo.goal.offset = pDCB->SyncOffset; 2190 pDCB->tinfo.current.offset = pDCB->SyncOffset; 2191 pDCB->SyncPeriod |= (bIndex | ALT_SYNC); 2192 re_prog: 2193 /* 2194 * 2195 * program SCSI control register 2196 * 2197 */ 2198 trm_reg_write8(pDCB->SyncPeriod, 2199 TRMREG_SCSI_SYNC); 2200 trm_reg_write8(pDCB->SyncOffset, 2201 TRMREG_SCSI_OFFSET); 2202 trm_SetXferRate(pACB,pSRB,pDCB); 2203 } 2204 } 2205 } 2206 min6: 2207 *pscsi_status = PH_BUS_FREE; 2208 /* .. initial phase */ 2209 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2210 /* it's important for atn stop */ 2211 /* 2212 * SCSI cammand 2213 */ 2214 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2215 } 2216 2217 static void 2218 trm_MsgInPhase1(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 2219 { 2220 2221 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 2222 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 2223 if (!(pSRB->SRBState & SRB_MSGIN)) { 2224 pSRB->SRBState &= SRB_DISCONNECT; 2225 pSRB->SRBState |= SRB_MSGIN; 2226 } 2227 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2228 /* it's important for atn stop*/ 2229 /* 2230 * SCSI cammand 2231 */ 2232 trm_reg_write8(SCMD_FIFO_IN, TRMREG_SCSI_COMMAND); 2233 } 2234 2235 static void 2236 trm_Nop0(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 2237 { 2238 2239 } 2240 2241 static void 2242 trm_Nop1(PACB pACB, PSRB pSRB, u_int8_t *pscsi_status) 2243 { 2244 2245 } 2246 2247 static void 2248 trm_SetXferRate(PACB pACB,PSRB pSRB, PDCB pDCB) 2249 { 2250 u_int16_t cnt, i; 2251 u_int8_t bval; 2252 PDCB pDCBTemp; 2253 u_int target_id,target_lun; 2254 2255 /* 2256 * set all lun device's period , offset 2257 */ 2258 target_id = pSRB->pccb->ccb_h.target_id; 2259 target_lun = pSRB->pccb->ccb_h.target_lun; 2260 TRM_DPRINTF("trm_SetXferRate:target_id= %d ,target_lun= %d \n" 2261 ,target_id,target_lun); 2262 if (!(pDCB->IdentifyMsg & 0x07)) { 2263 if (!pACB->scan_devices[target_id][target_lun]) { 2264 pDCBTemp = pACB->pLinkDCB; 2265 cnt = pACB->DeviceCnt; 2266 bval = pDCB->TargetID; 2267 for (i = 0; i < cnt; i++) { 2268 if (pDCBTemp->TargetID == bval) { 2269 pDCBTemp->SyncPeriod = pDCB->SyncPeriod; 2270 pDCBTemp->SyncOffset = pDCB->SyncOffset; 2271 pDCBTemp->SyncMode = pDCB->SyncMode; 2272 } 2273 pDCBTemp = pDCBTemp->pNextDCB; 2274 } 2275 } 2276 } 2277 return; 2278 } 2279 2280 /* 2281 * scsiiom 2282 * trm_Interrupt 2283 * 2284 * 2285 * ---SCSI bus phase 2286 * 2287 * PH_DATA_OUT 0x00 Data out phase 2288 * PH_DATA_IN 0x01 Data in phase 2289 * PH_COMMAND 0x02 Command phase 2290 * PH_STATUS 0x03 Status phase 2291 * PH_BUS_FREE 0x04 Invalid phase used as bus free 2292 * PH_BUS_FREE 0x05 Invalid phase used as bus free 2293 * PH_MSG_OUT 0x06 Message out phase 2294 * PH_MSG_IN 0x07 Message in phase 2295 * 2296 */ 2297 static void 2298 trm_Disconnect(PACB pACB) 2299 { 2300 PDCB pDCB; 2301 PSRB pSRB, psrb; 2302 u_int16_t i,j, cnt; 2303 u_int8_t bval; 2304 u_int target_id,target_lun; 2305 2306 TRM_DPRINTF("trm_Disconnect...............\n "); 2307 2308 crit_enter(); 2309 pDCB = pACB->pActiveDCB; 2310 if (!pDCB) { 2311 TRM_DPRINTF(" Exception Disconnect DCB=NULL..............\n "); 2312 j = 400; 2313 while (--j) 2314 DELAY(1); 2315 /* 1 msec */ 2316 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), 2317 TRMREG_SCSI_CONTROL); 2318 crit_exit(); 2319 return; 2320 } 2321 pSRB = pDCB->pActiveSRB; 2322 /* bug pSRB=0 */ 2323 target_id = pSRB->pccb->ccb_h.target_id; 2324 target_lun = pSRB->pccb->ccb_h.target_lun; 2325 TRM_DPRINTF(":pDCB->pActiveSRB= %8x \n ",(u_int) pDCB->pActiveSRB); 2326 pACB->pActiveDCB = 0; 2327 pSRB->ScsiPhase = PH_BUS_FREE; 2328 /* SCSI bus free Phase */ 2329 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), TRMREG_SCSI_CONTROL); 2330 if (pSRB->SRBState & SRB_UNEXPECT_RESEL) { 2331 pSRB->SRBState = 0; 2332 trm_DoWaitingSRB(pACB); 2333 } else if (pSRB->SRBState & SRB_ABORT_SENT) { 2334 pDCB->TagMask = 0; 2335 pDCB->DCBFlag = 0; 2336 cnt = pDCB->GoingSRBCnt; 2337 pDCB->GoingSRBCnt = 0; 2338 pSRB = pDCB->pGoingSRB; 2339 for (i = 0; i < cnt; i++) { 2340 psrb = pSRB->pNextSRB; 2341 pSRB->pNextSRB = pACB->pFreeSRB; 2342 pACB->pFreeSRB = pSRB; 2343 pSRB = psrb; 2344 } 2345 pDCB->pGoingSRB = 0; 2346 trm_DoWaitingSRB(pACB); 2347 } else { 2348 if ((pSRB->SRBState & (SRB_START_+SRB_MSGOUT)) || 2349 !(pSRB->SRBState & (SRB_DISCONNECT+SRB_COMPLETED))) { 2350 /* Selection time out */ 2351 if (!(pACB->scan_devices[target_id][target_lun])) { 2352 pSRB->SRBState = SRB_READY; 2353 trm_RewaitSRB(pDCB, pSRB); 2354 } else { 2355 pSRB->TargetStatus = SCSI_STAT_SEL_TIMEOUT; 2356 goto disc1; 2357 } 2358 } else if (pSRB->SRBState & SRB_DISCONNECT) { 2359 /* 2360 * SRB_DISCONNECT 2361 */ 2362 trm_DoWaitingSRB(pACB); 2363 } else if (pSRB->SRBState & SRB_COMPLETED) { 2364 disc1: 2365 /* 2366 * SRB_COMPLETED 2367 */ 2368 if (pDCB->MaxCommand > 1) { 2369 bval = pSRB->TagNumber; 2370 pDCB->TagMask &= (~(1 << bval)); 2371 /* free tag mask */ 2372 } 2373 pDCB->pActiveSRB = 0; 2374 pSRB->SRBState = SRB_FREE; 2375 trm_SRBdone(pACB, pDCB, pSRB); 2376 } 2377 } 2378 crit_exit(); 2379 return; 2380 } 2381 2382 static void 2383 trm_Reselect(PACB pACB) 2384 { 2385 PDCB pDCB; 2386 PSRB pSRB; 2387 u_int16_t RselTarLunId; 2388 2389 TRM_DPRINTF("trm_Reselect................. \n"); 2390 pDCB = pACB->pActiveDCB; 2391 if (pDCB) { 2392 /* Arbitration lost but Reselection win */ 2393 pSRB = pDCB->pActiveSRB; 2394 pSRB->SRBState = SRB_READY; 2395 trm_RewaitSRB(pDCB, pSRB); 2396 } 2397 /* Read Reselected Target Id and LUN */ 2398 RselTarLunId = trm_reg_read16(TRMREG_SCSI_TARGETID) & 0x1FFF; 2399 pDCB = pACB->pLinkDCB; 2400 while (RselTarLunId != *((u_int16_t *) &pDCB->TargetID)) { 2401 /* get pDCB of the reselect id */ 2402 pDCB = pDCB->pNextDCB; 2403 } 2404 2405 pACB->pActiveDCB = pDCB; 2406 if (pDCB->SyncMode & EN_TAG_QUEUING) { 2407 pSRB = pACB->pTmpSRB; 2408 pDCB->pActiveSRB = pSRB; 2409 } else { 2410 pSRB = pDCB->pActiveSRB; 2411 if (!pSRB || !(pSRB->SRBState & SRB_DISCONNECT)) { 2412 /* 2413 * abort command 2414 */ 2415 pSRB = pACB->pTmpSRB; 2416 pSRB->SRBState = SRB_UNEXPECT_RESEL; 2417 pDCB->pActiveSRB = pSRB; 2418 trm_EnableMsgOutAbort1(pACB, pSRB); 2419 } else { 2420 if (pDCB->DCBFlag & ABORT_DEV_) { 2421 pSRB->SRBState = SRB_ABORT_SENT; 2422 trm_EnableMsgOutAbort1(pACB, pSRB); 2423 } else 2424 pSRB->SRBState = SRB_DATA_XFER; 2425 } 2426 } 2427 pSRB->ScsiPhase = PH_BUS_FREE; 2428 /* SCSI bus free Phase */ 2429 /* 2430 * Program HA ID, target ID, period and offset 2431 */ 2432 trm_reg_write8((u_int8_t) RselTarLunId,TRMREG_SCSI_TARGETID); 2433 /* target ID */ 2434 trm_reg_write8(pACB->AdaptSCSIID,TRMREG_SCSI_HOSTID); 2435 /* host ID */ 2436 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC); 2437 /* period */ 2438 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET); 2439 /* offset */ 2440 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2441 /* it's important for atn stop*/ 2442 /* 2443 * SCSI cammand 2444 */ 2445 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2446 /* to rls the /ACK signal */ 2447 } 2448 2449 static void 2450 trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB) 2451 { 2452 PSRB psrb; 2453 u_int8_t bval, bval1,status; 2454 union ccb *pccb; 2455 struct ccb_scsiio *pcsio; 2456 PSCSI_INQDATA ptr; 2457 u_int target_id,target_lun; 2458 PDCB pTempDCB; 2459 2460 pccb = pSRB->pccb; 2461 if (pccb == NULL) 2462 return; 2463 pcsio = &pccb->csio; 2464 target_id = pSRB->pccb->ccb_h.target_id; 2465 target_lun = pSRB->pccb->ccb_h.target_lun; 2466 if ((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2467 bus_dmasync_op_t op; 2468 if ((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 2469 op = BUS_DMASYNC_POSTREAD; 2470 else 2471 op = BUS_DMASYNC_POSTWRITE; 2472 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 2473 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 2474 } 2475 /* 2476 * 2477 * target status 2478 * 2479 */ 2480 status = pSRB->TargetStatus; 2481 pcsio->scsi_status=SCSI_STAT_GOOD; 2482 pccb->ccb_h.status = CAM_REQ_CMP; 2483 if (pSRB->SRBFlag & AUTO_REQSENSE) { 2484 /* 2485 * status of auto request sense 2486 */ 2487 pSRB->SRBFlag &= ~AUTO_REQSENSE; 2488 pSRB->AdaptStatus = 0; 2489 pSRB->TargetStatus = SCSI_STATUS_CHECK_COND; 2490 2491 if (status == SCSI_STATUS_CHECK_COND) { 2492 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2493 goto ckc_e; 2494 } 2495 *((u_long *) &(pSRB->CmdBlock[0])) = pSRB->Segment0[0]; 2496 *((u_long *) &(pSRB->CmdBlock[4])) = pSRB->Segment0[1]; 2497 pSRB->SRBTotalXferLength = pSRB->Segment1[1]; 2498 pSRB->SegmentX[0].address = pSRB->SgSenseTemp.address; 2499 pSRB->SegmentX[0].length = pSRB->SgSenseTemp.length; 2500 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2501 pccb->ccb_h.status = CAM_AUTOSNS_VALID; 2502 goto ckc_e; 2503 } 2504 /* 2505 * target status 2506 */ 2507 if (status) { 2508 if (status == SCSI_STATUS_CHECK_COND) { 2509 if ((pcsio->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) { 2510 TRM_DPRINTF("trm_RequestSense..................\n"); 2511 trm_RequestSense(pACB, pDCB, pSRB); 2512 return; 2513 } 2514 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2515 pccb->ccb_h.status = CAM_AUTOSNS_VALID | 2516 CAM_SCSI_STATUS_ERROR; 2517 goto ckc_e; 2518 } else if (status == SCSI_STAT_QUEUEFULL) { 2519 bval = (u_int8_t) pDCB->GoingSRBCnt; 2520 bval--; 2521 pDCB->MaxCommand = bval; 2522 trm_RewaitSRB(pDCB, pSRB); 2523 pSRB->AdaptStatus = 0; 2524 pSRB->TargetStatus = 0; 2525 pcsio->scsi_status = SCSI_STAT_QUEUEFULL; 2526 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2527 goto ckc_e; 2528 } else if (status == SCSI_STAT_SEL_TIMEOUT) { 2529 pSRB->AdaptStatus = H_SEL_TIMEOUT; 2530 pSRB->TargetStatus = 0; 2531 pcsio->scsi_status = SCSI_STAT_SEL_TIMEOUT; 2532 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2533 } else if (status == SCSI_STAT_BUSY) { 2534 TRM_DPRINTF("trm: target busy at %s %d\n", 2535 __FILE__, __LINE__); 2536 pcsio->scsi_status = SCSI_STAT_BUSY; 2537 pccb->ccb_h.status = CAM_SCSI_BUSY; 2538 /* The device busy, try again later? */ 2539 } else if (status == SCSI_STAT_RESCONFLICT) { 2540 TRM_DPRINTF("trm: target reserved at %s %d\n", 2541 __FILE__, __LINE__); 2542 pcsio->scsi_status = SCSI_STAT_RESCONFLICT; 2543 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; /*XXX*/ 2544 } else { 2545 pSRB->AdaptStatus = 0; 2546 if (pSRB->RetryCnt) { 2547 pSRB->RetryCnt--; 2548 pSRB->TargetStatus = 0; 2549 pSRB->SRBSGIndex = 0; 2550 pSRB->SRBSGListPointer = (PSEG) 2551 &pSRB->SegmentX[0]; 2552 if (trm_StartSCSI(pACB, pDCB, pSRB)) { 2553 /* 2554 * If trm_StartSCSI return 1 : 2555 * current interrupt status is interrupt 2556 * disreenable 2557 * It's said that SCSI processor has more 2558 * one SRB need to do 2559 */ 2560 trm_RewaitSRB(pDCB, pSRB); 2561 } 2562 return; 2563 } else { 2564 TRM_DPRINTF("trm: driver stuffup at %s %d\n", 2565 __FILE__, __LINE__); 2566 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2567 } 2568 } 2569 } else { 2570 /* 2571 * process initiator status.......................... 2572 * Adapter (initiator) status 2573 */ 2574 status = pSRB->AdaptStatus; 2575 if (status & H_OVER_UNDER_RUN) { 2576 pSRB->TargetStatus = 0; 2577 pccb->ccb_h.status = CAM_DATA_RUN_ERR; 2578 /* Illegal length (over/under run) */ 2579 } else if (pSRB->SRBStatus & PARITY_ERROR) { 2580 TRM_DPRINTF("trm: driver stuffup %s %d\n", 2581 __FILE__, __LINE__); 2582 pDCB->tinfo.goal.period = 0; 2583 pDCB->tinfo.goal.offset = 0; 2584 /* Driver failed to perform operation */ 2585 pccb->ccb_h.status = CAM_UNCOR_PARITY; 2586 } else { 2587 /* no error */ 2588 pSRB->AdaptStatus = 0; 2589 pSRB->TargetStatus = 0; 2590 pccb->ccb_h.status = CAM_REQ_CMP; 2591 /* there is no error, (sense is invalid) */ 2592 } 2593 } 2594 ckc_e: 2595 if (pACB->scan_devices[target_id][target_lun]) { 2596 /* 2597 * if SCSI command in "scan devices" duty 2598 */ 2599 if (pSRB->CmdBlock[0] == TEST_UNIT_READY) 2600 pACB->scan_devices[target_id][target_lun] = 0; 2601 /* SCSI command phase :test unit ready */ 2602 else if (pSRB->CmdBlock[0] == INQUIRY) { 2603 /* 2604 * SCSI command phase :inquiry scsi device data 2605 * (type,capacity,manufacture.... 2606 */ 2607 if (pccb->ccb_h.status == CAM_SEL_TIMEOUT) 2608 goto NO_DEV; 2609 ptr = (PSCSI_INQDATA) pcsio->data_ptr; 2610 /* page fault */ 2611 TRM_DPRINTF("trm_SRBdone..PSCSI_INQDATA:%2x \n", 2612 ptr->DevType); 2613 bval1 = ptr->DevType & SCSI_DEVTYPE; 2614 if (bval1 == SCSI_NODEV) { 2615 NO_DEV: 2616 TRM_DPRINTF("trm_SRBdone NO Device:target_id= %d ,target_lun= %d \n", 2617 target_id, 2618 target_lun); 2619 crit_enter(); 2620 pACB->scan_devices[target_id][target_lun] = 0; 2621 /* no device set scan device flag =0*/ 2622 /* pDCB Q link */ 2623 /* move the head of DCB to tempDCB*/ 2624 pTempDCB=pACB->pLinkDCB; 2625 /* search current DCB for pass link */ 2626 while (pTempDCB->pNextDCB != pDCB) { 2627 pTempDCB = pTempDCB->pNextDCB; 2628 } 2629 /* 2630 * when the current DCB found than connect 2631 * current DCB tail 2632 */ 2633 /* to the DCB tail that before current DCB */ 2634 pTempDCB->pNextDCB = pDCB->pNextDCB; 2635 /* 2636 * if there was only one DCB ,connect his tail 2637 * to his head 2638 */ 2639 if (pACB->pLinkDCB == pDCB) 2640 pACB->pLinkDCB = pTempDCB->pNextDCB; 2641 if (pACB->pDCBRunRobin == pDCB) 2642 pACB->pDCBRunRobin = pTempDCB->pNextDCB; 2643 pACB->DeviceCnt--; 2644 if (pACB->DeviceCnt == 0) { 2645 pACB->pLinkDCB = NULL; 2646 pACB->pDCBRunRobin = NULL; 2647 } 2648 crit_exit(); 2649 } else { 2650 #ifdef trm_DEBUG1 2651 int j; 2652 for (j = 0; j < 28; j++) { 2653 TRM_DPRINTF("ptr=%2x ", 2654 ((u_int8_t *)ptr)[j]); 2655 } 2656 #endif 2657 pDCB->DevType = bval1; 2658 if (bval1 == SCSI_DASD || 2659 bval1 == SCSI_OPTICAL) { 2660 if ((((ptr->Vers & 0x07) >= 2) || 2661 ((ptr->RDF & 0x0F) == 2)) && 2662 (ptr->Flags & SCSI_INQ_CMDQUEUE) && 2663 (pDCB->DevMode & TAG_QUEUING_) && 2664 (pDCB->DevMode & EN_DISCONNECT_)) { 2665 if (pDCB->DevMode & 2666 TAG_QUEUING_) { 2667 pDCB->MaxCommand = 2668 pACB->TagMaxNum; 2669 pDCB->SyncMode |= 2670 EN_TAG_QUEUING; 2671 pDCB->TagMask = 0; 2672 pDCB->tinfo.disc_tag |= 2673 TRM_CUR_TAGENB; 2674 } else { 2675 pDCB->SyncMode |= 2676 EN_ATN_STOP; 2677 pDCB->tinfo.disc_tag &= 2678 ~TRM_CUR_TAGENB; 2679 } 2680 } 2681 } 2682 } 2683 /* pSRB->CmdBlock[0] == INQUIRY */ 2684 } 2685 /* pACB->scan_devices[target_id][target_lun] */ 2686 } 2687 crit_enter(); 2688 /* ReleaseSRB(pDCB, pSRB); */ 2689 if (pSRB == pDCB->pGoingSRB) 2690 pDCB->pGoingSRB = pSRB->pNextSRB; 2691 else { 2692 psrb = pDCB->pGoingSRB; 2693 while (psrb->pNextSRB != pSRB) { 2694 psrb = psrb->pNextSRB; 2695 } 2696 psrb->pNextSRB = pSRB->pNextSRB; 2697 if (pSRB == pDCB->pGoingLastSRB) { 2698 pDCB->pGoingLastSRB = psrb; 2699 } 2700 } 2701 pSRB->pNextSRB = pACB->pFreeSRB; 2702 pACB->pFreeSRB = pSRB; 2703 pDCB->GoingSRBCnt--; 2704 trm_DoWaitingSRB(pACB); 2705 2706 crit_exit(); 2707 /* Notify cmd done */ 2708 xpt_done (pccb); 2709 } 2710 2711 static void 2712 trm_DoingSRB_Done(PACB pACB) 2713 { 2714 PDCB pDCB, pdcb; 2715 PSRB psrb, psrb2; 2716 u_int16_t cnt, i; 2717 union ccb *pccb; 2718 2719 pDCB = pACB->pLinkDCB; 2720 if (pDCB == NULL) 2721 return; 2722 pdcb = pDCB; 2723 do { 2724 cnt = pdcb->GoingSRBCnt; 2725 psrb = pdcb->pGoingSRB; 2726 for (i = 0; i < cnt; i++) { 2727 psrb2 = psrb->pNextSRB; 2728 pccb = psrb->pccb; 2729 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2730 /* ReleaseSRB(pDCB, pSRB); */ 2731 psrb->pNextSRB = pACB->pFreeSRB; 2732 pACB->pFreeSRB = psrb; 2733 xpt_done(pccb); 2734 psrb = psrb2; 2735 } 2736 pdcb->GoingSRBCnt = 0; 2737 pdcb->pGoingSRB = NULL; 2738 pdcb->TagMask = 0; 2739 pdcb = pdcb->pNextDCB; 2740 } 2741 while (pdcb != pDCB); 2742 } 2743 2744 static void 2745 trm_ResetSCSIBus(PACB pACB) 2746 { 2747 crit_enter(); 2748 pACB->ACBFlag |= RESET_DEV; 2749 2750 trm_reg_write16(DO_RSTSCSI,TRMREG_SCSI_CONTROL); 2751 while (!(trm_reg_read16(TRMREG_SCSI_INTSTATUS) & INT_SCSIRESET)); 2752 crit_exit(); 2753 return; 2754 } 2755 2756 static void 2757 trm_ScsiRstDetect(PACB pACB) 2758 { 2759 u_long wlval; 2760 2761 TRM_DPRINTF("trm_ScsiRstDetect \n"); 2762 wlval = 1000; 2763 while (--wlval) 2764 DELAY(1000); 2765 crit_enter(); 2766 trm_reg_write8(STOPDMAXFER,TRMREG_DMA_CONTROL); 2767 2768 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 2769 2770 if (pACB->ACBFlag & RESET_DEV) 2771 pACB->ACBFlag |= RESET_DONE; 2772 else { 2773 pACB->ACBFlag |= RESET_DETECT; 2774 trm_ResetDevParam(pACB); 2775 /* trm_DoingSRB_Done(pACB); ???? */ 2776 trm_RecoverSRB(pACB); 2777 pACB->pActiveDCB = NULL; 2778 pACB->ACBFlag = 0; 2779 trm_DoWaitingSRB(pACB); 2780 } 2781 crit_exit(); 2782 return; 2783 } 2784 2785 static void 2786 trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB) 2787 { 2788 union ccb *pccb; 2789 struct ccb_scsiio *pcsio; 2790 2791 pccb = pSRB->pccb; 2792 pcsio = &pccb->csio; 2793 2794 pSRB->SRBFlag |= AUTO_REQSENSE; 2795 pSRB->Segment0[0] = *((u_long *) &(pSRB->CmdBlock[0])); 2796 pSRB->Segment0[1] = *((u_long *) &(pSRB->CmdBlock[4])); 2797 pSRB->Segment1[0] = (u_long) ((pSRB->ScsiCmdLen << 8) + 2798 pSRB->SRBSGCount); 2799 pSRB->Segment1[1] = pSRB->SRBTotalXferLength; /* ?????????? */ 2800 2801 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2802 pSRB->AdaptStatus = 0; 2803 pSRB->TargetStatus = 0; 2804 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2805 2806 pSRB->SRBTotalXferLength = sizeof(pcsio->sense_data); 2807 pSRB->SgSenseTemp.address = pSRB->SegmentX[0].address; 2808 pSRB->SgSenseTemp.length = pSRB->SegmentX[0].length; 2809 pSRB->SegmentX[0].address = (u_long) vtophys(&pcsio->sense_data); 2810 pSRB->SegmentX[0].length = (u_long) pcsio->sense_len; 2811 pSRB->SRBSGListPointer = &pSRB->SegmentX[0]; 2812 pSRB->SRBSGCount = 1; 2813 pSRB->SRBSGIndex = 0; 2814 2815 *((u_long *) &(pSRB->CmdBlock[0])) = 0x00000003; 2816 pSRB->CmdBlock[1] = pDCB->IdentifyMsg << 5; 2817 *((u_int16_t *) &(pSRB->CmdBlock[4])) = pcsio->sense_len; 2818 pSRB->ScsiCmdLen = 6; 2819 2820 if (trm_StartSCSI(pACB, pDCB, pSRB)) 2821 /* 2822 * If trm_StartSCSI return 1 : 2823 * current interrupt status is interrupt disreenable 2824 * It's said that SCSI processor has more one SRB need to do 2825 */ 2826 trm_RewaitSRB(pDCB, pSRB); 2827 } 2828 2829 static void 2830 trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB) 2831 { 2832 2833 pSRB->MsgCnt = 1; 2834 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2835 } 2836 2837 static void 2838 trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB) 2839 { 2840 2841 pSRB->MsgOutBuf[0] = MSG_ABORT; 2842 trm_EnableMsgOutAbort2(pACB, pSRB); 2843 } 2844 2845 static void 2846 trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit,u_int32_t i,u_int32_t j) 2847 { 2848 PNVRAMTYPE pEEpromBuf; 2849 u_int8_t bval,PeriodIndex; 2850 u_int target_id,target_lun; 2851 PDCB pTempDCB; 2852 2853 target_id = i; 2854 target_lun = j; 2855 2856 crit_enter(); 2857 if (pACB->pLinkDCB == 0) { 2858 pACB->pLinkDCB = pDCB; 2859 /* 2860 * RunRobin impersonate the role 2861 * that let each device had good proportion 2862 * about SCSI command proceeding 2863 */ 2864 pACB->pDCBRunRobin = pDCB; 2865 pDCB->pNextDCB = pDCB; 2866 } else { 2867 pTempDCB=pACB->pLinkDCB; 2868 /* search the last nod of DCB link */ 2869 while (pTempDCB->pNextDCB != pACB->pLinkDCB) 2870 pTempDCB = pTempDCB->pNextDCB; 2871 /* connect current DCB with last DCB tail */ 2872 pTempDCB->pNextDCB = pDCB; 2873 /* connect current DCB tail to this DCB Q head */ 2874 pDCB->pNextDCB=pACB->pLinkDCB; 2875 } 2876 crit_exit(); 2877 2878 pACB->DeviceCnt++; 2879 pDCB->pDCBACB = pACB; 2880 pDCB->TargetID = target_id; 2881 pDCB->TargetLUN = target_lun; 2882 pDCB->pWaitingSRB = NULL; 2883 pDCB->pGoingSRB = NULL; 2884 pDCB->GoingSRBCnt = 0; 2885 pDCB->pActiveSRB = NULL; 2886 pDCB->TagMask = 0; 2887 pDCB->MaxCommand = 1; 2888 pDCB->DCBFlag = 0; 2889 /* $$$$$$$ */ 2890 pEEpromBuf = &trm_eepromBuf[unit]; 2891 pDCB->DevMode = pEEpromBuf->NvramTarget[target_id].NvmTarCfg0; 2892 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 2893 /* $$$$$$$ */ 2894 /* 2895 * disconnect enable ? 2896 */ 2897 if (pDCB->DevMode & NTC_DO_DISCONNECT) { 2898 bval = 0xC0; 2899 pDCB->tinfo.disc_tag |= TRM_USR_DISCENB ; 2900 } else { 2901 bval = 0x80; 2902 pDCB->tinfo.disc_tag &= ~(TRM_USR_DISCENB); 2903 } 2904 bval |= target_lun; 2905 pDCB->IdentifyMsg = bval; 2906 /* $$$$$$$ */ 2907 /* 2908 * tag Qing enable ? 2909 */ 2910 if (pDCB->DevMode & TAG_QUEUING_) { 2911 pDCB->tinfo.disc_tag |= TRM_USR_TAGENB ; 2912 } else 2913 pDCB->tinfo.disc_tag &= ~(TRM_USR_TAGENB); 2914 /* $$$$$$$ */ 2915 /* 2916 * wide nego ,sync nego enable ? 2917 */ 2918 pDCB->SyncPeriod = 0; 2919 pDCB->SyncOffset = 0; 2920 PeriodIndex = pEEpromBuf->NvramTarget[target_id].NvmTarPeriod & 0x07; 2921 pDCB->MaxNegoPeriod = dc395x_trm_clock_period[ PeriodIndex ] ; 2922 pDCB->SyncMode = 0; 2923 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 2924 (pACB->Config & HCC_WIDE_CARD)) 2925 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 2926 /* enable wide nego */ 2927 if (pDCB->DevMode & NTC_DO_SYNC_NEGO) 2928 pDCB->SyncMode |= SYNC_NEGO_ENABLE; 2929 /* enable sync nego */ 2930 /* $$$$$$$ */ 2931 /* 2932 * Fill in tinfo structure. 2933 */ 2934 pDCB->tinfo.user.period = pDCB->MaxNegoPeriod; 2935 pDCB->tinfo.user.offset = (pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 15 : 0; 2936 pDCB->tinfo.user.width = (pDCB->SyncMode & WIDE_NEGO_ENABLE) ? 2937 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT; 2938 2939 pDCB->tinfo.current.period = 0; 2940 pDCB->tinfo.current.offset = 0; 2941 pDCB->tinfo.current.width = MSG_EXT_WDTR_BUS_8_BIT; 2942 } 2943 2944 static void 2945 trm_initSRB(PSRB psrb) 2946 { 2947 2948 psrb->PhysSRB = vtophys(psrb); 2949 } 2950 2951 static void 2952 trm_linkSRB(PACB pACB) 2953 { 2954 u_int16_t i; 2955 2956 for (i = 0; i < MAX_SRB_CNT; i++) { 2957 if (i != MAX_SRB_CNT - 1) 2958 /* 2959 * link all SRB 2960 */ 2961 pACB->SRB_array[i].pNextSRB = &pACB->SRB_array[i+1]; 2962 else 2963 /* 2964 * load NULL to NextSRB of the last SRB 2965 */ 2966 pACB->SRB_array[i].pNextSRB = NULL; 2967 /* 2968 * convert and save physical address of SRB to pSRB->PhysSRB 2969 */ 2970 trm_initSRB((PSRB) &pACB->SRB_array[i]); 2971 } 2972 } 2973 2974 2975 static void 2976 trm_initACB(PACB pACB, u_int16_t unit) 2977 { 2978 PNVRAMTYPE pEEpromBuf; 2979 u_int16_t i,j; 2980 2981 pEEpromBuf = &trm_eepromBuf[unit]; 2982 pACB->max_id = 15; 2983 2984 if (pEEpromBuf->NvramChannelCfg & NAC_SCANLUN) 2985 pACB->max_lun = 7; 2986 else 2987 pACB->max_lun = 0; 2988 2989 TRM_DPRINTF("trm: pACB->max_id= %d pACB->max_lun= %d \n", 2990 pACB->max_id, pACB->max_lun); 2991 2992 pACB->pLinkDCB = NULL; 2993 pACB->pDCBRunRobin = NULL; 2994 pACB->pActiveDCB = NULL; 2995 pACB->pFreeSRB = pACB->SRB_array; 2996 pACB->AdapterUnit = unit; 2997 pACB->AdaptSCSIID = pEEpromBuf->NvramScsiId; 2998 pACB->AdaptSCSILUN = 0; 2999 pACB->DeviceCnt = 0; 3000 pACB->TagMaxNum = 2 << pEEpromBuf->NvramMaxTag ; 3001 pACB->ACBFlag = 0; 3002 /* 3003 * link all device's SRB Q of this adapter 3004 */ 3005 trm_linkSRB(pACB); 3006 /* 3007 * temp SRB for Q tag used or abord command used 3008 */ 3009 pACB->pTmpSRB = &pACB->TmpSRB; 3010 /* 3011 * convert and save physical address of SRB to pSRB->PhysSRB 3012 */ 3013 trm_initSRB(pACB->pTmpSRB); 3014 /* allocate DCB array for scan device */ 3015 for (i = 0; i < (pACB->max_id +1); i++) { 3016 if (pACB->AdaptSCSIID != i) { 3017 for (j = 0; j < (pACB->max_lun +1); j++) { 3018 pACB->scan_devices[i][j] = 1; 3019 pACB->pDCB[i][j]= (PDCB) kmalloc ( 3020 sizeof (struct _DCB), M_DEVBUF, M_WAITOK); 3021 trm_initDCB(pACB, 3022 pACB->pDCB[i][j], unit, i, j); 3023 TRM_DPRINTF("pDCB= %8x \n", 3024 (u_int)pACB->pDCB[i][j]); 3025 } 3026 } 3027 } 3028 TRM_DPRINTF("sizeof(struct _DCB)= %8x \n",sizeof(struct _DCB)); 3029 TRM_DPRINTF("sizeof(struct _ACB)= %8x \n",sizeof(struct _ACB)); 3030 TRM_DPRINTF("sizeof(struct _SRB)= %8x \n",sizeof(struct _SRB)); 3031 } 3032 3033 static void 3034 TRM_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB) 3035 { 3036 u_int8_t *bpEeprom = (u_int8_t *) pEEpromBuf; 3037 u_int8_t bAddr; 3038 3039 /* Enable SEEPROM */ 3040 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 3041 TRMREG_GEN_CONTROL); 3042 /* 3043 * Write enable 3044 */ 3045 TRM_write_cmd(pACB, 0x04, 0xFF); 3046 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3047 TRM_wait_30us(pACB); 3048 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) { 3049 TRM_set_data(pACB, bAddr, *bpEeprom); 3050 } 3051 /* 3052 * Write disable 3053 */ 3054 TRM_write_cmd(pACB, 0x04, 0x00); 3055 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 3056 TRM_wait_30us(pACB); 3057 /* Disable SEEPROM */ 3058 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 3059 TRMREG_GEN_CONTROL); 3060 return; 3061 } 3062 3063 static void 3064 TRM_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData) 3065 { 3066 int i; 3067 u_int8_t bSendData; 3068 /* 3069 * Send write command & address 3070 */ 3071 3072 TRM_write_cmd(pACB, 0x05, bAddr); 3073 /* 3074 * Write data 3075 */ 3076 for (i = 0; i < 8; i++, bData <<= 1) { 3077 bSendData = NVR_SELECT; 3078 if (bData & 0x80) 3079 /* Start from bit 7 */ 3080 bSendData |= NVR_BITOUT; 3081 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 3082 TRM_wait_30us(pACB); 3083 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3084 TRM_wait_30us(pACB); 3085 } 3086 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 3087 TRM_wait_30us(pACB); 3088 /* 3089 * Disable chip select 3090 */ 3091 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 3092 TRM_wait_30us(pACB); 3093 trm_reg_write8(NVR_SELECT ,TRMREG_GEN_NVRAM); 3094 TRM_wait_30us(pACB); 3095 /* 3096 * Wait for write ready 3097 */ 3098 while (1) { 3099 trm_reg_write8((NVR_SELECT | NVR_CLOCK), TRMREG_GEN_NVRAM); 3100 TRM_wait_30us(pACB); 3101 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 3102 TRM_wait_30us(pACB); 3103 if (trm_reg_read8(TRMREG_GEN_NVRAM) & NVR_BITIN) { 3104 break; 3105 } 3106 } 3107 /* 3108 * Disable chip select 3109 */ 3110 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3111 return; 3112 } 3113 3114 static void 3115 TRM_read_all(PNVRAMTYPE pEEpromBuf, PACB pACB) 3116 { 3117 u_int8_t *bpEeprom = (u_int8_t*) pEEpromBuf; 3118 u_int8_t bAddr; 3119 3120 /* 3121 * Enable SEEPROM 3122 */ 3123 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 3124 TRMREG_GEN_CONTROL); 3125 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) 3126 *bpEeprom = TRM_get_data(pACB, bAddr); 3127 /* 3128 * Disable SEEPROM 3129 */ 3130 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 3131 TRMREG_GEN_CONTROL); 3132 return; 3133 } 3134 3135 static u_int8_t 3136 TRM_get_data(PACB pACB, u_int8_t bAddr) 3137 { 3138 int i; 3139 u_int8_t bReadData, bData = 0; 3140 /* 3141 * Send read command & address 3142 */ 3143 3144 TRM_write_cmd(pACB, 0x06, bAddr); 3145 3146 for (i = 0; i < 8; i++) { 3147 /* 3148 * Read data 3149 */ 3150 trm_reg_write8((NVR_SELECT | NVR_CLOCK) , TRMREG_GEN_NVRAM); 3151 TRM_wait_30us(pACB); 3152 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 3153 /* 3154 * Get data bit while falling edge 3155 */ 3156 bReadData = trm_reg_read8(TRMREG_GEN_NVRAM); 3157 bData <<= 1; 3158 if (bReadData & NVR_BITIN) { 3159 bData |= 1; 3160 } 3161 TRM_wait_30us(pACB); 3162 } 3163 /* 3164 * Disable chip select 3165 */ 3166 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3167 return (bData); 3168 } 3169 3170 static void 3171 TRM_wait_30us(PACB pACB) 3172 { 3173 3174 /* ScsiPortStallExecution(30); wait 30 us */ 3175 trm_reg_write8(5, TRMREG_GEN_TIMER); 3176 while (!(trm_reg_read8(TRMREG_GEN_STATUS) & GTIMEOUT)); 3177 return; 3178 } 3179 3180 static void 3181 TRM_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr) 3182 { 3183 int i; 3184 u_int8_t bSendData; 3185 3186 for (i = 0; i < 3; i++, bCmd <<= 1) { 3187 /* 3188 * Program SB+OP code 3189 */ 3190 bSendData = NVR_SELECT; 3191 if (bCmd & 0x04) 3192 bSendData |= NVR_BITOUT; 3193 /* start from bit 2 */ 3194 trm_reg_write8(bSendData, TRMREG_GEN_NVRAM); 3195 TRM_wait_30us(pACB); 3196 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3197 TRM_wait_30us(pACB); 3198 } 3199 for (i = 0; i < 7; i++, bAddr <<= 1) { 3200 /* 3201 * Program address 3202 */ 3203 bSendData = NVR_SELECT; 3204 if (bAddr & 0x40) 3205 /* Start from bit 6 */ 3206 bSendData |= NVR_BITOUT; 3207 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 3208 TRM_wait_30us(pACB); 3209 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3210 TRM_wait_30us(pACB); 3211 } 3212 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 3213 TRM_wait_30us(pACB); 3214 } 3215 3216 static void 3217 trm_check_eeprom(PNVRAMTYPE pEEpromBuf, PACB pACB) 3218 { 3219 u_int16_t *wpEeprom = (u_int16_t *) pEEpromBuf; 3220 u_int16_t wAddr, wCheckSum; 3221 u_long dAddr, *dpEeprom; 3222 3223 TRM_read_all(pEEpromBuf,pACB); 3224 wCheckSum = 0; 3225 for (wAddr = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3226 wAddr < 64; wAddr++, wpEeprom++) { 3227 wCheckSum += *wpEeprom; 3228 } 3229 if (wCheckSum != 0x1234) { 3230 /* 3231 * Checksum error, load default 3232 */ 3233 pEEpromBuf->NvramSubVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3234 pEEpromBuf->NvramSubVendorID[1] = 3235 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3236 pEEpromBuf->NvramSubSysID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3237 pEEpromBuf->NvramSubSysID[1] = 3238 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3239 pEEpromBuf->NvramSubClass = 0x00; 3240 pEEpromBuf->NvramVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3241 pEEpromBuf->NvramVendorID[1] = 3242 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3243 pEEpromBuf->NvramDeviceID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3244 pEEpromBuf->NvramDeviceID[1] = 3245 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3246 pEEpromBuf->NvramReserved = 0x00; 3247 3248 for (dAddr = 0, dpEeprom = (u_long *) pEEpromBuf->NvramTarget; 3249 dAddr < 16; dAddr++, dpEeprom++) { 3250 *dpEeprom = 0x00000077; 3251 /* NvmTarCfg3,NvmTarCfg2,NvmTarPeriod,NvmTarCfg0 */ 3252 } 3253 3254 *dpEeprom++ = 0x04000F07; 3255 /* NvramMaxTag,NvramDelayTime,NvramChannelCfg,NvramScsiId */ 3256 *dpEeprom++ = 0x00000015; 3257 /* NvramReserved1,NvramBootLun,NvramBootTarget,NvramReserved0 */ 3258 for (dAddr = 0; dAddr < 12; dAddr++, dpEeprom++) 3259 *dpEeprom = 0x00; 3260 pEEpromBuf->NvramCheckSum = 0x00; 3261 for (wAddr = 0, wCheckSum = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3262 wAddr < 63; wAddr++, wpEeprom++) 3263 wCheckSum += *wpEeprom; 3264 *wpEeprom = 0x1234 - wCheckSum; 3265 TRM_write_all(pEEpromBuf,pACB); 3266 } 3267 return; 3268 } 3269 static int 3270 trm_initAdapter(PACB pACB, u_int16_t unit, device_t pci_config_id) 3271 { 3272 PNVRAMTYPE pEEpromBuf; 3273 u_int16_t wval; 3274 u_int8_t bval; 3275 3276 pEEpromBuf = &trm_eepromBuf[unit]; 3277 3278 /* 250ms selection timeout */ 3279 trm_reg_write8(SEL_TIMEOUT, TRMREG_SCSI_TIMEOUT); 3280 /* Mask all the interrupt */ 3281 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 3282 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 3283 /* Reset SCSI module */ 3284 trm_reg_write16(DO_RSTMODULE, TRMREG_SCSI_CONTROL); 3285 /* program configuration 0 */ 3286 pACB->Config = HCC_AUTOTERM | HCC_PARITY; 3287 if (trm_reg_read8(TRMREG_GEN_STATUS) & WIDESCSI) 3288 pACB->Config |= HCC_WIDE_CARD; 3289 if (pEEpromBuf->NvramChannelCfg & NAC_POWERON_SCSI_RESET) 3290 pACB->Config |= HCC_SCSI_RESET; 3291 if (pACB->Config & HCC_PARITY) 3292 bval = PHASELATCH | INITIATOR | BLOCKRST | PARITYCHECK; 3293 else 3294 bval = PHASELATCH | INITIATOR | BLOCKRST ; 3295 trm_reg_write8(bval,TRMREG_SCSI_CONFIG0); 3296 /* program configuration 1 */ 3297 trm_reg_write8(0x13, TRMREG_SCSI_CONFIG1); 3298 /* program Host ID */ 3299 bval = pEEpromBuf->NvramScsiId; 3300 trm_reg_write8(bval, TRMREG_SCSI_HOSTID); 3301 /* set ansynchronous transfer */ 3302 trm_reg_write8(0x00, TRMREG_SCSI_OFFSET); 3303 /* Trun LED control off*/ 3304 wval = trm_reg_read16(TRMREG_GEN_CONTROL) & 0x7F; 3305 trm_reg_write16(wval, TRMREG_GEN_CONTROL); 3306 /* DMA config */ 3307 wval = trm_reg_read16(TRMREG_DMA_CONFIG) | DMA_ENHANCE; 3308 trm_reg_write16(wval, TRMREG_DMA_CONFIG); 3309 /* Clear pending interrupt status */ 3310 trm_reg_read8(TRMREG_SCSI_INTSTATUS); 3311 /* Enable SCSI interrupt */ 3312 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 3313 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 3314 return (0); 3315 } 3316 3317 static PACB 3318 trm_init(u_int16_t unit, device_t pci_config_id) 3319 { 3320 PACB pACB; 3321 int rid = PCIR_MAPS; 3322 3323 pACB = (PACB) device_get_softc(pci_config_id); 3324 if (!pACB) { 3325 kprintf("trm%d: cannot allocate ACB !\n", unit); 3326 return (NULL); 3327 } 3328 bzero (pACB, sizeof (struct _ACB)); 3329 pACB->iores = bus_alloc_resource(pci_config_id, SYS_RES_IOPORT, 3330 &rid, 0, ~0, 1, RF_ACTIVE); 3331 if (pACB->iores == NULL) { 3332 kprintf("trm_init: bus_alloc_resource failed!\n"); 3333 return (NULL); 3334 } 3335 pACB->tag = rman_get_bustag(pACB->iores); 3336 pACB->bsh = rman_get_bushandle(pACB->iores); 3337 if (bus_dma_tag_create(/*parent_dmat*/ NULL, 3338 /*alignment*/ 1, 3339 /*boundary*/ 0, 3340 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 3341 /*highaddr*/ BUS_SPACE_MAXADDR, 3342 /*filter*/ NULL, 3343 /*filterarg*/ NULL, 3344 /*maxsize*/ MAXBSIZE, 3345 /*nsegments*/ TRM_NSEG, 3346 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3347 /*flags*/ BUS_DMA_ALLOCNOW, 3348 &pACB->buffer_dmat) != 0) 3349 goto bad; 3350 trm_check_eeprom(&trm_eepromBuf[unit],pACB); 3351 trm_initACB(pACB, unit); 3352 if (trm_initAdapter(pACB, unit, pci_config_id)) { 3353 kprintf("trm_initAdapter: initial ERROR\n"); 3354 goto bad; 3355 } 3356 return (pACB); 3357 bad: 3358 if (pACB->iores) 3359 bus_release_resource(pci_config_id, SYS_RES_IOPORT, PCIR_MAPS, 3360 pACB->iores); 3361 if (pACB->buffer_dmat) 3362 bus_dma_tag_destroy(pACB->buffer_dmat); 3363 return (NULL); 3364 } 3365 3366 static int 3367 trm_attach(device_t pci_config_id) 3368 { 3369 struct cam_devq *device_Q; 3370 u_long device_id; 3371 PACB pACB = 0; 3372 int rid = 0; 3373 int unit = device_get_unit(pci_config_id); 3374 3375 device_id = pci_get_devid(pci_config_id); 3376 /* 3377 * These cards do not allow memory mapped accesses 3378 */ 3379 if (device_id == PCI_DEVICEID_TRMS1040) { 3380 if ((pACB=trm_init((u_int16_t) unit, 3381 pci_config_id)) == NULL) { 3382 kprintf("trm%d: trm_init error!\n",unit); 3383 return (ENXIO); 3384 } 3385 } else 3386 return (ENXIO); 3387 /* After setting up the adapter, map our interrupt */ 3388 /* 3389 * Now let the CAM generic SCSI layer find the SCSI devices on the bus 3390 * start queue to reset to the idle loop. 3391 * Create device queue of SIM(s) 3392 * (MAX_START_JOB - 1) : max_sim_transactions 3393 */ 3394 pACB->irq = bus_alloc_resource(pci_config_id, SYS_RES_IRQ, &rid, 0, 3395 ~0, 1, RF_SHAREABLE | RF_ACTIVE); 3396 if (pACB->irq == NULL || 3397 bus_setup_intr(pci_config_id, pACB->irq, 3398 0, trm_Interrupt, pACB, 3399 &pACB->ih, NULL)) { 3400 kprintf("trm%d: register Interrupt handler error!\n", unit); 3401 goto bad; 3402 } 3403 device_Q = cam_simq_alloc(MAX_START_JOB); 3404 if (device_Q == NULL){ 3405 kprintf("trm%d: device_Q == NULL !\n",unit); 3406 goto bad; 3407 } 3408 /* 3409 * Now tell the generic SCSI layer 3410 * about our bus. 3411 * If this is the xpt layer creating a sim, then it's OK 3412 * to wait for an allocation. 3413 * XXX Should we pass in a flag to indicate that wait is OK? 3414 * 3415 * SIM allocation 3416 * 3417 * SCSI Interface Modules 3418 * The sim driver creates a sim for each controller. The sim device 3419 * queue is separately created in order to allow resource sharing betwee 3420 * sims. For instance, a driver may create one sim for each channel of 3421 * a multi-channel controller and use the same queue for each channel. 3422 * In this way, the queue resources are shared across all the channels 3423 * of the multi-channel controller. 3424 * trm_action : sim_action_func 3425 * trm_poll : sim_poll_func 3426 * "trm" : sim_name ,if sim_name = "xpt" ..M_DEVBUF,M_WAITOK 3427 * pACB : *softc if sim_name <> "xpt" ..M_DEVBUF,M_NOWAIT 3428 * pACB->unit : unit 3429 * 1 : max_dev_transactions 3430 * MAX_TAGS : max_tagged_dev_transactions 3431 * 3432 * *******Construct our first channel SIM entry 3433 */ 3434 pACB->psim = cam_sim_alloc(trm_action, 3435 trm_poll, 3436 "trm", 3437 pACB, 3438 unit, 3439 1, 3440 MAX_TAGS_CMD_QUEUE, 3441 device_Q); 3442 cam_simq_release(device_Q); /* SIM allocate fault*/ 3443 if (pACB->psim == NULL) { 3444 kprintf("trm%d: SIM allocate fault !\n",unit); 3445 goto bad; 3446 } 3447 if (xpt_bus_register(pACB->psim, 0) != CAM_SUCCESS) { 3448 kprintf("trm%d: xpt_bus_register fault !\n",unit); 3449 goto bad; 3450 } 3451 if (xpt_create_path(&pACB->ppath, 3452 NULL, 3453 cam_sim_path(pACB->psim), 3454 CAM_TARGET_WILDCARD, 3455 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 3456 kprintf("trm%d: xpt_create_path fault !\n",unit); 3457 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3458 goto bad; 3459 /* 3460 * cam_sim_free(pACB->psim, TRUE); free_devq 3461 * pACB->psim = NULL; 3462 */ 3463 return (ENXIO); 3464 } 3465 return (0); 3466 bad: 3467 if (pACB->iores) 3468 bus_release_resource(pci_config_id, SYS_RES_IOPORT, PCIR_MAPS, 3469 pACB->iores); 3470 if (pACB->buffer_dmat) 3471 bus_dma_tag_destroy(pACB->buffer_dmat); 3472 if (pACB->ih) 3473 bus_teardown_intr(pci_config_id, pACB->irq, pACB->ih); 3474 if (pACB->irq) 3475 bus_release_resource(pci_config_id, SYS_RES_IRQ, 0, pACB->irq); 3476 if (pACB->psim) 3477 cam_sim_free(pACB->psim); 3478 3479 return (ENXIO); 3480 3481 } 3482 3483 /* 3484 * pci_device 3485 * trm_probe (device_t tag, pcidi_t type) 3486 * 3487 */ 3488 static int 3489 trm_probe(device_t tag) 3490 { 3491 3492 if (pci_get_devid(tag) == PCI_DEVICEID_TRMS1040) { 3493 device_set_desc(tag, 3494 "Tekram DC395U/UW/F DC315/U Fast20 Wide SCSI Adapter"); 3495 return (0); 3496 } else 3497 return (ENXIO); 3498 } 3499 3500 static int 3501 trm_detach(device_t dev) 3502 { 3503 PACB pACB = device_get_softc(dev); 3504 3505 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS, pACB->iores); 3506 bus_dma_tag_destroy(pACB->buffer_dmat); 3507 bus_teardown_intr(dev, pACB->irq, pACB->ih); 3508 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq); 3509 xpt_async(AC_LOST_DEVICE, pACB->ppath, NULL); 3510 xpt_free_path(pACB->ppath); 3511 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3512 cam_sim_free(pACB->psim); 3513 return (0); 3514 } 3515 static device_method_t trm_methods[] = { 3516 /* Device interface */ 3517 DEVMETHOD(device_probe, trm_probe), 3518 DEVMETHOD(device_attach, trm_attach), 3519 DEVMETHOD(device_detach, trm_detach), 3520 { 0, 0 } 3521 }; 3522 3523 static driver_t trm_driver = { 3524 "trm", trm_methods, sizeof(struct _ACB) 3525 }; 3526 3527 static devclass_t trm_devclass; 3528 DRIVER_MODULE(trm, pci, trm_driver, trm_devclass, 0, 0); 3529