1*b843c749SSergey Zigachev /*
2*b843c749SSergey Zigachev * Copyright 2015 Advanced Micro Devices, Inc.
3*b843c749SSergey Zigachev *
4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a
5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"),
6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation
7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the
9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions:
10*b843c749SSergey Zigachev *
11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in
12*b843c749SSergey Zigachev * all copies or substantial portions of the Software.
13*b843c749SSergey Zigachev *
14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE.
21*b843c749SSergey Zigachev *
22*b843c749SSergey Zigachev * Authors: AMD
23*b843c749SSergey Zigachev *
24*b843c749SSergey Zigachev */
25*b843c749SSergey Zigachev
26*b843c749SSergey Zigachev #include <linux/irqdomain.h>
27*b843c749SSergey Zigachev #include <linux/pm_domain.h>
28*b843c749SSergey Zigachev #include <linux/platform_device.h>
29*b843c749SSergey Zigachev #include <sound/designware_i2s.h>
30*b843c749SSergey Zigachev #include <sound/pcm.h>
31*b843c749SSergey Zigachev
32*b843c749SSergey Zigachev #include "amdgpu.h"
33*b843c749SSergey Zigachev #include "atom.h"
34*b843c749SSergey Zigachev #include "amdgpu_acp.h"
35*b843c749SSergey Zigachev
36*b843c749SSergey Zigachev #include "acp_gfx_if.h"
37*b843c749SSergey Zigachev
38*b843c749SSergey Zigachev #define ACP_TILE_ON_MASK 0x03
39*b843c749SSergey Zigachev #define ACP_TILE_OFF_MASK 0x02
40*b843c749SSergey Zigachev #define ACP_TILE_ON_RETAIN_REG_MASK 0x1f
41*b843c749SSergey Zigachev #define ACP_TILE_OFF_RETAIN_REG_MASK 0x20
42*b843c749SSergey Zigachev
43*b843c749SSergey Zigachev #define ACP_TILE_P1_MASK 0x3e
44*b843c749SSergey Zigachev #define ACP_TILE_P2_MASK 0x3d
45*b843c749SSergey Zigachev #define ACP_TILE_DSP0_MASK 0x3b
46*b843c749SSergey Zigachev #define ACP_TILE_DSP1_MASK 0x37
47*b843c749SSergey Zigachev
48*b843c749SSergey Zigachev #define ACP_TILE_DSP2_MASK 0x2f
49*b843c749SSergey Zigachev
50*b843c749SSergey Zigachev #define ACP_DMA_REGS_END 0x146c0
51*b843c749SSergey Zigachev #define ACP_I2S_PLAY_REGS_START 0x14840
52*b843c749SSergey Zigachev #define ACP_I2S_PLAY_REGS_END 0x148b4
53*b843c749SSergey Zigachev #define ACP_I2S_CAP_REGS_START 0x148b8
54*b843c749SSergey Zigachev #define ACP_I2S_CAP_REGS_END 0x1496c
55*b843c749SSergey Zigachev
56*b843c749SSergey Zigachev #define ACP_I2S_COMP1_CAP_REG_OFFSET 0xac
57*b843c749SSergey Zigachev #define ACP_I2S_COMP2_CAP_REG_OFFSET 0xa8
58*b843c749SSergey Zigachev #define ACP_I2S_COMP1_PLAY_REG_OFFSET 0x6c
59*b843c749SSergey Zigachev #define ACP_I2S_COMP2_PLAY_REG_OFFSET 0x68
60*b843c749SSergey Zigachev #define ACP_BT_PLAY_REGS_START 0x14970
61*b843c749SSergey Zigachev #define ACP_BT_PLAY_REGS_END 0x14a24
62*b843c749SSergey Zigachev #define ACP_BT_COMP1_REG_OFFSET 0xac
63*b843c749SSergey Zigachev #define ACP_BT_COMP2_REG_OFFSET 0xa8
64*b843c749SSergey Zigachev
65*b843c749SSergey Zigachev #define mmACP_PGFSM_RETAIN_REG 0x51c9
66*b843c749SSergey Zigachev #define mmACP_PGFSM_CONFIG_REG 0x51ca
67*b843c749SSergey Zigachev #define mmACP_PGFSM_READ_REG_0 0x51cc
68*b843c749SSergey Zigachev
69*b843c749SSergey Zigachev #define mmACP_MEM_SHUT_DOWN_REQ_LO 0x51f8
70*b843c749SSergey Zigachev #define mmACP_MEM_SHUT_DOWN_REQ_HI 0x51f9
71*b843c749SSergey Zigachev #define mmACP_MEM_SHUT_DOWN_STS_LO 0x51fa
72*b843c749SSergey Zigachev #define mmACP_MEM_SHUT_DOWN_STS_HI 0x51fb
73*b843c749SSergey Zigachev
74*b843c749SSergey Zigachev #define mmACP_CONTROL 0x5131
75*b843c749SSergey Zigachev #define mmACP_STATUS 0x5133
76*b843c749SSergey Zigachev #define mmACP_SOFT_RESET 0x5134
77*b843c749SSergey Zigachev #define ACP_CONTROL__ClkEn_MASK 0x1
78*b843c749SSergey Zigachev #define ACP_SOFT_RESET__SoftResetAud_MASK 0x100
79*b843c749SSergey Zigachev #define ACP_SOFT_RESET__SoftResetAudDone_MASK 0x1000000
80*b843c749SSergey Zigachev #define ACP_CLOCK_EN_TIME_OUT_VALUE 0x000000FF
81*b843c749SSergey Zigachev #define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE 0x000000FF
82*b843c749SSergey Zigachev
83*b843c749SSergey Zigachev #define ACP_TIMEOUT_LOOP 0x000000FF
84*b843c749SSergey Zigachev #define ACP_DEVS 4
85*b843c749SSergey Zigachev #define ACP_SRC_ID 162
86*b843c749SSergey Zigachev
87*b843c749SSergey Zigachev enum {
88*b843c749SSergey Zigachev ACP_TILE_P1 = 0,
89*b843c749SSergey Zigachev ACP_TILE_P2,
90*b843c749SSergey Zigachev ACP_TILE_DSP0,
91*b843c749SSergey Zigachev ACP_TILE_DSP1,
92*b843c749SSergey Zigachev ACP_TILE_DSP2,
93*b843c749SSergey Zigachev };
94*b843c749SSergey Zigachev
acp_sw_init(void * handle)95*b843c749SSergey Zigachev static int acp_sw_init(void *handle)
96*b843c749SSergey Zigachev {
97*b843c749SSergey Zigachev struct amdgpu_device *adev = (struct amdgpu_device *)handle;
98*b843c749SSergey Zigachev
99*b843c749SSergey Zigachev adev->acp.parent = adev->dev;
100*b843c749SSergey Zigachev
101*b843c749SSergey Zigachev adev->acp.cgs_device =
102*b843c749SSergey Zigachev amdgpu_cgs_create_device(adev);
103*b843c749SSergey Zigachev if (!adev->acp.cgs_device)
104*b843c749SSergey Zigachev return -EINVAL;
105*b843c749SSergey Zigachev
106*b843c749SSergey Zigachev return 0;
107*b843c749SSergey Zigachev }
108*b843c749SSergey Zigachev
acp_sw_fini(void * handle)109*b843c749SSergey Zigachev static int acp_sw_fini(void *handle)
110*b843c749SSergey Zigachev {
111*b843c749SSergey Zigachev struct amdgpu_device *adev = (struct amdgpu_device *)handle;
112*b843c749SSergey Zigachev
113*b843c749SSergey Zigachev if (adev->acp.cgs_device)
114*b843c749SSergey Zigachev amdgpu_cgs_destroy_device(adev->acp.cgs_device);
115*b843c749SSergey Zigachev
116*b843c749SSergey Zigachev return 0;
117*b843c749SSergey Zigachev }
118*b843c749SSergey Zigachev
119*b843c749SSergey Zigachev /* power off a tile/block within ACP */
acp_suspend_tile(void * cgs_dev,int tile)120*b843c749SSergey Zigachev static int acp_suspend_tile(void *cgs_dev, int tile)
121*b843c749SSergey Zigachev {
122*b843c749SSergey Zigachev u32 val = 0;
123*b843c749SSergey Zigachev u32 count = 0;
124*b843c749SSergey Zigachev
125*b843c749SSergey Zigachev if ((tile < ACP_TILE_P1) || (tile > ACP_TILE_DSP2)) {
126*b843c749SSergey Zigachev pr_err("Invalid ACP tile : %d to suspend\n", tile);
127*b843c749SSergey Zigachev return -1;
128*b843c749SSergey Zigachev }
129*b843c749SSergey Zigachev
130*b843c749SSergey Zigachev val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 + tile);
131*b843c749SSergey Zigachev val &= ACP_TILE_ON_MASK;
132*b843c749SSergey Zigachev
133*b843c749SSergey Zigachev if (val == 0x0) {
134*b843c749SSergey Zigachev val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG);
135*b843c749SSergey Zigachev val = val | (1 << tile);
136*b843c749SSergey Zigachev cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val);
137*b843c749SSergey Zigachev cgs_write_register(cgs_dev, mmACP_PGFSM_CONFIG_REG,
138*b843c749SSergey Zigachev 0x500 + tile);
139*b843c749SSergey Zigachev
140*b843c749SSergey Zigachev count = ACP_TIMEOUT_LOOP;
141*b843c749SSergey Zigachev while (true) {
142*b843c749SSergey Zigachev val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0
143*b843c749SSergey Zigachev + tile);
144*b843c749SSergey Zigachev val = val & ACP_TILE_ON_MASK;
145*b843c749SSergey Zigachev if (val == ACP_TILE_OFF_MASK)
146*b843c749SSergey Zigachev break;
147*b843c749SSergey Zigachev if (--count == 0) {
148*b843c749SSergey Zigachev pr_err("Timeout reading ACP PGFSM status\n");
149*b843c749SSergey Zigachev return -ETIMEDOUT;
150*b843c749SSergey Zigachev }
151*b843c749SSergey Zigachev udelay(100);
152*b843c749SSergey Zigachev }
153*b843c749SSergey Zigachev
154*b843c749SSergey Zigachev val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG);
155*b843c749SSergey Zigachev
156*b843c749SSergey Zigachev val |= ACP_TILE_OFF_RETAIN_REG_MASK;
157*b843c749SSergey Zigachev cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val);
158*b843c749SSergey Zigachev }
159*b843c749SSergey Zigachev return 0;
160*b843c749SSergey Zigachev }
161*b843c749SSergey Zigachev
162*b843c749SSergey Zigachev /* power on a tile/block within ACP */
acp_resume_tile(void * cgs_dev,int tile)163*b843c749SSergey Zigachev static int acp_resume_tile(void *cgs_dev, int tile)
164*b843c749SSergey Zigachev {
165*b843c749SSergey Zigachev u32 val = 0;
166*b843c749SSergey Zigachev u32 count = 0;
167*b843c749SSergey Zigachev
168*b843c749SSergey Zigachev if ((tile < ACP_TILE_P1) || (tile > ACP_TILE_DSP2)) {
169*b843c749SSergey Zigachev pr_err("Invalid ACP tile to resume\n");
170*b843c749SSergey Zigachev return -1;
171*b843c749SSergey Zigachev }
172*b843c749SSergey Zigachev
173*b843c749SSergey Zigachev val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 + tile);
174*b843c749SSergey Zigachev val = val & ACP_TILE_ON_MASK;
175*b843c749SSergey Zigachev
176*b843c749SSergey Zigachev if (val != 0x0) {
177*b843c749SSergey Zigachev cgs_write_register(cgs_dev, mmACP_PGFSM_CONFIG_REG,
178*b843c749SSergey Zigachev 0x600 + tile);
179*b843c749SSergey Zigachev count = ACP_TIMEOUT_LOOP;
180*b843c749SSergey Zigachev while (true) {
181*b843c749SSergey Zigachev val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0
182*b843c749SSergey Zigachev + tile);
183*b843c749SSergey Zigachev val = val & ACP_TILE_ON_MASK;
184*b843c749SSergey Zigachev if (val == 0x0)
185*b843c749SSergey Zigachev break;
186*b843c749SSergey Zigachev if (--count == 0) {
187*b843c749SSergey Zigachev pr_err("Timeout reading ACP PGFSM status\n");
188*b843c749SSergey Zigachev return -ETIMEDOUT;
189*b843c749SSergey Zigachev }
190*b843c749SSergey Zigachev udelay(100);
191*b843c749SSergey Zigachev }
192*b843c749SSergey Zigachev val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG);
193*b843c749SSergey Zigachev if (tile == ACP_TILE_P1)
194*b843c749SSergey Zigachev val = val & (ACP_TILE_P1_MASK);
195*b843c749SSergey Zigachev else if (tile == ACP_TILE_P2)
196*b843c749SSergey Zigachev val = val & (ACP_TILE_P2_MASK);
197*b843c749SSergey Zigachev
198*b843c749SSergey Zigachev cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val);
199*b843c749SSergey Zigachev }
200*b843c749SSergey Zigachev return 0;
201*b843c749SSergey Zigachev }
202*b843c749SSergey Zigachev
203*b843c749SSergey Zigachev struct acp_pm_domain {
204*b843c749SSergey Zigachev void *cgs_dev;
205*b843c749SSergey Zigachev struct generic_pm_domain gpd;
206*b843c749SSergey Zigachev };
207*b843c749SSergey Zigachev
acp_poweroff(struct generic_pm_domain * genpd)208*b843c749SSergey Zigachev static int acp_poweroff(struct generic_pm_domain *genpd)
209*b843c749SSergey Zigachev {
210*b843c749SSergey Zigachev int i, ret;
211*b843c749SSergey Zigachev struct acp_pm_domain *apd;
212*b843c749SSergey Zigachev
213*b843c749SSergey Zigachev apd = container_of(genpd, struct acp_pm_domain, gpd);
214*b843c749SSergey Zigachev if (apd != NULL) {
215*b843c749SSergey Zigachev /* Donot return abruptly if any of power tile fails to suspend.
216*b843c749SSergey Zigachev * Log it and continue powering off other tile
217*b843c749SSergey Zigachev */
218*b843c749SSergey Zigachev for (i = 4; i >= 0 ; i--) {
219*b843c749SSergey Zigachev ret = acp_suspend_tile(apd->cgs_dev, ACP_TILE_P1 + i);
220*b843c749SSergey Zigachev if (ret)
221*b843c749SSergey Zigachev pr_err("ACP tile %d tile suspend failed\n", i);
222*b843c749SSergey Zigachev }
223*b843c749SSergey Zigachev }
224*b843c749SSergey Zigachev return 0;
225*b843c749SSergey Zigachev }
226*b843c749SSergey Zigachev
acp_poweron(struct generic_pm_domain * genpd)227*b843c749SSergey Zigachev static int acp_poweron(struct generic_pm_domain *genpd)
228*b843c749SSergey Zigachev {
229*b843c749SSergey Zigachev int i, ret;
230*b843c749SSergey Zigachev struct acp_pm_domain *apd;
231*b843c749SSergey Zigachev
232*b843c749SSergey Zigachev apd = container_of(genpd, struct acp_pm_domain, gpd);
233*b843c749SSergey Zigachev if (apd != NULL) {
234*b843c749SSergey Zigachev for (i = 0; i < 2; i++) {
235*b843c749SSergey Zigachev ret = acp_resume_tile(apd->cgs_dev, ACP_TILE_P1 + i);
236*b843c749SSergey Zigachev if (ret) {
237*b843c749SSergey Zigachev pr_err("ACP tile %d resume failed\n", i);
238*b843c749SSergey Zigachev break;
239*b843c749SSergey Zigachev }
240*b843c749SSergey Zigachev }
241*b843c749SSergey Zigachev
242*b843c749SSergey Zigachev /* Disable DSPs which are not going to be used */
243*b843c749SSergey Zigachev for (i = 0; i < 3; i++) {
244*b843c749SSergey Zigachev ret = acp_suspend_tile(apd->cgs_dev, ACP_TILE_DSP0 + i);
245*b843c749SSergey Zigachev /* Continue suspending other DSP, even if one fails */
246*b843c749SSergey Zigachev if (ret)
247*b843c749SSergey Zigachev pr_err("ACP DSP %d suspend failed\n", i);
248*b843c749SSergey Zigachev }
249*b843c749SSergey Zigachev }
250*b843c749SSergey Zigachev return 0;
251*b843c749SSergey Zigachev }
252*b843c749SSergey Zigachev
get_mfd_cell_dev(const char * device_name,int r)253*b843c749SSergey Zigachev static struct device *get_mfd_cell_dev(const char *device_name, int r)
254*b843c749SSergey Zigachev {
255*b843c749SSergey Zigachev char auto_dev_name[25];
256*b843c749SSergey Zigachev struct device *dev;
257*b843c749SSergey Zigachev
258*b843c749SSergey Zigachev snprintf(auto_dev_name, sizeof(auto_dev_name),
259*b843c749SSergey Zigachev "%s.%d.auto", device_name, r);
260*b843c749SSergey Zigachev dev = bus_find_device_by_name(&platform_bus_type, NULL, auto_dev_name);
261*b843c749SSergey Zigachev dev_info(dev, "device %s added to pm domain\n", auto_dev_name);
262*b843c749SSergey Zigachev
263*b843c749SSergey Zigachev return dev;
264*b843c749SSergey Zigachev }
265*b843c749SSergey Zigachev
266*b843c749SSergey Zigachev /**
267*b843c749SSergey Zigachev * acp_hw_init - start and test ACP block
268*b843c749SSergey Zigachev *
269*b843c749SSergey Zigachev * @adev: amdgpu_device pointer
270*b843c749SSergey Zigachev *
271*b843c749SSergey Zigachev */
acp_hw_init(void * handle)272*b843c749SSergey Zigachev static int acp_hw_init(void *handle)
273*b843c749SSergey Zigachev {
274*b843c749SSergey Zigachev int r, i;
275*b843c749SSergey Zigachev uint64_t acp_base;
276*b843c749SSergey Zigachev u32 val = 0;
277*b843c749SSergey Zigachev u32 count = 0;
278*b843c749SSergey Zigachev struct device *dev;
279*b843c749SSergey Zigachev struct i2s_platform_data *i2s_pdata = NULL;
280*b843c749SSergey Zigachev
281*b843c749SSergey Zigachev struct amdgpu_device *adev = (struct amdgpu_device *)handle;
282*b843c749SSergey Zigachev
283*b843c749SSergey Zigachev const struct amdgpu_ip_block *ip_block =
284*b843c749SSergey Zigachev amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP);
285*b843c749SSergey Zigachev
286*b843c749SSergey Zigachev if (!ip_block)
287*b843c749SSergey Zigachev return -EINVAL;
288*b843c749SSergey Zigachev
289*b843c749SSergey Zigachev r = amd_acp_hw_init(adev->acp.cgs_device,
290*b843c749SSergey Zigachev ip_block->version->major, ip_block->version->minor);
291*b843c749SSergey Zigachev /* -ENODEV means board uses AZ rather than ACP */
292*b843c749SSergey Zigachev if (r == -ENODEV)
293*b843c749SSergey Zigachev return 0;
294*b843c749SSergey Zigachev else if (r)
295*b843c749SSergey Zigachev return r;
296*b843c749SSergey Zigachev
297*b843c749SSergey Zigachev if (adev->rmmio_size == 0 || adev->rmmio_size < 0x5289)
298*b843c749SSergey Zigachev return -EINVAL;
299*b843c749SSergey Zigachev
300*b843c749SSergey Zigachev acp_base = adev->rmmio_base;
301*b843c749SSergey Zigachev
302*b843c749SSergey Zigachev if (adev->asic_type != CHIP_STONEY) {
303*b843c749SSergey Zigachev adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL);
304*b843c749SSergey Zigachev if (adev->acp.acp_genpd == NULL)
305*b843c749SSergey Zigachev return -ENOMEM;
306*b843c749SSergey Zigachev
307*b843c749SSergey Zigachev adev->acp.acp_genpd->gpd.name = "ACP_AUDIO";
308*b843c749SSergey Zigachev adev->acp.acp_genpd->gpd.power_off = acp_poweroff;
309*b843c749SSergey Zigachev adev->acp.acp_genpd->gpd.power_on = acp_poweron;
310*b843c749SSergey Zigachev
311*b843c749SSergey Zigachev
312*b843c749SSergey Zigachev adev->acp.acp_genpd->cgs_dev = adev->acp.cgs_device;
313*b843c749SSergey Zigachev
314*b843c749SSergey Zigachev pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false);
315*b843c749SSergey Zigachev }
316*b843c749SSergey Zigachev
317*b843c749SSergey Zigachev adev->acp.acp_cell = kcalloc(ACP_DEVS, sizeof(struct mfd_cell),
318*b843c749SSergey Zigachev GFP_KERNEL);
319*b843c749SSergey Zigachev
320*b843c749SSergey Zigachev if (adev->acp.acp_cell == NULL) {
321*b843c749SSergey Zigachev r = -ENOMEM;
322*b843c749SSergey Zigachev goto failure;
323*b843c749SSergey Zigachev }
324*b843c749SSergey Zigachev
325*b843c749SSergey Zigachev adev->acp.acp_res = kcalloc(5, sizeof(struct resource), GFP_KERNEL);
326*b843c749SSergey Zigachev if (adev->acp.acp_res == NULL) {
327*b843c749SSergey Zigachev r = -ENOMEM;
328*b843c749SSergey Zigachev goto failure;
329*b843c749SSergey Zigachev }
330*b843c749SSergey Zigachev
331*b843c749SSergey Zigachev i2s_pdata = kcalloc(3, sizeof(struct i2s_platform_data), GFP_KERNEL);
332*b843c749SSergey Zigachev if (i2s_pdata == NULL) {
333*b843c749SSergey Zigachev r = -ENOMEM;
334*b843c749SSergey Zigachev goto failure;
335*b843c749SSergey Zigachev }
336*b843c749SSergey Zigachev
337*b843c749SSergey Zigachev switch (adev->asic_type) {
338*b843c749SSergey Zigachev case CHIP_STONEY:
339*b843c749SSergey Zigachev i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
340*b843c749SSergey Zigachev DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
341*b843c749SSergey Zigachev break;
342*b843c749SSergey Zigachev default:
343*b843c749SSergey Zigachev i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
344*b843c749SSergey Zigachev }
345*b843c749SSergey Zigachev i2s_pdata[0].cap = DWC_I2S_PLAY;
346*b843c749SSergey Zigachev i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;
347*b843c749SSergey Zigachev i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET;
348*b843c749SSergey Zigachev i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET;
349*b843c749SSergey Zigachev switch (adev->asic_type) {
350*b843c749SSergey Zigachev case CHIP_STONEY:
351*b843c749SSergey Zigachev i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
352*b843c749SSergey Zigachev DW_I2S_QUIRK_COMP_PARAM1 |
353*b843c749SSergey Zigachev DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
354*b843c749SSergey Zigachev break;
355*b843c749SSergey Zigachev default:
356*b843c749SSergey Zigachev i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
357*b843c749SSergey Zigachev DW_I2S_QUIRK_COMP_PARAM1;
358*b843c749SSergey Zigachev }
359*b843c749SSergey Zigachev
360*b843c749SSergey Zigachev i2s_pdata[1].cap = DWC_I2S_RECORD;
361*b843c749SSergey Zigachev i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000;
362*b843c749SSergey Zigachev i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;
363*b843c749SSergey Zigachev i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET;
364*b843c749SSergey Zigachev
365*b843c749SSergey Zigachev i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
366*b843c749SSergey Zigachev switch (adev->asic_type) {
367*b843c749SSergey Zigachev case CHIP_STONEY:
368*b843c749SSergey Zigachev i2s_pdata[2].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
369*b843c749SSergey Zigachev break;
370*b843c749SSergey Zigachev default:
371*b843c749SSergey Zigachev break;
372*b843c749SSergey Zigachev }
373*b843c749SSergey Zigachev
374*b843c749SSergey Zigachev i2s_pdata[2].cap = DWC_I2S_PLAY | DWC_I2S_RECORD;
375*b843c749SSergey Zigachev i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000;
376*b843c749SSergey Zigachev i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET;
377*b843c749SSergey Zigachev i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET;
378*b843c749SSergey Zigachev
379*b843c749SSergey Zigachev adev->acp.acp_res[0].name = "acp2x_dma";
380*b843c749SSergey Zigachev adev->acp.acp_res[0].flags = IORESOURCE_MEM;
381*b843c749SSergey Zigachev adev->acp.acp_res[0].start = acp_base;
382*b843c749SSergey Zigachev adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END;
383*b843c749SSergey Zigachev
384*b843c749SSergey Zigachev adev->acp.acp_res[1].name = "acp2x_dw_i2s_play";
385*b843c749SSergey Zigachev adev->acp.acp_res[1].flags = IORESOURCE_MEM;
386*b843c749SSergey Zigachev adev->acp.acp_res[1].start = acp_base + ACP_I2S_PLAY_REGS_START;
387*b843c749SSergey Zigachev adev->acp.acp_res[1].end = acp_base + ACP_I2S_PLAY_REGS_END;
388*b843c749SSergey Zigachev
389*b843c749SSergey Zigachev adev->acp.acp_res[2].name = "acp2x_dw_i2s_cap";
390*b843c749SSergey Zigachev adev->acp.acp_res[2].flags = IORESOURCE_MEM;
391*b843c749SSergey Zigachev adev->acp.acp_res[2].start = acp_base + ACP_I2S_CAP_REGS_START;
392*b843c749SSergey Zigachev adev->acp.acp_res[2].end = acp_base + ACP_I2S_CAP_REGS_END;
393*b843c749SSergey Zigachev
394*b843c749SSergey Zigachev adev->acp.acp_res[3].name = "acp2x_dw_bt_i2s_play_cap";
395*b843c749SSergey Zigachev adev->acp.acp_res[3].flags = IORESOURCE_MEM;
396*b843c749SSergey Zigachev adev->acp.acp_res[3].start = acp_base + ACP_BT_PLAY_REGS_START;
397*b843c749SSergey Zigachev adev->acp.acp_res[3].end = acp_base + ACP_BT_PLAY_REGS_END;
398*b843c749SSergey Zigachev
399*b843c749SSergey Zigachev adev->acp.acp_res[4].name = "acp2x_dma_irq";
400*b843c749SSergey Zigachev adev->acp.acp_res[4].flags = IORESOURCE_IRQ;
401*b843c749SSergey Zigachev adev->acp.acp_res[4].start = amdgpu_irq_create_mapping(adev, 162);
402*b843c749SSergey Zigachev adev->acp.acp_res[4].end = adev->acp.acp_res[4].start;
403*b843c749SSergey Zigachev
404*b843c749SSergey Zigachev adev->acp.acp_cell[0].name = "acp_audio_dma";
405*b843c749SSergey Zigachev adev->acp.acp_cell[0].num_resources = 5;
406*b843c749SSergey Zigachev adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0];
407*b843c749SSergey Zigachev adev->acp.acp_cell[0].platform_data = &adev->asic_type;
408*b843c749SSergey Zigachev adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type);
409*b843c749SSergey Zigachev
410*b843c749SSergey Zigachev adev->acp.acp_cell[1].name = "designware-i2s";
411*b843c749SSergey Zigachev adev->acp.acp_cell[1].num_resources = 1;
412*b843c749SSergey Zigachev adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1];
413*b843c749SSergey Zigachev adev->acp.acp_cell[1].platform_data = &i2s_pdata[0];
414*b843c749SSergey Zigachev adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data);
415*b843c749SSergey Zigachev
416*b843c749SSergey Zigachev adev->acp.acp_cell[2].name = "designware-i2s";
417*b843c749SSergey Zigachev adev->acp.acp_cell[2].num_resources = 1;
418*b843c749SSergey Zigachev adev->acp.acp_cell[2].resources = &adev->acp.acp_res[2];
419*b843c749SSergey Zigachev adev->acp.acp_cell[2].platform_data = &i2s_pdata[1];
420*b843c749SSergey Zigachev adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data);
421*b843c749SSergey Zigachev
422*b843c749SSergey Zigachev adev->acp.acp_cell[3].name = "designware-i2s";
423*b843c749SSergey Zigachev adev->acp.acp_cell[3].num_resources = 1;
424*b843c749SSergey Zigachev adev->acp.acp_cell[3].resources = &adev->acp.acp_res[3];
425*b843c749SSergey Zigachev adev->acp.acp_cell[3].platform_data = &i2s_pdata[2];
426*b843c749SSergey Zigachev adev->acp.acp_cell[3].pdata_size = sizeof(struct i2s_platform_data);
427*b843c749SSergey Zigachev
428*b843c749SSergey Zigachev r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell,
429*b843c749SSergey Zigachev ACP_DEVS);
430*b843c749SSergey Zigachev if (r)
431*b843c749SSergey Zigachev goto failure;
432*b843c749SSergey Zigachev
433*b843c749SSergey Zigachev if (adev->asic_type != CHIP_STONEY) {
434*b843c749SSergey Zigachev for (i = 0; i < ACP_DEVS ; i++) {
435*b843c749SSergey Zigachev dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
436*b843c749SSergey Zigachev r = pm_genpd_add_device(&adev->acp.acp_genpd->gpd, dev);
437*b843c749SSergey Zigachev if (r) {
438*b843c749SSergey Zigachev dev_err(dev, "Failed to add dev to genpd\n");
439*b843c749SSergey Zigachev goto failure;
440*b843c749SSergey Zigachev }
441*b843c749SSergey Zigachev }
442*b843c749SSergey Zigachev }
443*b843c749SSergey Zigachev
444*b843c749SSergey Zigachev /* Assert Soft reset of ACP */
445*b843c749SSergey Zigachev val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
446*b843c749SSergey Zigachev
447*b843c749SSergey Zigachev val |= ACP_SOFT_RESET__SoftResetAud_MASK;
448*b843c749SSergey Zigachev cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
449*b843c749SSergey Zigachev
450*b843c749SSergey Zigachev count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
451*b843c749SSergey Zigachev while (true) {
452*b843c749SSergey Zigachev val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
453*b843c749SSergey Zigachev if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
454*b843c749SSergey Zigachev (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
455*b843c749SSergey Zigachev break;
456*b843c749SSergey Zigachev if (--count == 0) {
457*b843c749SSergey Zigachev dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
458*b843c749SSergey Zigachev r = -ETIMEDOUT;
459*b843c749SSergey Zigachev goto failure;
460*b843c749SSergey Zigachev }
461*b843c749SSergey Zigachev udelay(100);
462*b843c749SSergey Zigachev }
463*b843c749SSergey Zigachev /* Enable clock to ACP and wait until the clock is enabled */
464*b843c749SSergey Zigachev val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
465*b843c749SSergey Zigachev val = val | ACP_CONTROL__ClkEn_MASK;
466*b843c749SSergey Zigachev cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);
467*b843c749SSergey Zigachev
468*b843c749SSergey Zigachev count = ACP_CLOCK_EN_TIME_OUT_VALUE;
469*b843c749SSergey Zigachev
470*b843c749SSergey Zigachev while (true) {
471*b843c749SSergey Zigachev val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
472*b843c749SSergey Zigachev if (val & (u32) 0x1)
473*b843c749SSergey Zigachev break;
474*b843c749SSergey Zigachev if (--count == 0) {
475*b843c749SSergey Zigachev dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
476*b843c749SSergey Zigachev r = -ETIMEDOUT;
477*b843c749SSergey Zigachev goto failure;
478*b843c749SSergey Zigachev }
479*b843c749SSergey Zigachev udelay(100);
480*b843c749SSergey Zigachev }
481*b843c749SSergey Zigachev /* Deassert the SOFT RESET flags */
482*b843c749SSergey Zigachev val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
483*b843c749SSergey Zigachev val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
484*b843c749SSergey Zigachev cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
485*b843c749SSergey Zigachev return 0;
486*b843c749SSergey Zigachev
487*b843c749SSergey Zigachev failure:
488*b843c749SSergey Zigachev kfree(i2s_pdata);
489*b843c749SSergey Zigachev kfree(adev->acp.acp_res);
490*b843c749SSergey Zigachev kfree(adev->acp.acp_cell);
491*b843c749SSergey Zigachev kfree(adev->acp.acp_genpd);
492*b843c749SSergey Zigachev return r;
493*b843c749SSergey Zigachev }
494*b843c749SSergey Zigachev
495*b843c749SSergey Zigachev /**
496*b843c749SSergey Zigachev * acp_hw_fini - stop the hardware block
497*b843c749SSergey Zigachev *
498*b843c749SSergey Zigachev * @adev: amdgpu_device pointer
499*b843c749SSergey Zigachev *
500*b843c749SSergey Zigachev */
acp_hw_fini(void * handle)501*b843c749SSergey Zigachev static int acp_hw_fini(void *handle)
502*b843c749SSergey Zigachev {
503*b843c749SSergey Zigachev int i, ret;
504*b843c749SSergey Zigachev u32 val = 0;
505*b843c749SSergey Zigachev u32 count = 0;
506*b843c749SSergey Zigachev struct device *dev;
507*b843c749SSergey Zigachev struct amdgpu_device *adev = (struct amdgpu_device *)handle;
508*b843c749SSergey Zigachev
509*b843c749SSergey Zigachev /* return early if no ACP */
510*b843c749SSergey Zigachev if (!adev->acp.acp_cell)
511*b843c749SSergey Zigachev return 0;
512*b843c749SSergey Zigachev
513*b843c749SSergey Zigachev /* Assert Soft reset of ACP */
514*b843c749SSergey Zigachev val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
515*b843c749SSergey Zigachev
516*b843c749SSergey Zigachev val |= ACP_SOFT_RESET__SoftResetAud_MASK;
517*b843c749SSergey Zigachev cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
518*b843c749SSergey Zigachev
519*b843c749SSergey Zigachev count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
520*b843c749SSergey Zigachev while (true) {
521*b843c749SSergey Zigachev val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
522*b843c749SSergey Zigachev if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
523*b843c749SSergey Zigachev (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
524*b843c749SSergey Zigachev break;
525*b843c749SSergey Zigachev if (--count == 0) {
526*b843c749SSergey Zigachev dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
527*b843c749SSergey Zigachev return -ETIMEDOUT;
528*b843c749SSergey Zigachev }
529*b843c749SSergey Zigachev udelay(100);
530*b843c749SSergey Zigachev }
531*b843c749SSergey Zigachev /* Disable ACP clock */
532*b843c749SSergey Zigachev val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
533*b843c749SSergey Zigachev val &= ~ACP_CONTROL__ClkEn_MASK;
534*b843c749SSergey Zigachev cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);
535*b843c749SSergey Zigachev
536*b843c749SSergey Zigachev count = ACP_CLOCK_EN_TIME_OUT_VALUE;
537*b843c749SSergey Zigachev
538*b843c749SSergey Zigachev while (true) {
539*b843c749SSergey Zigachev val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
540*b843c749SSergey Zigachev if (val & (u32) 0x1)
541*b843c749SSergey Zigachev break;
542*b843c749SSergey Zigachev if (--count == 0) {
543*b843c749SSergey Zigachev dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
544*b843c749SSergey Zigachev return -ETIMEDOUT;
545*b843c749SSergey Zigachev }
546*b843c749SSergey Zigachev udelay(100);
547*b843c749SSergey Zigachev }
548*b843c749SSergey Zigachev
549*b843c749SSergey Zigachev if (adev->acp.acp_genpd) {
550*b843c749SSergey Zigachev for (i = 0; i < ACP_DEVS ; i++) {
551*b843c749SSergey Zigachev dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
552*b843c749SSergey Zigachev ret = pm_genpd_remove_device(dev);
553*b843c749SSergey Zigachev /* If removal fails, dont giveup and try rest */
554*b843c749SSergey Zigachev if (ret)
555*b843c749SSergey Zigachev dev_err(dev, "remove dev from genpd failed\n");
556*b843c749SSergey Zigachev }
557*b843c749SSergey Zigachev kfree(adev->acp.acp_genpd);
558*b843c749SSergey Zigachev }
559*b843c749SSergey Zigachev
560*b843c749SSergey Zigachev mfd_remove_devices(adev->acp.parent);
561*b843c749SSergey Zigachev kfree(adev->acp.acp_res);
562*b843c749SSergey Zigachev kfree(adev->acp.acp_cell);
563*b843c749SSergey Zigachev
564*b843c749SSergey Zigachev return 0;
565*b843c749SSergey Zigachev }
566*b843c749SSergey Zigachev
acp_suspend(void * handle)567*b843c749SSergey Zigachev static int acp_suspend(void *handle)
568*b843c749SSergey Zigachev {
569*b843c749SSergey Zigachev return 0;
570*b843c749SSergey Zigachev }
571*b843c749SSergey Zigachev
acp_resume(void * handle)572*b843c749SSergey Zigachev static int acp_resume(void *handle)
573*b843c749SSergey Zigachev {
574*b843c749SSergey Zigachev return 0;
575*b843c749SSergey Zigachev }
576*b843c749SSergey Zigachev
acp_early_init(void * handle)577*b843c749SSergey Zigachev static int acp_early_init(void *handle)
578*b843c749SSergey Zigachev {
579*b843c749SSergey Zigachev return 0;
580*b843c749SSergey Zigachev }
581*b843c749SSergey Zigachev
acp_is_idle(void * handle)582*b843c749SSergey Zigachev static bool acp_is_idle(void *handle)
583*b843c749SSergey Zigachev {
584*b843c749SSergey Zigachev return true;
585*b843c749SSergey Zigachev }
586*b843c749SSergey Zigachev
acp_wait_for_idle(void * handle)587*b843c749SSergey Zigachev static int acp_wait_for_idle(void *handle)
588*b843c749SSergey Zigachev {
589*b843c749SSergey Zigachev return 0;
590*b843c749SSergey Zigachev }
591*b843c749SSergey Zigachev
acp_soft_reset(void * handle)592*b843c749SSergey Zigachev static int acp_soft_reset(void *handle)
593*b843c749SSergey Zigachev {
594*b843c749SSergey Zigachev return 0;
595*b843c749SSergey Zigachev }
596*b843c749SSergey Zigachev
acp_set_clockgating_state(void * handle,enum amd_clockgating_state state)597*b843c749SSergey Zigachev static int acp_set_clockgating_state(void *handle,
598*b843c749SSergey Zigachev enum amd_clockgating_state state)
599*b843c749SSergey Zigachev {
600*b843c749SSergey Zigachev return 0;
601*b843c749SSergey Zigachev }
602*b843c749SSergey Zigachev
acp_set_powergating_state(void * handle,enum amd_powergating_state state)603*b843c749SSergey Zigachev static int acp_set_powergating_state(void *handle,
604*b843c749SSergey Zigachev enum amd_powergating_state state)
605*b843c749SSergey Zigachev {
606*b843c749SSergey Zigachev return 0;
607*b843c749SSergey Zigachev }
608*b843c749SSergey Zigachev
609*b843c749SSergey Zigachev static const struct amd_ip_funcs acp_ip_funcs = {
610*b843c749SSergey Zigachev .name = "acp_ip",
611*b843c749SSergey Zigachev .early_init = acp_early_init,
612*b843c749SSergey Zigachev .late_init = NULL,
613*b843c749SSergey Zigachev .sw_init = acp_sw_init,
614*b843c749SSergey Zigachev .sw_fini = acp_sw_fini,
615*b843c749SSergey Zigachev .hw_init = acp_hw_init,
616*b843c749SSergey Zigachev .hw_fini = acp_hw_fini,
617*b843c749SSergey Zigachev .suspend = acp_suspend,
618*b843c749SSergey Zigachev .resume = acp_resume,
619*b843c749SSergey Zigachev .is_idle = acp_is_idle,
620*b843c749SSergey Zigachev .wait_for_idle = acp_wait_for_idle,
621*b843c749SSergey Zigachev .soft_reset = acp_soft_reset,
622*b843c749SSergey Zigachev .set_clockgating_state = acp_set_clockgating_state,
623*b843c749SSergey Zigachev .set_powergating_state = acp_set_powergating_state,
624*b843c749SSergey Zigachev };
625*b843c749SSergey Zigachev
626*b843c749SSergey Zigachev const struct amdgpu_ip_block_version acp_ip_block =
627*b843c749SSergey Zigachev {
628*b843c749SSergey Zigachev .type = AMD_IP_BLOCK_TYPE_ACP,
629*b843c749SSergey Zigachev .major = 2,
630*b843c749SSergey Zigachev .minor = 2,
631*b843c749SSergey Zigachev .rev = 0,
632*b843c749SSergey Zigachev .funcs = &acp_ip_funcs,
633*b843c749SSergey Zigachev };
634