1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #include <linux/kthread.h> 27 #include <drm/drmP.h> 28 #include <linux/debugfs.h> 29 #include "amdgpu.h" 30 31 /** 32 * amdgpu_debugfs_add_files - Add simple debugfs entries 33 * 34 * @adev: Device to attach debugfs entries to 35 * @files: Array of function callbacks that respond to reads 36 * @nfiles: Number of callbacks to register 37 * 38 */ 39 int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 40 const struct drm_info_list *files, 41 unsigned nfiles) 42 { 43 unsigned i; 44 45 for (i = 0; i < adev->debugfs_count; i++) { 46 if (adev->debugfs[i].files == files) { 47 /* Already registered */ 48 return 0; 49 } 50 } 51 52 i = adev->debugfs_count + 1; 53 if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) { 54 DRM_ERROR("Reached maximum number of debugfs components.\n"); 55 DRM_ERROR("Report so we increase " 56 "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n"); 57 return -EINVAL; 58 } 59 adev->debugfs[adev->debugfs_count].files = files; 60 adev->debugfs[adev->debugfs_count].num_files = nfiles; 61 adev->debugfs_count = i; 62 #if defined(CONFIG_DEBUG_FS) 63 drm_debugfs_create_files(files, nfiles, 64 adev->ddev->primary->debugfs_root, 65 adev->ddev->primary); 66 #endif 67 return 0; 68 } 69 70 #if defined(CONFIG_DEBUG_FS) 71 72 /** 73 * amdgpu_debugfs_process_reg_op - Handle MMIO register reads/writes 74 * 75 * @read: True if reading 76 * @f: open file handle 77 * @buf: User buffer to write/read to 78 * @size: Number of bytes to write/read 79 * @pos: Offset to seek to 80 * 81 * This debugfs entry has special meaning on the offset being sought. 82 * Various bits have different meanings: 83 * 84 * Bit 62: Indicates a GRBM bank switch is needed 85 * Bit 61: Indicates a SRBM bank switch is needed (implies bit 62 is 86 * zero) 87 * Bits 24..33: The SE or ME selector if needed 88 * Bits 34..43: The SH (or SA) or PIPE selector if needed 89 * Bits 44..53: The INSTANCE (or CU/WGP) or QUEUE selector if needed 90 * 91 * Bit 23: Indicates that the PM power gating lock should be held 92 * This is necessary to read registers that might be 93 * unreliable during a power gating transistion. 94 * 95 * The lower bits are the BYTE offset of the register to read. This 96 * allows reading multiple registers in a single call and having 97 * the returned size reflect that. 98 */ 99 static int amdgpu_debugfs_process_reg_op(bool read, struct file *f, 100 char __user *buf, size_t size, loff_t *pos) 101 { 102 struct amdgpu_device *adev = file_inode(f)->i_private; 103 ssize_t result = 0; 104 int r; 105 bool pm_pg_lock, use_bank, use_ring; 106 unsigned instance_bank, sh_bank, se_bank, me, pipe, queue; 107 108 pm_pg_lock = use_bank = use_ring = false; 109 instance_bank = sh_bank = se_bank = me = pipe = queue = 0; 110 111 if (size & 0x3 || *pos & 0x3 || 112 ((*pos & (1ULL << 62)) && (*pos & (1ULL << 61)))) 113 return -EINVAL; 114 115 /* are we reading registers for which a PG lock is necessary? */ 116 pm_pg_lock = (*pos >> 23) & 1; 117 118 if (*pos & (1ULL << 62)) { 119 se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24; 120 sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34; 121 instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44; 122 123 if (se_bank == 0x3FF) 124 se_bank = 0xFFFFFFFF; 125 if (sh_bank == 0x3FF) 126 sh_bank = 0xFFFFFFFF; 127 if (instance_bank == 0x3FF) 128 instance_bank = 0xFFFFFFFF; 129 use_bank = 1; 130 } else if (*pos & (1ULL << 61)) { 131 132 me = (*pos & GENMASK_ULL(33, 24)) >> 24; 133 pipe = (*pos & GENMASK_ULL(43, 34)) >> 34; 134 queue = (*pos & GENMASK_ULL(53, 44)) >> 44; 135 136 use_ring = 1; 137 } else { 138 use_bank = use_ring = 0; 139 } 140 141 *pos &= (1UL << 22) - 1; 142 143 if (use_bank) { 144 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || 145 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) 146 return -EINVAL; 147 mutex_lock(&adev->grbm_idx_mutex); 148 amdgpu_gfx_select_se_sh(adev, se_bank, 149 sh_bank, instance_bank); 150 } else if (use_ring) { 151 mutex_lock(&adev->srbm_mutex); 152 amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue); 153 } 154 155 if (pm_pg_lock) 156 mutex_lock(&adev->pm.mutex); 157 158 while (size) { 159 uint32_t value; 160 161 if (*pos > adev->rmmio_size) 162 goto end; 163 164 if (read) { 165 value = RREG32(*pos >> 2); 166 r = put_user(value, (uint32_t *)buf); 167 } else { 168 r = get_user(value, (uint32_t *)buf); 169 if (!r) 170 WREG32(*pos >> 2, value); 171 } 172 if (r) { 173 result = r; 174 goto end; 175 } 176 177 result += 4; 178 buf += 4; 179 *pos += 4; 180 size -= 4; 181 } 182 183 end: 184 if (use_bank) { 185 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 186 mutex_unlock(&adev->grbm_idx_mutex); 187 } else if (use_ring) { 188 amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0); 189 mutex_unlock(&adev->srbm_mutex); 190 } 191 192 if (pm_pg_lock) 193 mutex_unlock(&adev->pm.mutex); 194 195 return result; 196 } 197 198 /** 199 * amdgpu_debugfs_regs_read - Callback for reading MMIO registers 200 */ 201 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, 202 size_t size, loff_t *pos) 203 { 204 return amdgpu_debugfs_process_reg_op(true, f, buf, size, pos); 205 } 206 207 /** 208 * amdgpu_debugfs_regs_write - Callback for writing MMIO registers 209 */ 210 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, 211 size_t size, loff_t *pos) 212 { 213 return amdgpu_debugfs_process_reg_op(false, f, (char __user *)buf, size, pos); 214 } 215 216 217 /** 218 * amdgpu_debugfs_regs_pcie_read - Read from a PCIE register 219 * 220 * @f: open file handle 221 * @buf: User buffer to store read data in 222 * @size: Number of bytes to read 223 * @pos: Offset to seek to 224 * 225 * The lower bits are the BYTE offset of the register to read. This 226 * allows reading multiple registers in a single call and having 227 * the returned size reflect that. 228 */ 229 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf, 230 size_t size, loff_t *pos) 231 { 232 struct amdgpu_device *adev = file_inode(f)->i_private; 233 ssize_t result = 0; 234 int r; 235 236 if (size & 0x3 || *pos & 0x3) 237 return -EINVAL; 238 239 while (size) { 240 uint32_t value; 241 242 value = RREG32_PCIE(*pos); 243 r = put_user(value, (uint32_t *)buf); 244 if (r) 245 return r; 246 247 result += 4; 248 buf += 4; 249 *pos += 4; 250 size -= 4; 251 } 252 253 return result; 254 } 255 256 /** 257 * amdgpu_debugfs_regs_pcie_write - Write to a PCIE register 258 * 259 * @f: open file handle 260 * @buf: User buffer to write data from 261 * @size: Number of bytes to write 262 * @pos: Offset to seek to 263 * 264 * The lower bits are the BYTE offset of the register to write. This 265 * allows writing multiple registers in a single call and having 266 * the returned size reflect that. 267 */ 268 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf, 269 size_t size, loff_t *pos) 270 { 271 struct amdgpu_device *adev = file_inode(f)->i_private; 272 ssize_t result = 0; 273 int r; 274 275 if (size & 0x3 || *pos & 0x3) 276 return -EINVAL; 277 278 while (size) { 279 uint32_t value; 280 281 r = get_user(value, (uint32_t *)buf); 282 if (r) 283 return r; 284 285 WREG32_PCIE(*pos, value); 286 287 result += 4; 288 buf += 4; 289 *pos += 4; 290 size -= 4; 291 } 292 293 return result; 294 } 295 296 /** 297 * amdgpu_debugfs_regs_didt_read - Read from a DIDT register 298 * 299 * @f: open file handle 300 * @buf: User buffer to store read data in 301 * @size: Number of bytes to read 302 * @pos: Offset to seek to 303 * 304 * The lower bits are the BYTE offset of the register to read. This 305 * allows reading multiple registers in a single call and having 306 * the returned size reflect that. 307 */ 308 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf, 309 size_t size, loff_t *pos) 310 { 311 struct amdgpu_device *adev = file_inode(f)->i_private; 312 ssize_t result = 0; 313 int r; 314 315 if (size & 0x3 || *pos & 0x3) 316 return -EINVAL; 317 318 while (size) { 319 uint32_t value; 320 321 value = RREG32_DIDT(*pos >> 2); 322 r = put_user(value, (uint32_t *)buf); 323 if (r) 324 return r; 325 326 result += 4; 327 buf += 4; 328 *pos += 4; 329 size -= 4; 330 } 331 332 return result; 333 } 334 335 /** 336 * amdgpu_debugfs_regs_didt_write - Write to a DIDT register 337 * 338 * @f: open file handle 339 * @buf: User buffer to write data from 340 * @size: Number of bytes to write 341 * @pos: Offset to seek to 342 * 343 * The lower bits are the BYTE offset of the register to write. This 344 * allows writing multiple registers in a single call and having 345 * the returned size reflect that. 346 */ 347 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf, 348 size_t size, loff_t *pos) 349 { 350 struct amdgpu_device *adev = file_inode(f)->i_private; 351 ssize_t result = 0; 352 int r; 353 354 if (size & 0x3 || *pos & 0x3) 355 return -EINVAL; 356 357 while (size) { 358 uint32_t value; 359 360 r = get_user(value, (uint32_t *)buf); 361 if (r) 362 return r; 363 364 WREG32_DIDT(*pos >> 2, value); 365 366 result += 4; 367 buf += 4; 368 *pos += 4; 369 size -= 4; 370 } 371 372 return result; 373 } 374 375 /** 376 * amdgpu_debugfs_regs_smc_read - Read from a SMC register 377 * 378 * @f: open file handle 379 * @buf: User buffer to store read data in 380 * @size: Number of bytes to read 381 * @pos: Offset to seek to 382 * 383 * The lower bits are the BYTE offset of the register to read. This 384 * allows reading multiple registers in a single call and having 385 * the returned size reflect that. 386 */ 387 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, 388 size_t size, loff_t *pos) 389 { 390 struct amdgpu_device *adev = file_inode(f)->i_private; 391 ssize_t result = 0; 392 int r; 393 394 if (size & 0x3 || *pos & 0x3) 395 return -EINVAL; 396 397 while (size) { 398 uint32_t value; 399 400 value = RREG32_SMC(*pos); 401 r = put_user(value, (uint32_t *)buf); 402 if (r) 403 return r; 404 405 result += 4; 406 buf += 4; 407 *pos += 4; 408 size -= 4; 409 } 410 411 return result; 412 } 413 414 /** 415 * amdgpu_debugfs_regs_smc_write - Write to a SMC register 416 * 417 * @f: open file handle 418 * @buf: User buffer to write data from 419 * @size: Number of bytes to write 420 * @pos: Offset to seek to 421 * 422 * The lower bits are the BYTE offset of the register to write. This 423 * allows writing multiple registers in a single call and having 424 * the returned size reflect that. 425 */ 426 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf, 427 size_t size, loff_t *pos) 428 { 429 struct amdgpu_device *adev = file_inode(f)->i_private; 430 ssize_t result = 0; 431 int r; 432 433 if (size & 0x3 || *pos & 0x3) 434 return -EINVAL; 435 436 while (size) { 437 uint32_t value; 438 439 r = get_user(value, (uint32_t *)buf); 440 if (r) 441 return r; 442 443 WREG32_SMC(*pos, value); 444 445 result += 4; 446 buf += 4; 447 *pos += 4; 448 size -= 4; 449 } 450 451 return result; 452 } 453 454 /** 455 * amdgpu_debugfs_gca_config_read - Read from gfx config data 456 * 457 * @f: open file handle 458 * @buf: User buffer to store read data in 459 * @size: Number of bytes to read 460 * @pos: Offset to seek to 461 * 462 * This file is used to access configuration data in a somewhat 463 * stable fashion. The format is a series of DWORDs with the first 464 * indicating which revision it is. New content is appended to the 465 * end so that older software can still read the data. 466 */ 467 468 static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf, 469 size_t size, loff_t *pos) 470 { 471 struct amdgpu_device *adev = file_inode(f)->i_private; 472 ssize_t result = 0; 473 int r; 474 uint32_t *config, no_regs = 0; 475 476 if (size & 0x3 || *pos & 0x3) 477 return -EINVAL; 478 479 config = kmalloc_array(256, sizeof(*config), GFP_KERNEL); 480 if (!config) 481 return -ENOMEM; 482 483 /* version, increment each time something is added */ 484 config[no_regs++] = 3; 485 config[no_regs++] = adev->gfx.config.max_shader_engines; 486 config[no_regs++] = adev->gfx.config.max_tile_pipes; 487 config[no_regs++] = adev->gfx.config.max_cu_per_sh; 488 config[no_regs++] = adev->gfx.config.max_sh_per_se; 489 config[no_regs++] = adev->gfx.config.max_backends_per_se; 490 config[no_regs++] = adev->gfx.config.max_texture_channel_caches; 491 config[no_regs++] = adev->gfx.config.max_gprs; 492 config[no_regs++] = adev->gfx.config.max_gs_threads; 493 config[no_regs++] = adev->gfx.config.max_hw_contexts; 494 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend; 495 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend; 496 config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size; 497 config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size; 498 config[no_regs++] = adev->gfx.config.num_tile_pipes; 499 config[no_regs++] = adev->gfx.config.backend_enable_mask; 500 config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes; 501 config[no_regs++] = adev->gfx.config.mem_row_size_in_kb; 502 config[no_regs++] = adev->gfx.config.shader_engine_tile_size; 503 config[no_regs++] = adev->gfx.config.num_gpus; 504 config[no_regs++] = adev->gfx.config.multi_gpu_tile_size; 505 config[no_regs++] = adev->gfx.config.mc_arb_ramcfg; 506 config[no_regs++] = adev->gfx.config.gb_addr_config; 507 config[no_regs++] = adev->gfx.config.num_rbs; 508 509 /* rev==1 */ 510 config[no_regs++] = adev->rev_id; 511 config[no_regs++] = adev->pg_flags; 512 config[no_regs++] = adev->cg_flags; 513 514 /* rev==2 */ 515 config[no_regs++] = adev->family; 516 config[no_regs++] = adev->external_rev_id; 517 518 /* rev==3 */ 519 config[no_regs++] = adev->pdev->device; 520 config[no_regs++] = adev->pdev->revision; 521 config[no_regs++] = adev->pdev->subsystem_device; 522 config[no_regs++] = adev->pdev->subsystem_vendor; 523 524 while (size && (*pos < no_regs * 4)) { 525 uint32_t value; 526 527 value = config[*pos >> 2]; 528 r = put_user(value, (uint32_t *)buf); 529 if (r) { 530 kfree(config); 531 return r; 532 } 533 534 result += 4; 535 buf += 4; 536 *pos += 4; 537 size -= 4; 538 } 539 540 kfree(config); 541 return result; 542 } 543 544 /** 545 * amdgpu_debugfs_sensor_read - Read from the powerplay sensors 546 * 547 * @f: open file handle 548 * @buf: User buffer to store read data in 549 * @size: Number of bytes to read 550 * @pos: Offset to seek to 551 * 552 * The offset is treated as the BYTE address of one of the sensors 553 * enumerated in amd/include/kgd_pp_interface.h under the 554 * 'amd_pp_sensors' enumeration. For instance to read the UVD VCLK 555 * you would use the offset 3 * 4 = 12. 556 */ 557 static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf, 558 size_t size, loff_t *pos) 559 { 560 struct amdgpu_device *adev = file_inode(f)->i_private; 561 int idx, x, outsize, r, valuesize; 562 uint32_t values[16]; 563 564 if (size & 3 || *pos & 0x3) 565 return -EINVAL; 566 567 if (!adev->pm.dpm_enabled) 568 return -EINVAL; 569 570 /* convert offset to sensor number */ 571 idx = *pos >> 2; 572 573 valuesize = sizeof(values); 574 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor) 575 r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize); 576 else 577 return -EINVAL; 578 579 if (size > valuesize) 580 return -EINVAL; 581 582 outsize = 0; 583 x = 0; 584 if (!r) { 585 while (size) { 586 r = put_user(values[x++], (int32_t *)buf); 587 buf += 4; 588 size -= 4; 589 outsize += 4; 590 } 591 } 592 593 return !r ? outsize : r; 594 } 595 596 /** amdgpu_debugfs_wave_read - Read WAVE STATUS data 597 * 598 * @f: open file handle 599 * @buf: User buffer to store read data in 600 * @size: Number of bytes to read 601 * @pos: Offset to seek to 602 * 603 * The offset being sought changes which wave that the status data 604 * will be returned for. The bits are used as follows: 605 * 606 * Bits 0..6: Byte offset into data 607 * Bits 7..14: SE selector 608 * Bits 15..22: SH/SA selector 609 * Bits 23..30: CU/{WGP+SIMD} selector 610 * Bits 31..36: WAVE ID selector 611 * Bits 37..44: SIMD ID selector 612 * 613 * The returned data begins with one DWORD of version information 614 * Followed by WAVE STATUS registers relevant to the GFX IP version 615 * being used. See gfx_v8_0_read_wave_data() for an example output. 616 */ 617 static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf, 618 size_t size, loff_t *pos) 619 { 620 struct amdgpu_device *adev = f->f_inode->i_private; 621 int r, x; 622 ssize_t result=0; 623 uint32_t offset, se, sh, cu, wave, simd, data[32]; 624 625 if (size & 3 || *pos & 3) 626 return -EINVAL; 627 628 /* decode offset */ 629 offset = (*pos & GENMASK_ULL(6, 0)); 630 se = (*pos & GENMASK_ULL(14, 7)) >> 7; 631 sh = (*pos & GENMASK_ULL(22, 15)) >> 15; 632 cu = (*pos & GENMASK_ULL(30, 23)) >> 23; 633 wave = (*pos & GENMASK_ULL(36, 31)) >> 31; 634 simd = (*pos & GENMASK_ULL(44, 37)) >> 37; 635 636 /* switch to the specific se/sh/cu */ 637 mutex_lock(&adev->grbm_idx_mutex); 638 amdgpu_gfx_select_se_sh(adev, se, sh, cu); 639 640 x = 0; 641 if (adev->gfx.funcs->read_wave_data) 642 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x); 643 644 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); 645 mutex_unlock(&adev->grbm_idx_mutex); 646 647 if (!x) 648 return -EINVAL; 649 650 while (size && (offset < x * 4)) { 651 uint32_t value; 652 653 value = data[offset >> 2]; 654 r = put_user(value, (uint32_t *)buf); 655 if (r) 656 return r; 657 658 result += 4; 659 buf += 4; 660 offset += 4; 661 size -= 4; 662 } 663 664 return result; 665 } 666 667 /** amdgpu_debugfs_gpr_read - Read wave gprs 668 * 669 * @f: open file handle 670 * @buf: User buffer to store read data in 671 * @size: Number of bytes to read 672 * @pos: Offset to seek to 673 * 674 * The offset being sought changes which wave that the status data 675 * will be returned for. The bits are used as follows: 676 * 677 * Bits 0..11: Byte offset into data 678 * Bits 12..19: SE selector 679 * Bits 20..27: SH/SA selector 680 * Bits 28..35: CU/{WGP+SIMD} selector 681 * Bits 36..43: WAVE ID selector 682 * Bits 37..44: SIMD ID selector 683 * Bits 52..59: Thread selector 684 * Bits 60..61: Bank selector (VGPR=0,SGPR=1) 685 * 686 * The return data comes from the SGPR or VGPR register bank for 687 * the selected operational unit. 688 */ 689 static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf, 690 size_t size, loff_t *pos) 691 { 692 struct amdgpu_device *adev = f->f_inode->i_private; 693 int r; 694 ssize_t result = 0; 695 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; 696 697 if (size > 4096 || size & 3 || *pos & 3) 698 return -EINVAL; 699 700 /* decode offset */ 701 offset = (*pos & GENMASK_ULL(11, 0)) >> 2; 702 se = (*pos & GENMASK_ULL(19, 12)) >> 12; 703 sh = (*pos & GENMASK_ULL(27, 20)) >> 20; 704 cu = (*pos & GENMASK_ULL(35, 28)) >> 28; 705 wave = (*pos & GENMASK_ULL(43, 36)) >> 36; 706 simd = (*pos & GENMASK_ULL(51, 44)) >> 44; 707 thread = (*pos & GENMASK_ULL(59, 52)) >> 52; 708 bank = (*pos & GENMASK_ULL(61, 60)) >> 60; 709 710 data = kcalloc(1024, sizeof(*data), GFP_KERNEL); 711 if (!data) 712 return -ENOMEM; 713 714 /* switch to the specific se/sh/cu */ 715 mutex_lock(&adev->grbm_idx_mutex); 716 amdgpu_gfx_select_se_sh(adev, se, sh, cu); 717 718 if (bank == 0) { 719 if (adev->gfx.funcs->read_wave_vgprs) 720 adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data); 721 } else { 722 if (adev->gfx.funcs->read_wave_sgprs) 723 adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data); 724 } 725 726 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); 727 mutex_unlock(&adev->grbm_idx_mutex); 728 729 while (size) { 730 uint32_t value; 731 732 value = data[result >> 2]; 733 r = put_user(value, (uint32_t *)buf); 734 if (r) { 735 result = r; 736 goto err; 737 } 738 739 result += 4; 740 buf += 4; 741 size -= 4; 742 } 743 744 err: 745 kfree(data); 746 return result; 747 } 748 749 static const struct file_operations amdgpu_debugfs_regs_fops = { 750 .owner = THIS_MODULE, 751 .read = amdgpu_debugfs_regs_read, 752 .write = amdgpu_debugfs_regs_write, 753 .llseek = default_llseek 754 }; 755 static const struct file_operations amdgpu_debugfs_regs_didt_fops = { 756 .owner = THIS_MODULE, 757 .read = amdgpu_debugfs_regs_didt_read, 758 .write = amdgpu_debugfs_regs_didt_write, 759 .llseek = default_llseek 760 }; 761 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = { 762 .owner = THIS_MODULE, 763 .read = amdgpu_debugfs_regs_pcie_read, 764 .write = amdgpu_debugfs_regs_pcie_write, 765 .llseek = default_llseek 766 }; 767 static const struct file_operations amdgpu_debugfs_regs_smc_fops = { 768 .owner = THIS_MODULE, 769 .read = amdgpu_debugfs_regs_smc_read, 770 .write = amdgpu_debugfs_regs_smc_write, 771 .llseek = default_llseek 772 }; 773 774 static const struct file_operations amdgpu_debugfs_gca_config_fops = { 775 .owner = THIS_MODULE, 776 .read = amdgpu_debugfs_gca_config_read, 777 .llseek = default_llseek 778 }; 779 780 static const struct file_operations amdgpu_debugfs_sensors_fops = { 781 .owner = THIS_MODULE, 782 .read = amdgpu_debugfs_sensor_read, 783 .llseek = default_llseek 784 }; 785 786 static const struct file_operations amdgpu_debugfs_wave_fops = { 787 .owner = THIS_MODULE, 788 .read = amdgpu_debugfs_wave_read, 789 .llseek = default_llseek 790 }; 791 static const struct file_operations amdgpu_debugfs_gpr_fops = { 792 .owner = THIS_MODULE, 793 .read = amdgpu_debugfs_gpr_read, 794 .llseek = default_llseek 795 }; 796 797 static const struct file_operations *debugfs_regs[] = { 798 &amdgpu_debugfs_regs_fops, 799 &amdgpu_debugfs_regs_didt_fops, 800 &amdgpu_debugfs_regs_pcie_fops, 801 &amdgpu_debugfs_regs_smc_fops, 802 &amdgpu_debugfs_gca_config_fops, 803 &amdgpu_debugfs_sensors_fops, 804 &amdgpu_debugfs_wave_fops, 805 &amdgpu_debugfs_gpr_fops, 806 }; 807 808 static const char *debugfs_regs_names[] = { 809 "amdgpu_regs", 810 "amdgpu_regs_didt", 811 "amdgpu_regs_pcie", 812 "amdgpu_regs_smc", 813 "amdgpu_gca_config", 814 "amdgpu_sensors", 815 "amdgpu_wave", 816 "amdgpu_gpr", 817 }; 818 819 /** 820 * amdgpu_debugfs_regs_init - Initialize debugfs entries that provide 821 * register access. 822 * 823 * @adev: The device to attach the debugfs entries to 824 */ 825 int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) 826 { 827 struct drm_minor *minor = adev->ddev->primary; 828 struct dentry *ent, *root = minor->debugfs_root; 829 unsigned i, j; 830 831 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { 832 ent = debugfs_create_file(debugfs_regs_names[i], 833 S_IFREG | S_IRUGO, root, 834 adev, debugfs_regs[i]); 835 if (IS_ERR(ent)) { 836 for (j = 0; j < i; j++) { 837 debugfs_remove(adev->debugfs_regs[i]); 838 adev->debugfs_regs[i] = NULL; 839 } 840 return PTR_ERR(ent); 841 } 842 843 if (!i) 844 i_size_write(ent->d_inode, adev->rmmio_size); 845 adev->debugfs_regs[i] = ent; 846 } 847 848 return 0; 849 } 850 851 void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) 852 { 853 unsigned i; 854 855 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { 856 if (adev->debugfs_regs[i]) { 857 debugfs_remove(adev->debugfs_regs[i]); 858 adev->debugfs_regs[i] = NULL; 859 } 860 } 861 } 862 863 static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data) 864 { 865 struct drm_info_node *node = (struct drm_info_node *) m->private; 866 struct drm_device *dev = node->minor->dev; 867 struct amdgpu_device *adev = dev->dev_private; 868 int r = 0, i; 869 870 /* hold on the scheduler */ 871 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 872 struct amdgpu_ring *ring = adev->rings[i]; 873 874 if (!ring || !ring->sched.thread) 875 continue; 876 kthread_park(ring->sched.thread); 877 } 878 879 seq_printf(m, "run ib test:\n"); 880 r = amdgpu_ib_ring_tests(adev); 881 if (r) 882 seq_printf(m, "ib ring tests failed (%d).\n", r); 883 else 884 seq_printf(m, "ib ring tests passed.\n"); 885 886 /* go on the scheduler */ 887 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 888 struct amdgpu_ring *ring = adev->rings[i]; 889 890 if (!ring || !ring->sched.thread) 891 continue; 892 kthread_unpark(ring->sched.thread); 893 } 894 895 return 0; 896 } 897 898 static int amdgpu_debugfs_get_vbios_dump(struct seq_file *m, void *data) 899 { 900 struct drm_info_node *node = (struct drm_info_node *) m->private; 901 struct drm_device *dev = node->minor->dev; 902 struct amdgpu_device *adev = dev->dev_private; 903 904 seq_write(m, adev->bios, adev->bios_size); 905 return 0; 906 } 907 908 static int amdgpu_debugfs_evict_vram(struct seq_file *m, void *data) 909 { 910 struct drm_info_node *node = (struct drm_info_node *)m->private; 911 struct drm_device *dev = node->minor->dev; 912 struct amdgpu_device *adev = dev->dev_private; 913 914 seq_printf(m, "(%d)\n", amdgpu_bo_evict_vram(adev)); 915 return 0; 916 } 917 918 static int amdgpu_debugfs_evict_gtt(struct seq_file *m, void *data) 919 { 920 struct drm_info_node *node = (struct drm_info_node *)m->private; 921 struct drm_device *dev = node->minor->dev; 922 struct amdgpu_device *adev = dev->dev_private; 923 924 seq_printf(m, "(%d)\n", ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_TT)); 925 return 0; 926 } 927 928 static const struct drm_info_list amdgpu_debugfs_list[] = { 929 {"amdgpu_vbios", amdgpu_debugfs_get_vbios_dump}, 930 {"amdgpu_test_ib", &amdgpu_debugfs_test_ib}, 931 {"amdgpu_evict_vram", &amdgpu_debugfs_evict_vram}, 932 {"amdgpu_evict_gtt", &amdgpu_debugfs_evict_gtt}, 933 }; 934 935 int amdgpu_debugfs_init(struct amdgpu_device *adev) 936 { 937 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_list, 938 ARRAY_SIZE(amdgpu_debugfs_list)); 939 } 940 941 #else 942 int amdgpu_debugfs_init(struct amdgpu_device *adev) 943 { 944 return 0; 945 } 946 int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) 947 { 948 return 0; 949 } 950 void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { } 951 #endif 952