1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/amdgpu_drm.h> 28 #include "amdgpu.h" 29 #include "amdgpu_i2c.h" 30 #include "atom.h" 31 #include "amdgpu_connectors.h" 32 #include "amdgpu_display.h" 33 #include <asm/div64.h> 34 35 #include <linux/pm_runtime.h> 36 #include <drm/drm_crtc_helper.h> 37 #include <drm/drm_edid.h> 38 #include <drm/drm_gem_framebuffer_helper.h> 39 #include <drm/drm_fb_helper.h> 40 41 static void amdgpu_display_flip_callback(struct dma_fence *f, 42 struct dma_fence_cb *cb) 43 { 44 struct amdgpu_flip_work *work = 45 container_of(cb, struct amdgpu_flip_work, cb); 46 47 dma_fence_put(f); 48 schedule_work(&work->flip_work.work); 49 } 50 51 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work, 52 struct dma_fence **f) 53 { 54 struct dma_fence *fence= *f; 55 56 if (fence == NULL) 57 return false; 58 59 *f = NULL; 60 61 if (!dma_fence_add_callback(fence, &work->cb, 62 amdgpu_display_flip_callback)) 63 return true; 64 65 dma_fence_put(fence); 66 return false; 67 } 68 69 static void amdgpu_display_flip_work_func(struct work_struct *__work) 70 { 71 struct delayed_work *delayed_work = 72 container_of(__work, struct delayed_work, work); 73 struct amdgpu_flip_work *work = 74 container_of(delayed_work, struct amdgpu_flip_work, flip_work); 75 struct amdgpu_device *adev = work->adev; 76 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id]; 77 78 struct drm_crtc *crtc = &amdgpu_crtc->base; 79 unsigned long flags; 80 unsigned i; 81 int vpos, hpos; 82 83 if (amdgpu_display_flip_handle_fence(work, &work->excl)) 84 return; 85 86 for (i = 0; i < work->shared_count; ++i) 87 if (amdgpu_display_flip_handle_fence(work, &work->shared[i])) 88 return; 89 90 /* Wait until we're out of the vertical blank period before the one 91 * targeted by the flip 92 */ 93 if (amdgpu_crtc->enabled && 94 (amdgpu_display_get_crtc_scanoutpos(adev->ddev, work->crtc_id, 0, 95 &vpos, &hpos, NULL, NULL, 96 &crtc->hwmode) 97 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 98 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 99 (int)(work->target_vblank - 100 amdgpu_get_vblank_counter_kms(adev->ddev, amdgpu_crtc->crtc_id)) > 0) { 101 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000)); 102 return; 103 } 104 105 /* We borrow the event spin lock for protecting flip_status */ 106 spin_lock_irqsave(&crtc->dev->event_lock, flags); 107 108 /* Do the flip (mmio) */ 109 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async); 110 111 /* Set the flip status */ 112 amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 113 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 114 115 116 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n", 117 amdgpu_crtc->crtc_id, amdgpu_crtc, work); 118 119 } 120 121 /* 122 * Handle unpin events outside the interrupt handler proper. 123 */ 124 static void amdgpu_display_unpin_work_func(struct work_struct *__work) 125 { 126 struct amdgpu_flip_work *work = 127 container_of(__work, struct amdgpu_flip_work, unpin_work); 128 int r; 129 130 /* unpin of the old buffer */ 131 r = amdgpu_bo_reserve(work->old_abo, true); 132 if (likely(r == 0)) { 133 r = amdgpu_bo_unpin(work->old_abo); 134 if (unlikely(r != 0)) { 135 DRM_ERROR("failed to unpin buffer after flip\n"); 136 } 137 amdgpu_bo_unreserve(work->old_abo); 138 } else 139 DRM_ERROR("failed to reserve buffer after flip\n"); 140 141 amdgpu_bo_unref(&work->old_abo); 142 kfree(work->shared); 143 kfree(work); 144 } 145 146 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, 147 struct drm_framebuffer *fb, 148 struct drm_pending_vblank_event *event, 149 uint32_t page_flip_flags, uint32_t target, 150 struct drm_modeset_acquire_ctx *ctx) 151 { 152 struct drm_device *dev = crtc->dev; 153 struct amdgpu_device *adev = dev->dev_private; 154 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 155 struct drm_gem_object *obj; 156 struct amdgpu_flip_work *work; 157 struct amdgpu_bo *new_abo; 158 unsigned long flags; 159 u64 tiling_flags; 160 int i, r; 161 162 work = kzalloc(sizeof *work, GFP_KERNEL); 163 if (work == NULL) 164 return -ENOMEM; 165 166 INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func); 167 INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func); 168 169 work->event = event; 170 work->adev = adev; 171 work->crtc_id = amdgpu_crtc->crtc_id; 172 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 173 174 /* schedule unpin of the old buffer */ 175 obj = crtc->primary->fb->obj[0]; 176 177 /* take a reference to the old object */ 178 work->old_abo = gem_to_amdgpu_bo(obj); 179 amdgpu_bo_ref(work->old_abo); 180 181 obj = fb->obj[0]; 182 new_abo = gem_to_amdgpu_bo(obj); 183 184 /* pin the new buffer */ 185 r = amdgpu_bo_reserve(new_abo, false); 186 if (unlikely(r != 0)) { 187 DRM_ERROR("failed to reserve new abo buffer before flip\n"); 188 goto cleanup; 189 } 190 191 r = amdgpu_bo_pin(new_abo, amdgpu_display_supported_domains(adev)); 192 if (unlikely(r != 0)) { 193 DRM_ERROR("failed to pin new abo buffer before flip\n"); 194 goto unreserve; 195 } 196 197 r = amdgpu_ttm_alloc_gart(&new_abo->tbo); 198 if (unlikely(r != 0)) { 199 DRM_ERROR("%p bind failed\n", new_abo); 200 goto unpin; 201 } 202 203 r = reservation_object_get_fences_rcu(new_abo->tbo.resv, &work->excl, 204 &work->shared_count, 205 &work->shared); 206 if (unlikely(r != 0)) { 207 DRM_ERROR("failed to get fences for buffer\n"); 208 goto unpin; 209 } 210 211 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); 212 amdgpu_bo_unreserve(new_abo); 213 214 work->base = amdgpu_bo_gpu_offset(new_abo); 215 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + 216 amdgpu_get_vblank_counter_kms(dev, work->crtc_id); 217 218 /* we borrow the event spin lock for protecting flip_wrok */ 219 spin_lock_irqsave(&crtc->dev->event_lock, flags); 220 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { 221 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 222 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 223 r = -EBUSY; 224 goto pflip_cleanup; 225 } 226 227 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; 228 amdgpu_crtc->pflip_works = work; 229 230 231 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n", 232 amdgpu_crtc->crtc_id, amdgpu_crtc, work); 233 /* update crtc fb */ 234 crtc->primary->fb = fb; 235 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 236 amdgpu_display_flip_work_func(&work->flip_work.work); 237 return 0; 238 239 pflip_cleanup: 240 if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) { 241 DRM_ERROR("failed to reserve new abo in error path\n"); 242 goto cleanup; 243 } 244 unpin: 245 if (unlikely(amdgpu_bo_unpin(new_abo) != 0)) { 246 DRM_ERROR("failed to unpin new abo in error path\n"); 247 } 248 unreserve: 249 amdgpu_bo_unreserve(new_abo); 250 251 cleanup: 252 amdgpu_bo_unref(&work->old_abo); 253 dma_fence_put(work->excl); 254 for (i = 0; i < work->shared_count; ++i) 255 dma_fence_put(work->shared[i]); 256 kfree(work->shared); 257 kfree(work); 258 259 return r; 260 } 261 262 int amdgpu_display_crtc_set_config(struct drm_mode_set *set, 263 struct drm_modeset_acquire_ctx *ctx) 264 { 265 struct drm_device *dev; 266 struct amdgpu_device *adev; 267 struct drm_crtc *crtc; 268 bool active = false; 269 int ret; 270 271 if (!set || !set->crtc) 272 return -EINVAL; 273 274 dev = set->crtc->dev; 275 276 ret = pm_runtime_get_sync(dev->dev); 277 if (ret < 0) 278 goto out; 279 280 ret = drm_crtc_helper_set_config(set, ctx); 281 282 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 283 if (crtc->enabled) 284 active = true; 285 286 pm_runtime_mark_last_busy(dev->dev); 287 288 adev = dev->dev_private; 289 /* if we have active crtcs and we don't have a power ref, 290 take the current one */ 291 if (active && !adev->have_disp_power_ref) { 292 adev->have_disp_power_ref = true; 293 return ret; 294 } 295 /* if we have no active crtcs, then drop the power ref 296 we got before */ 297 if (!active && adev->have_disp_power_ref) { 298 pm_runtime_put_autosuspend(dev->dev); 299 adev->have_disp_power_ref = false; 300 } 301 302 out: 303 /* drop the power reference we got coming in here */ 304 pm_runtime_put_autosuspend(dev->dev); 305 return ret; 306 } 307 308 static const char *encoder_names[41] = { 309 "NONE", 310 "INTERNAL_LVDS", 311 "INTERNAL_TMDS1", 312 "INTERNAL_TMDS2", 313 "INTERNAL_DAC1", 314 "INTERNAL_DAC2", 315 "INTERNAL_SDVOA", 316 "INTERNAL_SDVOB", 317 "SI170B", 318 "CH7303", 319 "CH7301", 320 "INTERNAL_DVO1", 321 "EXTERNAL_SDVOA", 322 "EXTERNAL_SDVOB", 323 "TITFP513", 324 "INTERNAL_LVTM1", 325 "VT1623", 326 "HDMI_SI1930", 327 "HDMI_INTERNAL", 328 "INTERNAL_KLDSCP_TMDS1", 329 "INTERNAL_KLDSCP_DVO1", 330 "INTERNAL_KLDSCP_DAC1", 331 "INTERNAL_KLDSCP_DAC2", 332 "SI178", 333 "MVPU_FPGA", 334 "INTERNAL_DDI", 335 "VT1625", 336 "HDMI_SI1932", 337 "DP_AN9801", 338 "DP_DP501", 339 "INTERNAL_UNIPHY", 340 "INTERNAL_KLDSCP_LVTMA", 341 "INTERNAL_UNIPHY1", 342 "INTERNAL_UNIPHY2", 343 "NUTMEG", 344 "TRAVIS", 345 "INTERNAL_VCE", 346 "INTERNAL_UNIPHY3", 347 "HDMI_ANX9805", 348 "INTERNAL_AMCLK", 349 "VIRTUAL", 350 }; 351 352 static const char *hpd_names[6] = { 353 "HPD1", 354 "HPD2", 355 "HPD3", 356 "HPD4", 357 "HPD5", 358 "HPD6", 359 }; 360 361 void amdgpu_display_print_display_setup(struct drm_device *dev) 362 { 363 struct drm_connector *connector; 364 struct amdgpu_connector *amdgpu_connector; 365 struct drm_encoder *encoder; 366 struct amdgpu_encoder *amdgpu_encoder; 367 uint32_t devices; 368 int i = 0; 369 370 DRM_INFO("AMDGPU Display Connectors\n"); 371 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 372 amdgpu_connector = to_amdgpu_connector(connector); 373 DRM_INFO("Connector %d:\n", i); 374 DRM_INFO(" %s\n", connector->name); 375 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) 376 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]); 377 if (amdgpu_connector->ddc_bus) { 378 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 379 amdgpu_connector->ddc_bus->rec.mask_clk_reg, 380 amdgpu_connector->ddc_bus->rec.mask_data_reg, 381 amdgpu_connector->ddc_bus->rec.a_clk_reg, 382 amdgpu_connector->ddc_bus->rec.a_data_reg, 383 amdgpu_connector->ddc_bus->rec.en_clk_reg, 384 amdgpu_connector->ddc_bus->rec.en_data_reg, 385 amdgpu_connector->ddc_bus->rec.y_clk_reg, 386 amdgpu_connector->ddc_bus->rec.y_data_reg); 387 if (amdgpu_connector->router.ddc_valid) 388 DRM_INFO(" DDC Router 0x%x/0x%x\n", 389 amdgpu_connector->router.ddc_mux_control_pin, 390 amdgpu_connector->router.ddc_mux_state); 391 if (amdgpu_connector->router.cd_valid) 392 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 393 amdgpu_connector->router.cd_mux_control_pin, 394 amdgpu_connector->router.cd_mux_state); 395 } else { 396 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 397 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 398 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 399 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 400 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 401 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 402 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 403 } 404 DRM_INFO(" Encoders:\n"); 405 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 406 amdgpu_encoder = to_amdgpu_encoder(encoder); 407 devices = amdgpu_encoder->devices & amdgpu_connector->devices; 408 if (devices) { 409 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 410 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 411 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 412 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 413 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 414 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 415 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 416 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 417 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 418 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 419 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 420 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 421 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 422 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 423 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 424 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 425 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 426 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 427 if (devices & ATOM_DEVICE_TV1_SUPPORT) 428 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 429 if (devices & ATOM_DEVICE_CV_SUPPORT) 430 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 431 } 432 } 433 i++; 434 } 435 } 436 437 /** 438 * amdgpu_display_ddc_probe 439 * 440 */ 441 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, 442 bool use_aux) 443 { 444 u8 out = 0x0; 445 u8 buf[8]; 446 int ret; 447 struct i2c_msg msgs[] = { 448 { 449 .addr = DDC_ADDR, 450 .flags = 0, 451 .len = 1, 452 .buf = &out, 453 }, 454 { 455 .addr = DDC_ADDR, 456 .flags = I2C_M_RD, 457 .len = 8, 458 .buf = buf, 459 } 460 }; 461 462 /* on hw with routers, select right port */ 463 if (amdgpu_connector->router.ddc_valid) 464 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 465 466 if (use_aux) { 467 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); 468 } else { 469 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); 470 } 471 472 if (ret != 2) 473 /* Couldn't find an accessible DDC on this connector */ 474 return false; 475 /* Probe also for valid EDID header 476 * EDID header starts with: 477 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 478 * Only the first 6 bytes must be valid as 479 * drm_edid_block_valid() can fix the last 2 bytes */ 480 if (drm_edid_header_is_valid(buf) < 6) { 481 /* Couldn't find an accessible EDID on this 482 * connector */ 483 return false; 484 } 485 return true; 486 } 487 488 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { 489 .destroy = drm_gem_fb_destroy, 490 .create_handle = drm_gem_fb_create_handle, 491 }; 492 493 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev) 494 { 495 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 496 497 #if defined(CONFIG_DRM_AMD_DC) 498 if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN && 499 adev->flags & AMD_IS_APU && 500 amdgpu_device_asic_has_dc_support(adev->asic_type)) 501 domain |= AMDGPU_GEM_DOMAIN_GTT; 502 #endif 503 504 return domain; 505 } 506 507 int amdgpu_display_framebuffer_init(struct drm_device *dev, 508 struct amdgpu_framebuffer *rfb, 509 const struct drm_mode_fb_cmd2 *mode_cmd, 510 struct drm_gem_object *obj) 511 { 512 int ret; 513 rfb->base.obj[0] = obj; 514 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); 515 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); 516 if (ret) { 517 rfb->base.obj[0] = NULL; 518 return ret; 519 } 520 return 0; 521 } 522 523 struct drm_framebuffer * 524 amdgpu_display_user_framebuffer_create(struct drm_device *dev, 525 struct drm_file *file_priv, 526 const struct drm_mode_fb_cmd2 *mode_cmd) 527 { 528 struct drm_gem_object *obj; 529 struct amdgpu_framebuffer *amdgpu_fb; 530 int ret; 531 532 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); 533 if (obj == NULL) { 534 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 535 "can't create framebuffer\n", mode_cmd->handles[0]); 536 return ERR_PTR(-ENOENT); 537 } 538 539 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ 540 if (obj->import_attach) { 541 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n"); 542 return ERR_PTR(-EINVAL); 543 } 544 545 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); 546 if (amdgpu_fb == NULL) { 547 drm_gem_object_put_unlocked(obj); 548 return ERR_PTR(-ENOMEM); 549 } 550 551 ret = amdgpu_display_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj); 552 if (ret) { 553 kfree(amdgpu_fb); 554 drm_gem_object_put_unlocked(obj); 555 return ERR_PTR(ret); 556 } 557 558 return &amdgpu_fb->base; 559 } 560 561 const struct drm_mode_config_funcs amdgpu_mode_funcs = { 562 .fb_create = amdgpu_display_user_framebuffer_create, 563 .output_poll_changed = drm_fb_helper_output_poll_changed, 564 }; 565 566 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] = 567 { { UNDERSCAN_OFF, "off" }, 568 { UNDERSCAN_ON, "on" }, 569 { UNDERSCAN_AUTO, "auto" }, 570 }; 571 572 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] = 573 { { AMDGPU_AUDIO_DISABLE, "off" }, 574 { AMDGPU_AUDIO_ENABLE, "on" }, 575 { AMDGPU_AUDIO_AUTO, "auto" }, 576 }; 577 578 /* XXX support different dither options? spatial, temporal, both, etc. */ 579 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] = 580 { { AMDGPU_FMT_DITHER_DISABLE, "off" }, 581 { AMDGPU_FMT_DITHER_ENABLE, "on" }, 582 }; 583 584 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev) 585 { 586 int sz; 587 588 adev->mode_info.coherent_mode_property = 589 drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1); 590 if (!adev->mode_info.coherent_mode_property) 591 return -ENOMEM; 592 593 adev->mode_info.load_detect_property = 594 drm_property_create_range(adev->ddev, 0, "load detection", 0, 1); 595 if (!adev->mode_info.load_detect_property) 596 return -ENOMEM; 597 598 drm_mode_create_scaling_mode_property(adev->ddev); 599 600 sz = ARRAY_SIZE(amdgpu_underscan_enum_list); 601 adev->mode_info.underscan_property = 602 drm_property_create_enum(adev->ddev, 0, 603 "underscan", 604 amdgpu_underscan_enum_list, sz); 605 606 adev->mode_info.underscan_hborder_property = 607 drm_property_create_range(adev->ddev, 0, 608 "underscan hborder", 0, 128); 609 if (!adev->mode_info.underscan_hborder_property) 610 return -ENOMEM; 611 612 adev->mode_info.underscan_vborder_property = 613 drm_property_create_range(adev->ddev, 0, 614 "underscan vborder", 0, 128); 615 if (!adev->mode_info.underscan_vborder_property) 616 return -ENOMEM; 617 618 sz = ARRAY_SIZE(amdgpu_audio_enum_list); 619 adev->mode_info.audio_property = 620 drm_property_create_enum(adev->ddev, 0, 621 "audio", 622 amdgpu_audio_enum_list, sz); 623 624 sz = ARRAY_SIZE(amdgpu_dither_enum_list); 625 adev->mode_info.dither_property = 626 drm_property_create_enum(adev->ddev, 0, 627 "dither", 628 amdgpu_dither_enum_list, sz); 629 630 if (amdgpu_device_has_dc_support(adev)) { 631 adev->mode_info.max_bpc_property = 632 drm_property_create_range(adev->ddev, 0, "max bpc", 8, 16); 633 if (!adev->mode_info.max_bpc_property) 634 return -ENOMEM; 635 } 636 637 return 0; 638 } 639 640 void amdgpu_display_update_priority(struct amdgpu_device *adev) 641 { 642 /* adjustment options for the display watermarks */ 643 if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2)) 644 adev->mode_info.disp_priority = 0; 645 else 646 adev->mode_info.disp_priority = amdgpu_disp_priority; 647 648 } 649 650 static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode) 651 { 652 /* try and guess if this is a tv or a monitor */ 653 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 654 (mode->vdisplay == 576) || /* 576p */ 655 (mode->vdisplay == 720) || /* 720p */ 656 (mode->vdisplay == 1080)) /* 1080p */ 657 return true; 658 else 659 return false; 660 } 661 662 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 663 const struct drm_display_mode *mode, 664 struct drm_display_mode *adjusted_mode) 665 { 666 struct drm_device *dev = crtc->dev; 667 struct drm_encoder *encoder; 668 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 669 struct amdgpu_encoder *amdgpu_encoder; 670 struct drm_connector *connector; 671 struct amdgpu_connector *amdgpu_connector; 672 u32 src_v = 1, dst_v = 1; 673 u32 src_h = 1, dst_h = 1; 674 675 amdgpu_crtc->h_border = 0; 676 amdgpu_crtc->v_border = 0; 677 678 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 679 if (encoder->crtc != crtc) 680 continue; 681 amdgpu_encoder = to_amdgpu_encoder(encoder); 682 connector = amdgpu_get_connector_for_encoder(encoder); 683 amdgpu_connector = to_amdgpu_connector(connector); 684 685 /* set scaling */ 686 if (amdgpu_encoder->rmx_type == RMX_OFF) 687 amdgpu_crtc->rmx_type = RMX_OFF; 688 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay || 689 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay) 690 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type; 691 else 692 amdgpu_crtc->rmx_type = RMX_OFF; 693 /* copy native mode */ 694 memcpy(&amdgpu_crtc->native_mode, 695 &amdgpu_encoder->native_mode, 696 sizeof(struct drm_display_mode)); 697 src_v = crtc->mode.vdisplay; 698 dst_v = amdgpu_crtc->native_mode.vdisplay; 699 src_h = crtc->mode.hdisplay; 700 dst_h = amdgpu_crtc->native_mode.hdisplay; 701 702 /* fix up for overscan on hdmi */ 703 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 704 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || 705 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && 706 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) && 707 amdgpu_display_is_hdtv_mode(mode)))) { 708 if (amdgpu_encoder->underscan_hborder != 0) 709 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; 710 else 711 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16; 712 if (amdgpu_encoder->underscan_vborder != 0) 713 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder; 714 else 715 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16; 716 amdgpu_crtc->rmx_type = RMX_FULL; 717 src_v = crtc->mode.vdisplay; 718 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2); 719 src_h = crtc->mode.hdisplay; 720 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2); 721 } 722 } 723 if (amdgpu_crtc->rmx_type != RMX_OFF) { 724 fixed20_12 a, b; 725 a.full = dfixed_const(src_v); 726 b.full = dfixed_const(dst_v); 727 amdgpu_crtc->vsc.full = dfixed_div(a, b); 728 a.full = dfixed_const(src_h); 729 b.full = dfixed_const(dst_h); 730 amdgpu_crtc->hsc.full = dfixed_div(a, b); 731 } else { 732 amdgpu_crtc->vsc.full = dfixed_const(1); 733 amdgpu_crtc->hsc.full = dfixed_const(1); 734 } 735 return true; 736 } 737 738 /* 739 * Retrieve current video scanout position of crtc on a given gpu, and 740 * an optional accurate timestamp of when query happened. 741 * 742 * \param dev Device to query. 743 * \param pipe Crtc to query. 744 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 745 * For driver internal use only also supports these flags: 746 * 747 * USE_REAL_VBLANKSTART to use the real start of vblank instead 748 * of a fudged earlier start of vblank. 749 * 750 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 751 * fudged earlier start of vblank in *vpos and the distance 752 * to true start of vblank in *hpos. 753 * 754 * \param *vpos Location where vertical scanout position should be stored. 755 * \param *hpos Location where horizontal scanout position should go. 756 * \param *stime Target location for timestamp taken immediately before 757 * scanout position query. Can be NULL to skip timestamp. 758 * \param *etime Target location for timestamp taken immediately after 759 * scanout position query. Can be NULL to skip timestamp. 760 * 761 * Returns vpos as a positive number while in active scanout area. 762 * Returns vpos as a negative number inside vblank, counting the number 763 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 764 * until start of active scanout / end of vblank." 765 * 766 * \return Flags, or'ed together as follows: 767 * 768 * DRM_SCANOUTPOS_VALID = Query successful. 769 * DRM_SCANOUTPOS_INVBL = Inside vblank. 770 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 771 * this flag means that returned position may be offset by a constant but 772 * unknown small number of scanlines wrt. real scanout position. 773 * 774 */ 775 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, 776 unsigned int pipe, unsigned int flags, int *vpos, 777 int *hpos, ktime_t *stime, ktime_t *etime, 778 const struct drm_display_mode *mode) 779 { 780 u32 vbl = 0, position = 0; 781 int vbl_start, vbl_end, vtotal, ret = 0; 782 bool in_vbl = true; 783 784 struct amdgpu_device *adev = dev->dev_private; 785 786 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 787 788 /* Get optional system timestamp before query. */ 789 if (stime) 790 *stime = ktime_get(); 791 792 if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0) 793 ret |= DRM_SCANOUTPOS_VALID; 794 795 /* Get optional system timestamp after query. */ 796 if (etime) 797 *etime = ktime_get(); 798 799 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 800 801 /* Decode into vertical and horizontal scanout position. */ 802 *vpos = position & 0x1fff; 803 *hpos = (position >> 16) & 0x1fff; 804 805 /* Valid vblank area boundaries from gpu retrieved? */ 806 if (vbl > 0) { 807 /* Yes: Decode. */ 808 ret |= DRM_SCANOUTPOS_ACCURATE; 809 vbl_start = vbl & 0x1fff; 810 vbl_end = (vbl >> 16) & 0x1fff; 811 } 812 else { 813 /* No: Fake something reasonable which gives at least ok results. */ 814 vbl_start = mode->crtc_vdisplay; 815 vbl_end = 0; 816 } 817 818 /* Called from driver internal vblank counter query code? */ 819 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 820 /* Caller wants distance from real vbl_start in *hpos */ 821 *hpos = *vpos - vbl_start; 822 } 823 824 /* Fudge vblank to start a few scanlines earlier to handle the 825 * problem that vblank irqs fire a few scanlines before start 826 * of vblank. Some driver internal callers need the true vblank 827 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 828 * 829 * The cause of the "early" vblank irq is that the irq is triggered 830 * by the line buffer logic when the line buffer read position enters 831 * the vblank, whereas our crtc scanout position naturally lags the 832 * line buffer read position. 833 */ 834 if (!(flags & USE_REAL_VBLANKSTART)) 835 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 836 837 /* Test scanout position against vblank region. */ 838 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 839 in_vbl = false; 840 841 /* In vblank? */ 842 if (in_vbl) 843 ret |= DRM_SCANOUTPOS_IN_VBLANK; 844 845 /* Called from driver internal vblank counter query code? */ 846 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 847 /* Caller wants distance from fudged earlier vbl_start */ 848 *vpos -= vbl_start; 849 return ret; 850 } 851 852 /* Check if inside vblank area and apply corrective offsets: 853 * vpos will then be >=0 in video scanout area, but negative 854 * within vblank area, counting down the number of lines until 855 * start of scanout. 856 */ 857 858 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 859 if (in_vbl && (*vpos >= vbl_start)) { 860 vtotal = mode->crtc_vtotal; 861 *vpos = *vpos - vtotal; 862 } 863 864 /* Correct for shifted end of vbl at vbl_end. */ 865 *vpos = *vpos - vbl_end; 866 867 return ret; 868 } 869 870 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc) 871 { 872 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 873 return AMDGPU_CRTC_IRQ_NONE; 874 875 switch (crtc) { 876 case 0: 877 return AMDGPU_CRTC_IRQ_VBLANK1; 878 case 1: 879 return AMDGPU_CRTC_IRQ_VBLANK2; 880 case 2: 881 return AMDGPU_CRTC_IRQ_VBLANK3; 882 case 3: 883 return AMDGPU_CRTC_IRQ_VBLANK4; 884 case 4: 885 return AMDGPU_CRTC_IRQ_VBLANK5; 886 case 5: 887 return AMDGPU_CRTC_IRQ_VBLANK6; 888 default: 889 return AMDGPU_CRTC_IRQ_NONE; 890 } 891 } 892