1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/ktime.h> 29 #include <linux/pagemap.h> 30 #include <drm/drmP.h> 31 #include <drm/amdgpu_drm.h> 32 #include "amdgpu.h" 33 #include "amdgpu_display.h" 34 35 void amdgpu_gem_object_free(struct drm_gem_object *gobj) 36 { 37 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); 38 39 if (robj) { 40 amdgpu_mn_unregister(robj); 41 amdgpu_bo_unref(&robj); 42 } 43 } 44 45 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 46 int alignment, u32 initial_domain, 47 u64 flags, enum ttm_bo_type type, 48 struct reservation_object *resv, 49 struct drm_gem_object **obj) 50 { 51 struct amdgpu_bo *bo; 52 struct amdgpu_bo_param bp; 53 int r; 54 55 memset(&bp, 0, sizeof(bp)); 56 *obj = NULL; 57 /* At least align on page size */ 58 if (alignment < PAGE_SIZE) { 59 alignment = PAGE_SIZE; 60 } 61 62 bp.size = size; 63 bp.byte_align = alignment; 64 bp.type = type; 65 bp.resv = resv; 66 bp.preferred_domain = initial_domain; 67 retry: 68 bp.flags = flags; 69 bp.domain = initial_domain; 70 r = amdgpu_bo_create(adev, &bp, &bo); 71 if (r) { 72 if (r != -ERESTARTSYS) { 73 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) { 74 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 75 goto retry; 76 } 77 78 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { 79 initial_domain |= AMDGPU_GEM_DOMAIN_GTT; 80 goto retry; 81 } 82 DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n", 83 size, initial_domain, alignment, r); 84 } 85 return r; 86 } 87 *obj = &bo->gem_base; 88 89 return 0; 90 } 91 92 void amdgpu_gem_force_release(struct amdgpu_device *adev) 93 { 94 struct drm_device *ddev = adev->ddev; 95 struct drm_file *file; 96 97 mutex_lock(&ddev->filelist_mutex); 98 99 list_for_each_entry(file, &ddev->filelist, lhead) { 100 struct drm_gem_object *gobj; 101 int handle; 102 103 WARN_ONCE(1, "Still active user space clients!\n"); 104 lockmgr(&file->table_lock, LK_EXCLUSIVE); 105 idr_for_each_entry(&file->object_idr, gobj, handle) { 106 WARN_ONCE(1, "And also active allocations!\n"); 107 drm_gem_object_put_unlocked(gobj); 108 } 109 idr_destroy(&file->object_idr); 110 lockmgr(&file->table_lock, LK_RELEASE); 111 } 112 113 mutex_unlock(&ddev->filelist_mutex); 114 } 115 116 /* 117 * Call from drm_gem_handle_create which appear in both new and open ioctl 118 * case. 119 */ 120 int amdgpu_gem_object_open(struct drm_gem_object *obj, 121 struct drm_file *file_priv) 122 { 123 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); 124 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 125 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 126 struct amdgpu_vm *vm = &fpriv->vm; 127 struct amdgpu_bo_va *bo_va; 128 struct mm_struct *mm; 129 int r; 130 131 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); 132 if (mm && mm != current->mm) 133 return -EPERM; 134 135 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && 136 abo->tbo.resv != vm->root.base.bo->tbo.resv) 137 return -EPERM; 138 139 r = amdgpu_bo_reserve(abo, false); 140 if (r) 141 return r; 142 143 bo_va = amdgpu_vm_bo_find(vm, abo); 144 if (!bo_va) { 145 bo_va = amdgpu_vm_bo_add(adev, vm, abo); 146 } else { 147 ++bo_va->ref_count; 148 } 149 amdgpu_bo_unreserve(abo); 150 return 0; 151 } 152 153 void amdgpu_gem_object_close(struct drm_gem_object *obj, 154 struct drm_file *file_priv) 155 { 156 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 157 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 158 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 159 struct amdgpu_vm *vm = &fpriv->vm; 160 161 struct amdgpu_bo_list_entry vm_pd; 162 struct list_head list, duplicates; 163 struct ttm_validate_buffer tv; 164 struct ww_acquire_ctx ticket; 165 struct amdgpu_bo_va *bo_va; 166 int r; 167 168 INIT_LIST_HEAD(&list); 169 INIT_LIST_HEAD(&duplicates); 170 171 tv.bo = &bo->tbo; 172 tv.shared = true; 173 list_add(&tv.head, &list); 174 175 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd); 176 177 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); 178 if (r) { 179 dev_err(adev->dev, "leaking bo va because " 180 "we fail to reserve bo (%d)\n", r); 181 return; 182 } 183 bo_va = amdgpu_vm_bo_find(vm, bo); 184 if (bo_va && --bo_va->ref_count == 0) { 185 amdgpu_vm_bo_rmv(adev, bo_va); 186 187 if (amdgpu_vm_ready(vm)) { 188 struct dma_fence *fence = NULL; 189 190 r = amdgpu_vm_clear_freed(adev, vm, &fence); 191 if (unlikely(r)) { 192 dev_err(adev->dev, "failed to clear page " 193 "tables on GEM object close (%d)\n", r); 194 } 195 196 if (fence) { 197 amdgpu_bo_fence(bo, fence, true); 198 dma_fence_put(fence); 199 } 200 } 201 } 202 ttm_eu_backoff_reservation(&ticket, &list); 203 } 204 205 /* 206 * GEM ioctls. 207 */ 208 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 209 struct drm_file *filp) 210 { 211 struct amdgpu_device *adev = dev->dev_private; 212 struct amdgpu_fpriv *fpriv = filp->driver_priv; 213 struct amdgpu_vm *vm = &fpriv->vm; 214 union drm_amdgpu_gem_create *args = data; 215 uint64_t flags = args->in.domain_flags; 216 uint64_t size = args->in.bo_size; 217 struct reservation_object *resv = NULL; 218 struct drm_gem_object *gobj; 219 uint32_t handle; 220 int r; 221 222 /* reject invalid gem flags */ 223 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 224 AMDGPU_GEM_CREATE_NO_CPU_ACCESS | 225 AMDGPU_GEM_CREATE_CPU_GTT_USWC | 226 AMDGPU_GEM_CREATE_VRAM_CLEARED | 227 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | 228 AMDGPU_GEM_CREATE_EXPLICIT_SYNC)) 229 230 return -EINVAL; 231 232 /* reject invalid gem domains */ 233 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK) 234 return -EINVAL; 235 236 /* create a gem object to contain this object in */ 237 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | 238 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 239 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 240 /* if gds bo is created from user space, it must be 241 * passed to bo list 242 */ 243 DRM_ERROR("GDS bo cannot be per-vm-bo\n"); 244 return -EINVAL; 245 } 246 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 247 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS) 248 size = size << AMDGPU_GDS_SHIFT; 249 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS) 250 size = size << AMDGPU_GWS_SHIFT; 251 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA) 252 size = size << AMDGPU_OA_SHIFT; 253 else 254 return -EINVAL; 255 } 256 size = roundup(size, PAGE_SIZE); 257 258 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 259 r = amdgpu_bo_reserve(vm->root.base.bo, false); 260 if (r) 261 return r; 262 263 resv = vm->root.base.bo->tbo.resv; 264 } 265 266 r = amdgpu_gem_object_create(adev, size, args->in.alignment, 267 (u32)(0xffffffff & args->in.domains), 268 flags, ttm_bo_type_device, resv, &gobj); 269 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 270 if (!r) { 271 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); 272 273 abo->parent = amdgpu_bo_ref(vm->root.base.bo); 274 } 275 amdgpu_bo_unreserve(vm->root.base.bo); 276 } 277 if (r) 278 return r; 279 280 r = drm_gem_handle_create(filp, gobj, &handle); 281 /* drop reference from allocate - handle holds it now */ 282 drm_gem_object_put_unlocked(gobj); 283 if (r) 284 return r; 285 286 memset(args, 0, sizeof(*args)); 287 args->out.handle = handle; 288 return 0; 289 } 290 291 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 292 struct drm_file *filp) 293 { 294 kprintf("amdgpu_gem_userptr_ioctl: not implemented\n"); 295 return -EINVAL; 296 #if 0 297 struct ttm_operation_ctx ctx = { true, false }; 298 struct amdgpu_device *adev = dev->dev_private; 299 struct drm_amdgpu_gem_userptr *args = data; 300 struct drm_gem_object *gobj; 301 struct amdgpu_bo *bo; 302 uint32_t handle; 303 int r; 304 305 if (offset_in_page(args->addr | args->size)) 306 return -EINVAL; 307 308 /* reject unknown flag values */ 309 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | 310 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | 311 AMDGPU_GEM_USERPTR_REGISTER)) 312 return -EINVAL; 313 314 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && 315 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { 316 317 /* if we want to write to it we must install a MMU notifier */ 318 return -EACCES; 319 } 320 321 /* create a gem object to contain this object in */ 322 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, 323 0, ttm_bo_type_device, NULL, &gobj); 324 if (r) 325 return r; 326 327 bo = gem_to_amdgpu_bo(gobj); 328 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; 329 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 330 r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags); 331 if (r) 332 goto release_object; 333 334 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { 335 r = amdgpu_mn_register(bo, args->addr); 336 if (r) 337 goto release_object; 338 } 339 340 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { 341 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm, 342 bo->tbo.ttm->pages); 343 if (r) 344 goto release_object; 345 346 r = amdgpu_bo_reserve(bo, true); 347 if (r) 348 goto free_pages; 349 350 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 351 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 352 amdgpu_bo_unreserve(bo); 353 if (r) 354 goto free_pages; 355 } 356 357 r = drm_gem_handle_create(filp, gobj, &handle); 358 /* drop reference from allocate - handle holds it now */ 359 drm_gem_object_put_unlocked(gobj); 360 if (r) 361 return r; 362 363 args->handle = handle; 364 return 0; 365 366 free_pages: 367 release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages); 368 369 release_object: 370 drm_gem_object_put_unlocked(gobj); 371 372 return r; 373 #endif 374 } 375 376 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 377 struct drm_device *dev, 378 uint32_t handle, uint64_t *offset_p) 379 { 380 struct drm_gem_object *gobj; 381 struct amdgpu_bo *robj; 382 383 gobj = drm_gem_object_lookup(filp, handle); 384 if (gobj == NULL) { 385 return -ENOENT; 386 } 387 robj = gem_to_amdgpu_bo(gobj); 388 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || 389 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { 390 drm_gem_object_put_unlocked(gobj); 391 return -EPERM; 392 } 393 *offset_p = amdgpu_bo_mmap_offset(robj); 394 drm_gem_object_put_unlocked(gobj); 395 return 0; 396 } 397 398 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 399 struct drm_file *filp) 400 { 401 union drm_amdgpu_gem_mmap *args = data; 402 uint32_t handle = args->in.handle; 403 memset(args, 0, sizeof(*args)); 404 return amdgpu_mode_dumb_mmap(filp, dev, handle, (uint64_t *)&args->out.addr_ptr); 405 } 406 407 /** 408 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value 409 * 410 * @timeout_ns: timeout in ns 411 * 412 * Calculate the timeout in jiffies from an absolute timeout in ns. 413 */ 414 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) 415 { 416 unsigned long timeout_jiffies; 417 ktime_t timeout; 418 419 /* clamp timeout if it's to large */ 420 if (((int64_t)timeout_ns) < 0) 421 return MAX_SCHEDULE_TIMEOUT; 422 423 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); 424 if (ktime_to_ns(timeout) < 0) 425 return 0; 426 427 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); 428 /* clamp timeout to avoid unsigned-> signed overflow */ 429 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) 430 return MAX_SCHEDULE_TIMEOUT - 1; 431 432 return timeout_jiffies; 433 } 434 435 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 436 struct drm_file *filp) 437 { 438 union drm_amdgpu_gem_wait_idle *args = data; 439 struct drm_gem_object *gobj; 440 struct amdgpu_bo *robj; 441 uint32_t handle = args->in.handle; 442 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); 443 int r = 0; 444 long ret; 445 446 gobj = drm_gem_object_lookup(filp, handle); 447 if (gobj == NULL) { 448 return -ENOENT; 449 } 450 robj = gem_to_amdgpu_bo(gobj); 451 ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, 452 timeout); 453 454 /* ret == 0 means not signaled, 455 * ret > 0 means signaled 456 * ret < 0 means interrupted before timeout 457 */ 458 if (ret >= 0) { 459 memset(args, 0, sizeof(*args)); 460 args->out.status = (ret == 0); 461 } else 462 r = ret; 463 464 drm_gem_object_put_unlocked(gobj); 465 return r; 466 } 467 468 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 469 struct drm_file *filp) 470 { 471 struct drm_amdgpu_gem_metadata *args = data; 472 struct drm_gem_object *gobj; 473 struct amdgpu_bo *robj; 474 int r = -1; 475 476 DRM_DEBUG("%d \n", args->handle); 477 gobj = drm_gem_object_lookup(filp, args->handle); 478 if (gobj == NULL) 479 return -ENOENT; 480 robj = gem_to_amdgpu_bo(gobj); 481 482 r = amdgpu_bo_reserve(robj, false); 483 if (unlikely(r != 0)) 484 goto out; 485 486 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { 487 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); 488 r = amdgpu_bo_get_metadata(robj, args->data.data, 489 sizeof(args->data.data), 490 &args->data.data_size_bytes, 491 (uint64_t *)&args->data.flags); 492 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { 493 if (args->data.data_size_bytes > sizeof(args->data.data)) { 494 r = -EINVAL; 495 goto unreserve; 496 } 497 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); 498 if (!r) 499 r = amdgpu_bo_set_metadata(robj, args->data.data, 500 args->data.data_size_bytes, 501 args->data.flags); 502 } 503 504 unreserve: 505 amdgpu_bo_unreserve(robj); 506 out: 507 drm_gem_object_put_unlocked(gobj); 508 return r; 509 } 510 511 /** 512 * amdgpu_gem_va_update_vm -update the bo_va in its VM 513 * 514 * @adev: amdgpu_device pointer 515 * @vm: vm to update 516 * @bo_va: bo_va to update 517 * @operation: map, unmap or clear 518 * 519 * Update the bo_va directly after setting its address. Errors are not 520 * vital here, so they are not reported back to userspace. 521 */ 522 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, 523 struct amdgpu_vm *vm, 524 struct amdgpu_bo_va *bo_va, 525 uint32_t operation) 526 { 527 int r; 528 529 if (!amdgpu_vm_ready(vm)) 530 return; 531 532 r = amdgpu_vm_clear_freed(adev, vm, NULL); 533 if (r) 534 goto error; 535 536 if (operation == AMDGPU_VA_OP_MAP || 537 operation == AMDGPU_VA_OP_REPLACE) { 538 r = amdgpu_vm_bo_update(adev, bo_va, false); 539 if (r) 540 goto error; 541 } 542 543 r = amdgpu_vm_update_directories(adev, vm); 544 545 error: 546 if (r && r != -ERESTARTSYS) 547 DRM_ERROR("Couldn't update BO_VA (%d)\n", r); 548 } 549 550 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 551 struct drm_file *filp) 552 { 553 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | 554 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | 555 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK; 556 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | 557 AMDGPU_VM_PAGE_PRT; 558 559 struct drm_amdgpu_gem_va *args = data; 560 struct drm_gem_object *gobj; 561 struct amdgpu_device *adev = dev->dev_private; 562 struct amdgpu_fpriv *fpriv = filp->driver_priv; 563 struct amdgpu_bo *abo; 564 struct amdgpu_bo_va *bo_va; 565 struct amdgpu_bo_list_entry vm_pd; 566 struct ttm_validate_buffer tv; 567 struct ww_acquire_ctx ticket; 568 struct list_head list, duplicates; 569 uint64_t va_flags; 570 uint64_t vm_size; 571 int r = 0; 572 573 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { 574 dev_dbg(&dev->pdev->dev, 575 "va_address 0x%LX is in reserved area 0x%LX\n", 576 args->va_address, AMDGPU_VA_RESERVED_SIZE); 577 return -EINVAL; 578 } 579 580 if (args->va_address >= AMDGPU_VA_HOLE_START && 581 args->va_address < AMDGPU_VA_HOLE_END) { 582 dev_dbg(&dev->pdev->dev, 583 "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n", 584 args->va_address, AMDGPU_VA_HOLE_START, 585 AMDGPU_VA_HOLE_END); 586 return -EINVAL; 587 } 588 589 args->va_address &= AMDGPU_VA_HOLE_MASK; 590 591 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 592 vm_size -= AMDGPU_VA_RESERVED_SIZE; 593 if (args->va_address + args->map_size > vm_size) { 594 dev_dbg(&dev->pdev->dev, 595 "va_address 0x%llx is in top reserved area 0x%lx\n", 596 args->va_address + args->map_size, vm_size); 597 return -EINVAL; 598 } 599 600 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { 601 dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n", 602 args->flags); 603 return -EINVAL; 604 } 605 606 switch (args->operation) { 607 case AMDGPU_VA_OP_MAP: 608 case AMDGPU_VA_OP_UNMAP: 609 case AMDGPU_VA_OP_CLEAR: 610 case AMDGPU_VA_OP_REPLACE: 611 break; 612 default: 613 dev_dbg(&dev->pdev->dev, "unsupported operation %d\n", 614 args->operation); 615 return -EINVAL; 616 } 617 618 INIT_LIST_HEAD(&list); 619 INIT_LIST_HEAD(&duplicates); 620 if ((args->operation != AMDGPU_VA_OP_CLEAR) && 621 !(args->flags & AMDGPU_VM_PAGE_PRT)) { 622 gobj = drm_gem_object_lookup(filp, args->handle); 623 if (gobj == NULL) 624 return -ENOENT; 625 abo = gem_to_amdgpu_bo(gobj); 626 tv.bo = &abo->tbo; 627 tv.shared = !!(abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID); 628 list_add(&tv.head, &list); 629 } else { 630 gobj = NULL; 631 abo = NULL; 632 } 633 634 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd); 635 636 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); 637 if (r) 638 goto error_unref; 639 640 if (abo) { 641 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); 642 if (!bo_va) { 643 r = -ENOENT; 644 goto error_backoff; 645 } 646 } else if (args->operation != AMDGPU_VA_OP_CLEAR) { 647 bo_va = fpriv->prt_va; 648 } else { 649 bo_va = NULL; 650 } 651 652 switch (args->operation) { 653 case AMDGPU_VA_OP_MAP: 654 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address, 655 args->map_size); 656 if (r) 657 goto error_backoff; 658 659 va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags); 660 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, 661 args->offset_in_bo, args->map_size, 662 va_flags); 663 break; 664 case AMDGPU_VA_OP_UNMAP: 665 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); 666 break; 667 668 case AMDGPU_VA_OP_CLEAR: 669 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm, 670 args->va_address, 671 args->map_size); 672 break; 673 case AMDGPU_VA_OP_REPLACE: 674 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address, 675 args->map_size); 676 if (r) 677 goto error_backoff; 678 679 va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags); 680 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, 681 args->offset_in_bo, args->map_size, 682 va_flags); 683 break; 684 default: 685 break; 686 } 687 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug) 688 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, 689 args->operation); 690 691 error_backoff: 692 ttm_eu_backoff_reservation(&ticket, &list); 693 694 error_unref: 695 drm_gem_object_put_unlocked(gobj); 696 return r; 697 } 698 699 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 700 struct drm_file *filp) 701 { 702 struct amdgpu_device *adev = dev->dev_private; 703 struct drm_amdgpu_gem_op *args = data; 704 struct drm_gem_object *gobj; 705 struct amdgpu_bo *robj; 706 int r; 707 708 gobj = drm_gem_object_lookup(filp, args->handle); 709 if (gobj == NULL) { 710 return -ENOENT; 711 } 712 robj = gem_to_amdgpu_bo(gobj); 713 714 r = amdgpu_bo_reserve(robj, false); 715 if (unlikely(r)) 716 goto out; 717 718 switch (args->op) { 719 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { 720 struct drm_amdgpu_gem_create_in info; 721 void __user *out = u64_to_user_ptr(args->value); 722 723 info.bo_size = robj->gem_base.size; 724 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; 725 info.domains = robj->preferred_domains; 726 info.domain_flags = robj->flags; 727 amdgpu_bo_unreserve(robj); 728 if (copy_to_user(out, &info, sizeof(info))) 729 r = -EFAULT; 730 break; 731 } 732 case AMDGPU_GEM_OP_SET_PLACEMENT: 733 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) { 734 r = -EINVAL; 735 amdgpu_bo_unreserve(robj); 736 break; 737 } 738 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { 739 r = -EPERM; 740 amdgpu_bo_unreserve(robj); 741 break; 742 } 743 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | 744 AMDGPU_GEM_DOMAIN_GTT | 745 AMDGPU_GEM_DOMAIN_CPU); 746 robj->allowed_domains = robj->preferred_domains; 747 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 748 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 749 750 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 751 amdgpu_vm_bo_invalidate(adev, robj, true); 752 753 amdgpu_bo_unreserve(robj); 754 break; 755 default: 756 amdgpu_bo_unreserve(robj); 757 r = -EINVAL; 758 } 759 760 out: 761 drm_gem_object_put_unlocked(gobj); 762 return r; 763 } 764 765 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 766 struct drm_device *dev, 767 struct drm_mode_create_dumb *args) 768 { 769 struct amdgpu_device *adev = dev->dev_private; 770 struct drm_gem_object *gobj; 771 uint32_t handle; 772 u32 domain; 773 int r; 774 775 args->pitch = amdgpu_align_pitch(adev, args->width, 776 DIV_ROUND_UP(args->bpp, 8), 0); 777 args->size = (u64)args->pitch * args->height; 778 args->size = ALIGN(args->size, PAGE_SIZE); 779 domain = amdgpu_bo_get_preferred_pin_domain(adev, 780 amdgpu_display_supported_domains(adev)); 781 r = amdgpu_gem_object_create(adev, args->size, 0, domain, 782 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 783 ttm_bo_type_device, NULL, &gobj); 784 if (r) 785 return -ENOMEM; 786 787 r = drm_gem_handle_create(file_priv, gobj, &handle); 788 /* drop reference from allocate - handle holds it now */ 789 drm_gem_object_put_unlocked(gobj); 790 if (r) { 791 return r; 792 } 793 args->handle = handle; 794 return 0; 795 } 796 797 #if defined(CONFIG_DEBUG_FS) 798 799 #define amdgpu_debugfs_gem_bo_print_flag(m, bo, flag) \ 800 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \ 801 seq_printf((m), " " #flag); \ 802 } 803 804 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data) 805 { 806 struct drm_gem_object *gobj = ptr; 807 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); 808 struct seq_file *m = data; 809 810 struct dma_buf_attachment *attachment; 811 struct dma_buf *dma_buf; 812 unsigned domain; 813 const char *placement; 814 unsigned pin_count; 815 816 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 817 switch (domain) { 818 case AMDGPU_GEM_DOMAIN_VRAM: 819 placement = "VRAM"; 820 break; 821 case AMDGPU_GEM_DOMAIN_GTT: 822 placement = " GTT"; 823 break; 824 case AMDGPU_GEM_DOMAIN_CPU: 825 default: 826 placement = " CPU"; 827 break; 828 } 829 seq_printf(m, "\t0x%08x: %12ld byte %s", 830 id, amdgpu_bo_size(bo), placement); 831 832 pin_count = READ_ONCE(bo->pin_count); 833 if (pin_count) 834 seq_printf(m, " pin count %d", pin_count); 835 836 dma_buf = READ_ONCE(bo->gem_base.dma_buf); 837 attachment = READ_ONCE(bo->gem_base.import_attach); 838 839 if (attachment) 840 seq_printf(m, " imported from %p", dma_buf); 841 else if (dma_buf) 842 seq_printf(m, " exported as %p", dma_buf); 843 844 amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED); 845 amdgpu_debugfs_gem_bo_print_flag(m, bo, NO_CPU_ACCESS); 846 amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_GTT_USWC); 847 amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CLEARED); 848 amdgpu_debugfs_gem_bo_print_flag(m, bo, SHADOW); 849 amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CONTIGUOUS); 850 amdgpu_debugfs_gem_bo_print_flag(m, bo, VM_ALWAYS_VALID); 851 amdgpu_debugfs_gem_bo_print_flag(m, bo, EXPLICIT_SYNC); 852 853 seq_printf(m, "\n"); 854 855 return 0; 856 } 857 858 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) 859 { 860 struct drm_info_node *node = (struct drm_info_node *)m->private; 861 struct drm_device *dev = node->minor->dev; 862 struct drm_file *file; 863 int r; 864 865 r = mutex_lock_interruptible(&dev->filelist_mutex); 866 if (r) 867 return r; 868 869 list_for_each_entry(file, &dev->filelist, lhead) { 870 struct task_struct *task; 871 872 /* 873 * Although we have a valid reference on file->pid, that does 874 * not guarantee that the task_struct who called get_pid() is 875 * still alive (e.g. get_pid(current) => fork() => exit()). 876 * Therefore, we need to protect this ->comm access using RCU. 877 */ 878 rcu_read_lock(); 879 task = pid_task(file->pid, PIDTYPE_PID); 880 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid), 881 task ? task->comm : "<unknown>"); 882 rcu_read_unlock(); 883 884 lockmgr(&file->table_lock, LK_EXCLUSIVE); 885 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m); 886 lockmgr(&file->table_lock, LK_RELEASE); 887 } 888 889 mutex_unlock(&dev->filelist_mutex); 890 return 0; 891 } 892 893 static const struct drm_info_list amdgpu_debugfs_gem_list[] = { 894 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, 895 }; 896 #endif 897 898 int amdgpu_debugfs_gem_init(struct amdgpu_device *adev) 899 { 900 #if defined(CONFIG_DEBUG_FS) 901 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1); 902 #endif 903 return 0; 904 } 905