1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_GFX_H__ 25 #define __AMDGPU_GFX_H__ 26 27 int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg); 28 void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg); 29 30 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, 31 unsigned max_sh); 32 33 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev); 34 35 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, 36 struct amdgpu_ring *ring, 37 struct amdgpu_irq_src *irq); 38 39 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring, 40 struct amdgpu_irq_src *irq); 41 42 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev); 43 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, 44 unsigned hpd_size); 45 46 int amdgpu_gfx_compute_mqd_sw_init(struct amdgpu_device *adev, 47 unsigned mqd_size); 48 void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device *adev); 49 50 /** 51 * amdgpu_gfx_create_bitmask - create a bitmask 52 * 53 * @bit_width: length of the mask 54 * 55 * create a variable length bit mask. 56 * Returns the bitmask. 57 */ 58 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width) 59 { 60 return (u32)((1ULL << bit_width) - 1); 61 } 62 63 static inline int amdgpu_gfx_queue_to_bit(struct amdgpu_device *adev, 64 int mec, int pipe, int queue) 65 { 66 int bit = 0; 67 68 bit += mec * adev->gfx.mec.num_pipe_per_mec 69 * adev->gfx.mec.num_queue_per_pipe; 70 bit += pipe * adev->gfx.mec.num_queue_per_pipe; 71 bit += queue; 72 73 return bit; 74 } 75 76 static inline void amdgpu_gfx_bit_to_queue(struct amdgpu_device *adev, int bit, 77 int *mec, int *pipe, int *queue) 78 { 79 *queue = bit % adev->gfx.mec.num_queue_per_pipe; 80 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) 81 % adev->gfx.mec.num_pipe_per_mec; 82 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) 83 / adev->gfx.mec.num_pipe_per_mec; 84 85 } 86 static inline bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, 87 int mec, int pipe, int queue) 88 { 89 return test_bit(amdgpu_gfx_queue_to_bit(adev, mec, pipe, queue), 90 adev->gfx.mec.queue_bitmap); 91 } 92 93 #endif 94