1b843c749SSergey Zigachev /* 2b843c749SSergey Zigachev * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3b843c749SSergey Zigachev * VA Linux Systems Inc., Fremont, California. 4b843c749SSergey Zigachev * Copyright 2008 Red Hat Inc. 5b843c749SSergey Zigachev * 6b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 7b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 8b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 9b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 11b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 12b843c749SSergey Zigachev * 13b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 14b843c749SSergey Zigachev * all copies or substantial portions of the Software. 15b843c749SSergey Zigachev * 16b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 23b843c749SSergey Zigachev * 24b843c749SSergey Zigachev * Original Authors: 25b843c749SSergey Zigachev * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26b843c749SSergey Zigachev * 27b843c749SSergey Zigachev * Kernel port Author: Dave Airlie 28b843c749SSergey Zigachev */ 29b843c749SSergey Zigachev 30b843c749SSergey Zigachev #ifndef AMDGPU_MODE_H 31b843c749SSergey Zigachev #define AMDGPU_MODE_H 32b843c749SSergey Zigachev 33b843c749SSergey Zigachev #include <drm/drm_crtc.h> 34b843c749SSergey Zigachev #include <drm/drm_edid.h> 35b843c749SSergey Zigachev #include <drm/drm_encoder.h> 36b843c749SSergey Zigachev #include <drm/drm_dp_helper.h> 37b843c749SSergey Zigachev #include <drm/drm_fixed.h> 38b843c749SSergey Zigachev #include <drm/drm_crtc_helper.h> 39b843c749SSergey Zigachev #include <drm/drm_fb_helper.h> 40b843c749SSergey Zigachev #include <drm/drm_plane_helper.h> 41b843c749SSergey Zigachev #include <drm/drm_fb_helper.h> 42b843c749SSergey Zigachev #include <linux/i2c.h> 43b843c749SSergey Zigachev #include <linux/i2c-algo-bit.h> 44b843c749SSergey Zigachev #include <linux/hrtimer.h> 45b843c749SSergey Zigachev #include "amdgpu_irq.h" 46b843c749SSergey Zigachev 47b843c749SSergey Zigachev #include <drm/drm_dp_mst_helper.h> 48b843c749SSergey Zigachev #include "modules/inc/mod_freesync.h" 49b843c749SSergey Zigachev 50b843c749SSergey Zigachev struct amdgpu_bo; 51b843c749SSergey Zigachev struct amdgpu_device; 52b843c749SSergey Zigachev struct amdgpu_encoder; 53b843c749SSergey Zigachev struct amdgpu_router; 54b843c749SSergey Zigachev struct amdgpu_hpd; 55b843c749SSergey Zigachev 56b843c749SSergey Zigachev #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base) 57b843c749SSergey Zigachev #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base) 58b843c749SSergey Zigachev #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base) 59b843c749SSergey Zigachev #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base) 60b843c749SSergey Zigachev #define to_amdgpu_plane(x) container_of(x, struct amdgpu_plane, base) 61b843c749SSergey Zigachev 62b843c749SSergey Zigachev #define to_dm_plane_state(x) container_of(x, struct dm_plane_state, base); 63b843c749SSergey Zigachev 64b843c749SSergey Zigachev #define AMDGPU_MAX_HPD_PINS 6 65b843c749SSergey Zigachev #define AMDGPU_MAX_CRTCS 6 66b843c749SSergey Zigachev #define AMDGPU_MAX_PLANES 6 67b843c749SSergey Zigachev #define AMDGPU_MAX_AFMT_BLOCKS 9 68b843c749SSergey Zigachev 69b843c749SSergey Zigachev enum amdgpu_rmx_type { 70b843c749SSergey Zigachev RMX_OFF, 71b843c749SSergey Zigachev RMX_FULL, 72b843c749SSergey Zigachev RMX_CENTER, 73b843c749SSergey Zigachev RMX_ASPECT 74b843c749SSergey Zigachev }; 75b843c749SSergey Zigachev 76b843c749SSergey Zigachev enum amdgpu_underscan_type { 77b843c749SSergey Zigachev UNDERSCAN_OFF, 78b843c749SSergey Zigachev UNDERSCAN_ON, 79b843c749SSergey Zigachev UNDERSCAN_AUTO, 80b843c749SSergey Zigachev }; 81b843c749SSergey Zigachev 82b843c749SSergey Zigachev #define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50 83b843c749SSergey Zigachev #define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10 84b843c749SSergey Zigachev 85b843c749SSergey Zigachev enum amdgpu_hpd_id { 86b843c749SSergey Zigachev AMDGPU_HPD_1 = 0, 87b843c749SSergey Zigachev AMDGPU_HPD_2, 88b843c749SSergey Zigachev AMDGPU_HPD_3, 89b843c749SSergey Zigachev AMDGPU_HPD_4, 90b843c749SSergey Zigachev AMDGPU_HPD_5, 91b843c749SSergey Zigachev AMDGPU_HPD_6, 92b843c749SSergey Zigachev AMDGPU_HPD_NONE = 0xff, 93b843c749SSergey Zigachev }; 94b843c749SSergey Zigachev 95b843c749SSergey Zigachev enum amdgpu_crtc_irq { 96b843c749SSergey Zigachev AMDGPU_CRTC_IRQ_VBLANK1 = 0, 97b843c749SSergey Zigachev AMDGPU_CRTC_IRQ_VBLANK2, 98b843c749SSergey Zigachev AMDGPU_CRTC_IRQ_VBLANK3, 99b843c749SSergey Zigachev AMDGPU_CRTC_IRQ_VBLANK4, 100b843c749SSergey Zigachev AMDGPU_CRTC_IRQ_VBLANK5, 101b843c749SSergey Zigachev AMDGPU_CRTC_IRQ_VBLANK6, 102b843c749SSergey Zigachev AMDGPU_CRTC_IRQ_VLINE1, 103b843c749SSergey Zigachev AMDGPU_CRTC_IRQ_VLINE2, 104b843c749SSergey Zigachev AMDGPU_CRTC_IRQ_VLINE3, 105b843c749SSergey Zigachev AMDGPU_CRTC_IRQ_VLINE4, 106b843c749SSergey Zigachev AMDGPU_CRTC_IRQ_VLINE5, 107b843c749SSergey Zigachev AMDGPU_CRTC_IRQ_VLINE6, 108b843c749SSergey Zigachev AMDGPU_CRTC_IRQ_NONE = 0xff 109b843c749SSergey Zigachev }; 110b843c749SSergey Zigachev 111b843c749SSergey Zigachev enum amdgpu_pageflip_irq { 112b843c749SSergey Zigachev AMDGPU_PAGEFLIP_IRQ_D1 = 0, 113b843c749SSergey Zigachev AMDGPU_PAGEFLIP_IRQ_D2, 114b843c749SSergey Zigachev AMDGPU_PAGEFLIP_IRQ_D3, 115b843c749SSergey Zigachev AMDGPU_PAGEFLIP_IRQ_D4, 116b843c749SSergey Zigachev AMDGPU_PAGEFLIP_IRQ_D5, 117b843c749SSergey Zigachev AMDGPU_PAGEFLIP_IRQ_D6, 118b843c749SSergey Zigachev AMDGPU_PAGEFLIP_IRQ_NONE = 0xff 119b843c749SSergey Zigachev }; 120b843c749SSergey Zigachev 121b843c749SSergey Zigachev enum amdgpu_flip_status { 122b843c749SSergey Zigachev AMDGPU_FLIP_NONE, 123b843c749SSergey Zigachev AMDGPU_FLIP_PENDING, 124b843c749SSergey Zigachev AMDGPU_FLIP_SUBMITTED 125b843c749SSergey Zigachev }; 126b843c749SSergey Zigachev 127b843c749SSergey Zigachev #define AMDGPU_MAX_I2C_BUS 16 128b843c749SSergey Zigachev 129b843c749SSergey Zigachev /* amdgpu gpio-based i2c 130b843c749SSergey Zigachev * 1. "mask" reg and bits 131b843c749SSergey Zigachev * grabs the gpio pins for software use 132b843c749SSergey Zigachev * 0=not held 1=held 133b843c749SSergey Zigachev * 2. "a" reg and bits 134b843c749SSergey Zigachev * output pin value 135b843c749SSergey Zigachev * 0=low 1=high 136b843c749SSergey Zigachev * 3. "en" reg and bits 137b843c749SSergey Zigachev * sets the pin direction 138b843c749SSergey Zigachev * 0=input 1=output 139b843c749SSergey Zigachev * 4. "y" reg and bits 140b843c749SSergey Zigachev * input pin value 141b843c749SSergey Zigachev * 0=low 1=high 142b843c749SSergey Zigachev */ 143b843c749SSergey Zigachev struct amdgpu_i2c_bus_rec { 144b843c749SSergey Zigachev bool valid; 145b843c749SSergey Zigachev /* id used by atom */ 146b843c749SSergey Zigachev uint8_t i2c_id; 147b843c749SSergey Zigachev /* id used by atom */ 148b843c749SSergey Zigachev enum amdgpu_hpd_id hpd; 149b843c749SSergey Zigachev /* can be used with hw i2c engine */ 150b843c749SSergey Zigachev bool hw_capable; 151b843c749SSergey Zigachev /* uses multi-media i2c engine */ 152b843c749SSergey Zigachev bool mm_i2c; 153b843c749SSergey Zigachev /* regs and bits */ 154b843c749SSergey Zigachev uint32_t mask_clk_reg; 155b843c749SSergey Zigachev uint32_t mask_data_reg; 156b843c749SSergey Zigachev uint32_t a_clk_reg; 157b843c749SSergey Zigachev uint32_t a_data_reg; 158b843c749SSergey Zigachev uint32_t en_clk_reg; 159b843c749SSergey Zigachev uint32_t en_data_reg; 160b843c749SSergey Zigachev uint32_t y_clk_reg; 161b843c749SSergey Zigachev uint32_t y_data_reg; 162b843c749SSergey Zigachev uint32_t mask_clk_mask; 163b843c749SSergey Zigachev uint32_t mask_data_mask; 164b843c749SSergey Zigachev uint32_t a_clk_mask; 165b843c749SSergey Zigachev uint32_t a_data_mask; 166b843c749SSergey Zigachev uint32_t en_clk_mask; 167b843c749SSergey Zigachev uint32_t en_data_mask; 168b843c749SSergey Zigachev uint32_t y_clk_mask; 169b843c749SSergey Zigachev uint32_t y_data_mask; 170b843c749SSergey Zigachev }; 171b843c749SSergey Zigachev 172b843c749SSergey Zigachev #define AMDGPU_MAX_BIOS_CONNECTOR 16 173b843c749SSergey Zigachev 174b843c749SSergey Zigachev /* pll flags */ 175b843c749SSergey Zigachev #define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0) 176b843c749SSergey Zigachev #define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1) 177b843c749SSergey Zigachev #define AMDGPU_PLL_USE_REF_DIV (1 << 2) 178b843c749SSergey Zigachev #define AMDGPU_PLL_LEGACY (1 << 3) 179b843c749SSergey Zigachev #define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4) 180b843c749SSergey Zigachev #define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5) 181b843c749SSergey Zigachev #define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6) 182b843c749SSergey Zigachev #define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7) 183b843c749SSergey Zigachev #define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8) 184b843c749SSergey Zigachev #define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9) 185b843c749SSergey Zigachev #define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10) 186b843c749SSergey Zigachev #define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11) 187b843c749SSergey Zigachev #define AMDGPU_PLL_USE_POST_DIV (1 << 12) 188b843c749SSergey Zigachev #define AMDGPU_PLL_IS_LCD (1 << 13) 189b843c749SSergey Zigachev #define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 190b843c749SSergey Zigachev 191b843c749SSergey Zigachev struct amdgpu_pll { 192b843c749SSergey Zigachev /* reference frequency */ 193b843c749SSergey Zigachev uint32_t reference_freq; 194b843c749SSergey Zigachev 195b843c749SSergey Zigachev /* fixed dividers */ 196b843c749SSergey Zigachev uint32_t reference_div; 197b843c749SSergey Zigachev uint32_t post_div; 198b843c749SSergey Zigachev 199b843c749SSergey Zigachev /* pll in/out limits */ 200b843c749SSergey Zigachev uint32_t pll_in_min; 201b843c749SSergey Zigachev uint32_t pll_in_max; 202b843c749SSergey Zigachev uint32_t pll_out_min; 203b843c749SSergey Zigachev uint32_t pll_out_max; 204b843c749SSergey Zigachev uint32_t lcd_pll_out_min; 205b843c749SSergey Zigachev uint32_t lcd_pll_out_max; 206b843c749SSergey Zigachev uint32_t best_vco; 207b843c749SSergey Zigachev 208b843c749SSergey Zigachev /* divider limits */ 209b843c749SSergey Zigachev uint32_t min_ref_div; 210b843c749SSergey Zigachev uint32_t max_ref_div; 211b843c749SSergey Zigachev uint32_t min_post_div; 212b843c749SSergey Zigachev uint32_t max_post_div; 213b843c749SSergey Zigachev uint32_t min_feedback_div; 214b843c749SSergey Zigachev uint32_t max_feedback_div; 215b843c749SSergey Zigachev uint32_t min_frac_feedback_div; 216b843c749SSergey Zigachev uint32_t max_frac_feedback_div; 217b843c749SSergey Zigachev 218b843c749SSergey Zigachev /* flags for the current clock */ 219b843c749SSergey Zigachev uint32_t flags; 220b843c749SSergey Zigachev 221b843c749SSergey Zigachev /* pll id */ 222b843c749SSergey Zigachev uint32_t id; 223b843c749SSergey Zigachev }; 224b843c749SSergey Zigachev 225b843c749SSergey Zigachev struct amdgpu_i2c_chan { 226b843c749SSergey Zigachev struct i2c_adapter adapter; 227b843c749SSergey Zigachev struct drm_device *dev; 228b843c749SSergey Zigachev struct i2c_algo_bit_data bit; 229b843c749SSergey Zigachev struct amdgpu_i2c_bus_rec rec; 230b843c749SSergey Zigachev struct drm_dp_aux aux; 231b843c749SSergey Zigachev bool has_aux; 232*78973132SSergey Zigachev struct lock mutex; 233b843c749SSergey Zigachev }; 234b843c749SSergey Zigachev 235b843c749SSergey Zigachev struct amdgpu_fbdev; 236b843c749SSergey Zigachev 237b843c749SSergey Zigachev struct amdgpu_afmt { 238b843c749SSergey Zigachev bool enabled; 239b843c749SSergey Zigachev int offset; 240b843c749SSergey Zigachev bool last_buffer_filled_status; 241b843c749SSergey Zigachev int id; 242b843c749SSergey Zigachev struct amdgpu_audio_pin *pin; 243b843c749SSergey Zigachev }; 244b843c749SSergey Zigachev 245b843c749SSergey Zigachev /* 246b843c749SSergey Zigachev * Audio 247b843c749SSergey Zigachev */ 248b843c749SSergey Zigachev struct amdgpu_audio_pin { 249b843c749SSergey Zigachev int channels; 250b843c749SSergey Zigachev int rate; 251b843c749SSergey Zigachev int bits_per_sample; 252b843c749SSergey Zigachev u8 status_bits; 253b843c749SSergey Zigachev u8 category_code; 254b843c749SSergey Zigachev u32 offset; 255b843c749SSergey Zigachev bool connected; 256b843c749SSergey Zigachev u32 id; 257b843c749SSergey Zigachev }; 258b843c749SSergey Zigachev 259b843c749SSergey Zigachev struct amdgpu_audio { 260b843c749SSergey Zigachev bool enabled; 261b843c749SSergey Zigachev struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS]; 262b843c749SSergey Zigachev int num_pins; 263b843c749SSergey Zigachev }; 264b843c749SSergey Zigachev 265b843c749SSergey Zigachev struct amdgpu_display_funcs { 266b843c749SSergey Zigachev /* display watermarks */ 267b843c749SSergey Zigachev void (*bandwidth_update)(struct amdgpu_device *adev); 268b843c749SSergey Zigachev /* get frame count */ 269b843c749SSergey Zigachev u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc); 270b843c749SSergey Zigachev /* set backlight level */ 271b843c749SSergey Zigachev void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder, 272b843c749SSergey Zigachev u8 level); 273b843c749SSergey Zigachev /* get backlight level */ 274b843c749SSergey Zigachev u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder); 275b843c749SSergey Zigachev /* hotplug detect */ 276b843c749SSergey Zigachev bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd); 277b843c749SSergey Zigachev void (*hpd_set_polarity)(struct amdgpu_device *adev, 278b843c749SSergey Zigachev enum amdgpu_hpd_id hpd); 279b843c749SSergey Zigachev u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev); 280b843c749SSergey Zigachev /* pageflipping */ 281b843c749SSergey Zigachev void (*page_flip)(struct amdgpu_device *adev, 282b843c749SSergey Zigachev int crtc_id, u64 crtc_base, bool async); 283b843c749SSergey Zigachev int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc, 284b843c749SSergey Zigachev u32 *vbl, u32 *position); 285b843c749SSergey Zigachev /* display topology setup */ 286b843c749SSergey Zigachev void (*add_encoder)(struct amdgpu_device *adev, 287b843c749SSergey Zigachev uint32_t encoder_enum, 288b843c749SSergey Zigachev uint32_t supported_device, 289b843c749SSergey Zigachev u16 caps); 290b843c749SSergey Zigachev void (*add_connector)(struct amdgpu_device *adev, 291b843c749SSergey Zigachev uint32_t connector_id, 292b843c749SSergey Zigachev uint32_t supported_device, 293b843c749SSergey Zigachev int connector_type, 294b843c749SSergey Zigachev struct amdgpu_i2c_bus_rec *i2c_bus, 295b843c749SSergey Zigachev uint16_t connector_object_id, 296b843c749SSergey Zigachev struct amdgpu_hpd *hpd, 297b843c749SSergey Zigachev struct amdgpu_router *router); 298b843c749SSergey Zigachev /* it is used to enter or exit into free sync mode */ 299b843c749SSergey Zigachev int (*notify_freesync)(struct drm_device *dev, void *data, 300b843c749SSergey Zigachev struct drm_file *filp); 301b843c749SSergey Zigachev /* it is used to allow enablement of freesync mode */ 302b843c749SSergey Zigachev int (*set_freesync_property)(struct drm_connector *connector, 303b843c749SSergey Zigachev struct drm_property *property, 304b843c749SSergey Zigachev uint64_t val); 305b843c749SSergey Zigachev 306b843c749SSergey Zigachev 307b843c749SSergey Zigachev }; 308b843c749SSergey Zigachev 309b843c749SSergey Zigachev struct amdgpu_framebuffer { 310b843c749SSergey Zigachev struct drm_framebuffer base; 311b843c749SSergey Zigachev 312b843c749SSergey Zigachev /* caching for later use */ 313b843c749SSergey Zigachev uint64_t address; 314b843c749SSergey Zigachev }; 315b843c749SSergey Zigachev 316b843c749SSergey Zigachev struct amdgpu_fbdev { 317b843c749SSergey Zigachev struct drm_fb_helper helper; 318b843c749SSergey Zigachev struct amdgpu_framebuffer rfb; 319b843c749SSergey Zigachev struct list_head fbdev_list; 320b843c749SSergey Zigachev struct amdgpu_device *adev; 321b843c749SSergey Zigachev }; 322b843c749SSergey Zigachev 323b843c749SSergey Zigachev struct amdgpu_mode_info { 324b843c749SSergey Zigachev struct atom_context *atom_context; 325b843c749SSergey Zigachev struct card_info *atom_card_info; 326b843c749SSergey Zigachev bool mode_config_initialized; 327b843c749SSergey Zigachev struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS]; 328b843c749SSergey Zigachev struct amdgpu_plane *planes[AMDGPU_MAX_PLANES]; 329b843c749SSergey Zigachev struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS]; 330b843c749SSergey Zigachev /* DVI-I properties */ 331b843c749SSergey Zigachev struct drm_property *coherent_mode_property; 332b843c749SSergey Zigachev /* DAC enable load detect */ 333b843c749SSergey Zigachev struct drm_property *load_detect_property; 334b843c749SSergey Zigachev /* underscan */ 335b843c749SSergey Zigachev struct drm_property *underscan_property; 336b843c749SSergey Zigachev struct drm_property *underscan_hborder_property; 337b843c749SSergey Zigachev struct drm_property *underscan_vborder_property; 338b843c749SSergey Zigachev /* audio */ 339b843c749SSergey Zigachev struct drm_property *audio_property; 340b843c749SSergey Zigachev /* FMT dithering */ 341b843c749SSergey Zigachev struct drm_property *dither_property; 342b843c749SSergey Zigachev /* maximum number of bits per channel for monitor color */ 343b843c749SSergey Zigachev struct drm_property *max_bpc_property; 344b843c749SSergey Zigachev /* hardcoded DFP edid from BIOS */ 345b843c749SSergey Zigachev struct edid *bios_hardcoded_edid; 346b843c749SSergey Zigachev int bios_hardcoded_edid_size; 347b843c749SSergey Zigachev 348b843c749SSergey Zigachev /* pointer to fbdev info structure */ 349b843c749SSergey Zigachev struct amdgpu_fbdev *rfbdev; 350b843c749SSergey Zigachev /* firmware flags */ 351b843c749SSergey Zigachev u16 firmware_flags; 352b843c749SSergey Zigachev /* pointer to backlight encoder */ 353b843c749SSergey Zigachev struct amdgpu_encoder *bl_encoder; 354b843c749SSergey Zigachev u8 bl_level; /* saved backlight level */ 355b843c749SSergey Zigachev struct amdgpu_audio audio; /* audio stuff */ 356b843c749SSergey Zigachev int num_crtc; /* number of crtcs */ 357b843c749SSergey Zigachev int num_hpd; /* number of hpd pins */ 358b843c749SSergey Zigachev int num_dig; /* number of dig blocks */ 359b843c749SSergey Zigachev int disp_priority; 360b843c749SSergey Zigachev const struct amdgpu_display_funcs *funcs; 361b843c749SSergey Zigachev const enum drm_plane_type *plane_type; 362b843c749SSergey Zigachev }; 363b843c749SSergey Zigachev 364b843c749SSergey Zigachev #define AMDGPU_MAX_BL_LEVEL 0xFF 365b843c749SSergey Zigachev 366b843c749SSergey Zigachev #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 367b843c749SSergey Zigachev 368b843c749SSergey Zigachev struct amdgpu_backlight_privdata { 369b843c749SSergey Zigachev struct amdgpu_encoder *encoder; 370b843c749SSergey Zigachev uint8_t negative; 371b843c749SSergey Zigachev }; 372b843c749SSergey Zigachev 373b843c749SSergey Zigachev #endif 374b843c749SSergey Zigachev 375b843c749SSergey Zigachev struct amdgpu_atom_ss { 376b843c749SSergey Zigachev uint16_t percentage; 377b843c749SSergey Zigachev uint16_t percentage_divider; 378b843c749SSergey Zigachev uint8_t type; 379b843c749SSergey Zigachev uint16_t step; 380b843c749SSergey Zigachev uint8_t delay; 381b843c749SSergey Zigachev uint8_t range; 382b843c749SSergey Zigachev uint8_t refdiv; 383b843c749SSergey Zigachev /* asic_ss */ 384b843c749SSergey Zigachev uint16_t rate; 385b843c749SSergey Zigachev uint16_t amount; 386b843c749SSergey Zigachev }; 387b843c749SSergey Zigachev 388b843c749SSergey Zigachev struct amdgpu_crtc { 389b843c749SSergey Zigachev struct drm_crtc base; 390b843c749SSergey Zigachev int crtc_id; 391b843c749SSergey Zigachev bool enabled; 392b843c749SSergey Zigachev bool can_tile; 393b843c749SSergey Zigachev uint32_t crtc_offset; 394b843c749SSergey Zigachev struct drm_gem_object *cursor_bo; 395b843c749SSergey Zigachev uint64_t cursor_addr; 396b843c749SSergey Zigachev int cursor_x; 397b843c749SSergey Zigachev int cursor_y; 398b843c749SSergey Zigachev int cursor_hot_x; 399b843c749SSergey Zigachev int cursor_hot_y; 400b843c749SSergey Zigachev int cursor_width; 401b843c749SSergey Zigachev int cursor_height; 402b843c749SSergey Zigachev int max_cursor_width; 403b843c749SSergey Zigachev int max_cursor_height; 404b843c749SSergey Zigachev enum amdgpu_rmx_type rmx_type; 405b843c749SSergey Zigachev u8 h_border; 406b843c749SSergey Zigachev u8 v_border; 407b843c749SSergey Zigachev fixed20_12 vsc; 408b843c749SSergey Zigachev fixed20_12 hsc; 409b843c749SSergey Zigachev struct drm_display_mode native_mode; 410b843c749SSergey Zigachev u32 pll_id; 411b843c749SSergey Zigachev /* page flipping */ 412b843c749SSergey Zigachev struct amdgpu_flip_work *pflip_works; 413b843c749SSergey Zigachev enum amdgpu_flip_status pflip_status; 414b843c749SSergey Zigachev int deferred_flip_completion; 415b843c749SSergey Zigachev /* pll sharing */ 416b843c749SSergey Zigachev struct amdgpu_atom_ss ss; 417b843c749SSergey Zigachev bool ss_enabled; 418b843c749SSergey Zigachev u32 adjusted_clock; 419b843c749SSergey Zigachev int bpc; 420b843c749SSergey Zigachev u32 pll_reference_div; 421b843c749SSergey Zigachev u32 pll_post_div; 422b843c749SSergey Zigachev u32 pll_flags; 423b843c749SSergey Zigachev struct drm_encoder *encoder; 424b843c749SSergey Zigachev struct drm_connector *connector; 425b843c749SSergey Zigachev /* for dpm */ 426b843c749SSergey Zigachev u32 line_time; 427b843c749SSergey Zigachev u32 wm_low; 428b843c749SSergey Zigachev u32 wm_high; 429b843c749SSergey Zigachev u32 lb_vblank_lead_lines; 430b843c749SSergey Zigachev struct drm_display_mode hw_mode; 431b843c749SSergey Zigachev /* for virtual dce */ 432b843c749SSergey Zigachev struct hrtimer vblank_timer; 433b843c749SSergey Zigachev enum amdgpu_interrupt_state vsync_timer_enabled; 434b843c749SSergey Zigachev 435b843c749SSergey Zigachev int otg_inst; 436b843c749SSergey Zigachev struct drm_pending_vblank_event *event; 437b843c749SSergey Zigachev }; 438b843c749SSergey Zigachev 439b843c749SSergey Zigachev struct amdgpu_plane { 440b843c749SSergey Zigachev struct drm_plane base; 441b843c749SSergey Zigachev enum drm_plane_type plane_type; 442b843c749SSergey Zigachev }; 443b843c749SSergey Zigachev 444b843c749SSergey Zigachev struct amdgpu_encoder_atom_dig { 445b843c749SSergey Zigachev bool linkb; 446b843c749SSergey Zigachev /* atom dig */ 447b843c749SSergey Zigachev bool coherent_mode; 448b843c749SSergey Zigachev int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 449b843c749SSergey Zigachev /* atom lvds/edp */ 450b843c749SSergey Zigachev uint32_t lcd_misc; 451b843c749SSergey Zigachev uint16_t panel_pwr_delay; 452b843c749SSergey Zigachev uint32_t lcd_ss_id; 453b843c749SSergey Zigachev /* panel mode */ 454b843c749SSergey Zigachev struct drm_display_mode native_mode; 455b843c749SSergey Zigachev struct backlight_device *bl_dev; 456b843c749SSergey Zigachev int dpms_mode; 457b843c749SSergey Zigachev uint8_t backlight_level; 458b843c749SSergey Zigachev int panel_mode; 459b843c749SSergey Zigachev struct amdgpu_afmt *afmt; 460b843c749SSergey Zigachev }; 461b843c749SSergey Zigachev 462b843c749SSergey Zigachev struct amdgpu_encoder { 463b843c749SSergey Zigachev struct drm_encoder base; 464b843c749SSergey Zigachev uint32_t encoder_enum; 465b843c749SSergey Zigachev uint32_t encoder_id; 466b843c749SSergey Zigachev uint32_t devices; 467b843c749SSergey Zigachev uint32_t active_device; 468b843c749SSergey Zigachev uint32_t flags; 469b843c749SSergey Zigachev uint32_t pixel_clock; 470b843c749SSergey Zigachev enum amdgpu_rmx_type rmx_type; 471b843c749SSergey Zigachev enum amdgpu_underscan_type underscan_type; 472b843c749SSergey Zigachev uint32_t underscan_hborder; 473b843c749SSergey Zigachev uint32_t underscan_vborder; 474b843c749SSergey Zigachev struct drm_display_mode native_mode; 475b843c749SSergey Zigachev void *enc_priv; 476b843c749SSergey Zigachev int audio_polling_active; 477b843c749SSergey Zigachev bool is_ext_encoder; 478b843c749SSergey Zigachev u16 caps; 479b843c749SSergey Zigachev }; 480b843c749SSergey Zigachev 481b843c749SSergey Zigachev struct amdgpu_connector_atom_dig { 482b843c749SSergey Zigachev /* displayport */ 483b843c749SSergey Zigachev u8 dpcd[DP_RECEIVER_CAP_SIZE]; 484b843c749SSergey Zigachev u8 dp_sink_type; 485b843c749SSergey Zigachev int dp_clock; 486b843c749SSergey Zigachev int dp_lane_count; 487b843c749SSergey Zigachev bool edp_on; 488b843c749SSergey Zigachev }; 489b843c749SSergey Zigachev 490b843c749SSergey Zigachev struct amdgpu_gpio_rec { 491b843c749SSergey Zigachev bool valid; 492b843c749SSergey Zigachev u8 id; 493b843c749SSergey Zigachev u32 reg; 494b843c749SSergey Zigachev u32 mask; 495b843c749SSergey Zigachev u32 shift; 496b843c749SSergey Zigachev }; 497b843c749SSergey Zigachev 498b843c749SSergey Zigachev struct amdgpu_hpd { 499b843c749SSergey Zigachev enum amdgpu_hpd_id hpd; 500b843c749SSergey Zigachev u8 plugged_state; 501b843c749SSergey Zigachev struct amdgpu_gpio_rec gpio; 502b843c749SSergey Zigachev }; 503b843c749SSergey Zigachev 504b843c749SSergey Zigachev struct amdgpu_router { 505b843c749SSergey Zigachev u32 router_id; 506b843c749SSergey Zigachev struct amdgpu_i2c_bus_rec i2c_info; 507b843c749SSergey Zigachev u8 i2c_addr; 508b843c749SSergey Zigachev /* i2c mux */ 509b843c749SSergey Zigachev bool ddc_valid; 510b843c749SSergey Zigachev u8 ddc_mux_type; 511b843c749SSergey Zigachev u8 ddc_mux_control_pin; 512b843c749SSergey Zigachev u8 ddc_mux_state; 513b843c749SSergey Zigachev /* clock/data mux */ 514b843c749SSergey Zigachev bool cd_valid; 515b843c749SSergey Zigachev u8 cd_mux_type; 516b843c749SSergey Zigachev u8 cd_mux_control_pin; 517b843c749SSergey Zigachev u8 cd_mux_state; 518b843c749SSergey Zigachev }; 519b843c749SSergey Zigachev 520b843c749SSergey Zigachev enum amdgpu_connector_audio { 521b843c749SSergey Zigachev AMDGPU_AUDIO_DISABLE = 0, 522b843c749SSergey Zigachev AMDGPU_AUDIO_ENABLE = 1, 523b843c749SSergey Zigachev AMDGPU_AUDIO_AUTO = 2 524b843c749SSergey Zigachev }; 525b843c749SSergey Zigachev 526b843c749SSergey Zigachev enum amdgpu_connector_dither { 527b843c749SSergey Zigachev AMDGPU_FMT_DITHER_DISABLE = 0, 528b843c749SSergey Zigachev AMDGPU_FMT_DITHER_ENABLE = 1, 529b843c749SSergey Zigachev }; 530b843c749SSergey Zigachev 531b843c749SSergey Zigachev struct amdgpu_dm_dp_aux { 532b843c749SSergey Zigachev struct drm_dp_aux aux; 533b843c749SSergey Zigachev struct ddc_service *ddc_service; 534b843c749SSergey Zigachev }; 535b843c749SSergey Zigachev 536b843c749SSergey Zigachev struct amdgpu_i2c_adapter { 537b843c749SSergey Zigachev struct i2c_adapter base; 538b843c749SSergey Zigachev 539b843c749SSergey Zigachev struct ddc_service *ddc_service; 540b843c749SSergey Zigachev }; 541b843c749SSergey Zigachev 542b843c749SSergey Zigachev #define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux) 543b843c749SSergey Zigachev 544b843c749SSergey Zigachev struct amdgpu_connector { 545b843c749SSergey Zigachev struct drm_connector base; 546b843c749SSergey Zigachev uint32_t connector_id; 547b843c749SSergey Zigachev uint32_t devices; 548b843c749SSergey Zigachev struct amdgpu_i2c_chan *ddc_bus; 549b843c749SSergey Zigachev /* some systems have an hdmi and vga port with a shared ddc line */ 550b843c749SSergey Zigachev bool shared_ddc; 551b843c749SSergey Zigachev bool use_digital; 552b843c749SSergey Zigachev /* we need to mind the EDID between detect 553b843c749SSergey Zigachev and get modes due to analog/digital/tvencoder */ 554b843c749SSergey Zigachev struct edid *edid; 555b843c749SSergey Zigachev void *con_priv; 556b843c749SSergey Zigachev bool dac_load_detect; 557b843c749SSergey Zigachev bool detected_by_load; /* if the connection status was determined by load */ 558b843c749SSergey Zigachev uint16_t connector_object_id; 559b843c749SSergey Zigachev struct amdgpu_hpd hpd; 560b843c749SSergey Zigachev struct amdgpu_router router; 561b843c749SSergey Zigachev struct amdgpu_i2c_chan *router_bus; 562b843c749SSergey Zigachev enum amdgpu_connector_audio audio; 563b843c749SSergey Zigachev enum amdgpu_connector_dither dither; 564b843c749SSergey Zigachev unsigned pixelclock_for_modeset; 565b843c749SSergey Zigachev }; 566b843c749SSergey Zigachev 567b843c749SSergey Zigachev /* TODO: start to use this struct and remove same field from base one */ 568b843c749SSergey Zigachev struct amdgpu_mst_connector { 569b843c749SSergey Zigachev struct amdgpu_connector base; 570b843c749SSergey Zigachev 571b843c749SSergey Zigachev struct drm_dp_mst_topology_mgr mst_mgr; 572b843c749SSergey Zigachev struct amdgpu_dm_dp_aux dm_dp_aux; 573b843c749SSergey Zigachev struct drm_dp_mst_port *port; 574b843c749SSergey Zigachev struct amdgpu_connector *mst_port; 575b843c749SSergey Zigachev bool is_mst_connector; 576b843c749SSergey Zigachev struct amdgpu_encoder *mst_encoder; 577b843c749SSergey Zigachev }; 578b843c749SSergey Zigachev 579b843c749SSergey Zigachev #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 580b843c749SSergey Zigachev ((em) == ATOM_ENCODER_MODE_DP_MST)) 581b843c749SSergey Zigachev 582b843c749SSergey Zigachev /* Driver internal use only flags of amdgpu_display_get_crtc_scanoutpos() */ 583b843c749SSergey Zigachev #define DRM_SCANOUTPOS_VALID (1 << 0) 584b843c749SSergey Zigachev #define DRM_SCANOUTPOS_IN_VBLANK (1 << 1) 585b843c749SSergey Zigachev #define DRM_SCANOUTPOS_ACCURATE (1 << 2) 586b843c749SSergey Zigachev #define USE_REAL_VBLANKSTART (1 << 30) 587b843c749SSergey Zigachev #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) 588b843c749SSergey Zigachev 589b843c749SSergey Zigachev void amdgpu_link_encoder_connector(struct drm_device *dev); 590b843c749SSergey Zigachev 591b843c749SSergey Zigachev struct drm_connector * 592b843c749SSergey Zigachev amdgpu_get_connector_for_encoder(struct drm_encoder *encoder); 593b843c749SSergey Zigachev struct drm_connector * 594b843c749SSergey Zigachev amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder); 595b843c749SSergey Zigachev bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, 596b843c749SSergey Zigachev u32 pixel_clock); 597b843c749SSergey Zigachev 598b843c749SSergey Zigachev u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 599b843c749SSergey Zigachev struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder); 600b843c749SSergey Zigachev 601b843c749SSergey Zigachev bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, 602b843c749SSergey Zigachev bool use_aux); 603b843c749SSergey Zigachev 604b843c749SSergey Zigachev void amdgpu_encoder_set_active_device(struct drm_encoder *encoder); 605b843c749SSergey Zigachev 606b843c749SSergey Zigachev int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, 607b843c749SSergey Zigachev unsigned int pipe, unsigned int flags, int *vpos, 608b843c749SSergey Zigachev int *hpos, ktime_t *stime, ktime_t *etime, 609b843c749SSergey Zigachev const struct drm_display_mode *mode); 610b843c749SSergey Zigachev 611b843c749SSergey Zigachev int amdgpu_display_framebuffer_init(struct drm_device *dev, 612b843c749SSergey Zigachev struct amdgpu_framebuffer *rfb, 613b843c749SSergey Zigachev const struct drm_mode_fb_cmd2 *mode_cmd, 614b843c749SSergey Zigachev struct drm_gem_object *obj); 615b843c749SSergey Zigachev 616b843c749SSergey Zigachev int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 617b843c749SSergey Zigachev 618b843c749SSergey Zigachev void amdgpu_enc_destroy(struct drm_encoder *encoder); 619b843c749SSergey Zigachev void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 620b843c749SSergey Zigachev bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 621b843c749SSergey Zigachev const struct drm_display_mode *mode, 622b843c749SSergey Zigachev struct drm_display_mode *adjusted_mode); 623b843c749SSergey Zigachev void amdgpu_panel_mode_fixup(struct drm_encoder *encoder, 624b843c749SSergey Zigachev struct drm_display_mode *adjusted_mode); 625b843c749SSergey Zigachev int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc); 626b843c749SSergey Zigachev 627b843c749SSergey Zigachev /* fbdev layer */ 628b843c749SSergey Zigachev int amdgpu_fbdev_init(struct amdgpu_device *adev); 629b843c749SSergey Zigachev void amdgpu_fbdev_fini(struct amdgpu_device *adev); 630b843c749SSergey Zigachev void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state); 631b843c749SSergey Zigachev int amdgpu_fbdev_total_size(struct amdgpu_device *adev); 632b843c749SSergey Zigachev bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj); 633b843c749SSergey Zigachev 634b843c749SSergey Zigachev int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled); 635b843c749SSergey Zigachev 636b843c749SSergey Zigachev /* amdgpu_display.c */ 637b843c749SSergey Zigachev void amdgpu_display_print_display_setup(struct drm_device *dev); 638b843c749SSergey Zigachev int amdgpu_display_modeset_create_props(struct amdgpu_device *adev); 639b843c749SSergey Zigachev int amdgpu_display_crtc_set_config(struct drm_mode_set *set, 640b843c749SSergey Zigachev struct drm_modeset_acquire_ctx *ctx); 641b843c749SSergey Zigachev int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, 642b843c749SSergey Zigachev struct drm_framebuffer *fb, 643b843c749SSergey Zigachev struct drm_pending_vblank_event *event, 644b843c749SSergey Zigachev uint32_t page_flip_flags, uint32_t target, 645b843c749SSergey Zigachev struct drm_modeset_acquire_ctx *ctx); 646b843c749SSergey Zigachev extern const struct drm_mode_config_funcs amdgpu_mode_funcs; 647b843c749SSergey Zigachev 648b843c749SSergey Zigachev #endif 649