1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_RING_H__ 25 #define __AMDGPU_RING_H__ 26 27 #include <drm/amdgpu_drm.h> 28 #include <drm/gpu_scheduler.h> 29 #include <drm/drm_print.h> 30 31 /* max number of rings */ 32 #define AMDGPU_MAX_RINGS 21 33 #define AMDGPU_MAX_GFX_RINGS 1 34 #define AMDGPU_MAX_COMPUTE_RINGS 8 35 #define AMDGPU_MAX_VCE_RINGS 3 36 #define AMDGPU_MAX_UVD_ENC_RINGS 2 37 38 /* some special values for the owner field */ 39 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void *)0ul) 40 #define AMDGPU_FENCE_OWNER_VM ((void *)1ul) 41 #define AMDGPU_FENCE_OWNER_KFD ((void *)2ul) 42 43 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 44 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 45 #define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2) 46 47 #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched) 48 49 enum amdgpu_ring_type { 50 AMDGPU_RING_TYPE_GFX, 51 AMDGPU_RING_TYPE_COMPUTE, 52 AMDGPU_RING_TYPE_SDMA, 53 AMDGPU_RING_TYPE_UVD, 54 AMDGPU_RING_TYPE_VCE, 55 AMDGPU_RING_TYPE_KIQ, 56 AMDGPU_RING_TYPE_UVD_ENC, 57 AMDGPU_RING_TYPE_VCN_DEC, 58 AMDGPU_RING_TYPE_VCN_ENC, 59 AMDGPU_RING_TYPE_VCN_JPEG 60 }; 61 62 struct amdgpu_device; 63 struct amdgpu_ring; 64 struct amdgpu_ib; 65 struct amdgpu_cs_parser; 66 struct amdgpu_job; 67 68 /* 69 * Fences. 70 */ 71 struct amdgpu_fence_driver { 72 uint64_t gpu_addr; 73 volatile uint32_t *cpu_addr; 74 /* sync_seq is protected by ring emission lock */ 75 uint32_t sync_seq; 76 atomic_t last_seq; 77 bool initialized; 78 struct amdgpu_irq_src *irq_src; 79 unsigned irq_type; 80 struct timer_list fallback_timer; 81 unsigned num_fences_mask; 82 spinlock_t lock; 83 struct dma_fence **fences; 84 }; 85 86 int amdgpu_fence_driver_init(struct amdgpu_device *adev); 87 void amdgpu_fence_driver_fini(struct amdgpu_device *adev); 88 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); 89 90 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, 91 unsigned num_hw_submission); 92 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 93 struct amdgpu_irq_src *irq_src, 94 unsigned irq_type); 95 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); 96 void amdgpu_fence_driver_resume(struct amdgpu_device *adev); 97 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence, 98 unsigned flags); 99 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s); 100 void amdgpu_fence_process(struct amdgpu_ring *ring); 101 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 102 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring, 103 uint32_t wait_seq, 104 signed long timeout); 105 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 106 107 /* 108 * Rings. 109 */ 110 111 /* provided by hw blocks that expose a ring buffer for commands */ 112 struct amdgpu_ring_funcs { 113 enum amdgpu_ring_type type; 114 uint32_t align_mask; 115 u32 nop; 116 bool support_64bit_ptrs; 117 unsigned vmhub; 118 unsigned extra_dw; 119 120 /* ring read/write ptr handling */ 121 uint64_t (*get_rptr)(struct amdgpu_ring *ring); 122 uint64_t (*get_wptr)(struct amdgpu_ring *ring); 123 void (*set_wptr)(struct amdgpu_ring *ring); 124 /* validating and patching of IBs */ 125 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 126 int (*patch_cs_in_place)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 127 /* constants to calculate how many DW are needed for an emit */ 128 unsigned emit_frame_size; 129 unsigned emit_ib_size; 130 /* command emit functions */ 131 void (*emit_ib)(struct amdgpu_ring *ring, 132 struct amdgpu_ib *ib, 133 unsigned vmid, bool ctx_switch); 134 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 135 uint64_t seq, unsigned flags); 136 void (*emit_pipeline_sync)(struct amdgpu_ring *ring); 137 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid, 138 uint64_t pd_addr); 139 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 140 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 141 uint32_t gds_base, uint32_t gds_size, 142 uint32_t gws_base, uint32_t gws_size, 143 uint32_t oa_base, uint32_t oa_size); 144 /* testing functions */ 145 int (*test_ring)(struct amdgpu_ring *ring); 146 int (*test_ib)(struct amdgpu_ring *ring, long timeout); 147 /* insert NOP packets */ 148 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 149 void (*insert_start)(struct amdgpu_ring *ring); 150 void (*insert_end)(struct amdgpu_ring *ring); 151 /* pad the indirect buffer to the necessary number of dw */ 152 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 153 unsigned (*init_cond_exec)(struct amdgpu_ring *ring); 154 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset); 155 /* note usage for clock and power gating */ 156 void (*begin_use)(struct amdgpu_ring *ring); 157 void (*end_use)(struct amdgpu_ring *ring); 158 void (*emit_switch_buffer) (struct amdgpu_ring *ring); 159 void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags); 160 void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg); 161 void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); 162 void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg, 163 uint32_t val, uint32_t mask); 164 void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring, 165 uint32_t reg0, uint32_t reg1, 166 uint32_t ref, uint32_t mask); 167 void (*emit_tmz)(struct amdgpu_ring *ring, bool start); 168 /* priority functions */ 169 void (*set_priority) (struct amdgpu_ring *ring, 170 enum drm_sched_priority priority); 171 }; 172 173 struct amdgpu_ring { 174 struct amdgpu_device *adev; 175 const struct amdgpu_ring_funcs *funcs; 176 struct amdgpu_fence_driver fence_drv; 177 struct drm_gpu_scheduler sched; 178 struct list_head lru_list; 179 180 struct amdgpu_bo *ring_obj; 181 volatile uint32_t *ring; 182 unsigned rptr_offs; 183 u64 wptr; 184 u64 wptr_old; 185 unsigned ring_size; 186 unsigned max_dw; 187 int count_dw; 188 uint64_t gpu_addr; 189 uint64_t ptr_mask; 190 uint32_t buf_mask; 191 bool ready; 192 u32 idx; 193 u32 me; 194 u32 pipe; 195 u32 queue; 196 struct amdgpu_bo *mqd_obj; 197 uint64_t mqd_gpu_addr; 198 void *mqd_ptr; 199 uint64_t eop_gpu_addr; 200 u32 doorbell_index; 201 bool use_doorbell; 202 bool use_pollmem; 203 unsigned wptr_offs; 204 unsigned fence_offs; 205 uint64_t current_ctx; 206 char name[16]; 207 unsigned cond_exe_offs; 208 u64 cond_exe_gpu_addr; 209 volatile u32 *cond_exe_cpu_addr; 210 unsigned vm_inv_eng; 211 struct dma_fence *vmid_wait; 212 bool has_compute_vm_bug; 213 214 atomic_t num_jobs[DRM_SCHED_PRIORITY_MAX]; 215 struct lock priority_mutex; 216 /* protected by priority_mutex */ 217 int priority; 218 219 #if defined(CONFIG_DEBUG_FS) 220 struct dentry *ent; 221 #endif 222 }; 223 224 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 225 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 226 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 227 void amdgpu_ring_commit(struct amdgpu_ring *ring); 228 void amdgpu_ring_undo(struct amdgpu_ring *ring); 229 void amdgpu_ring_priority_get(struct amdgpu_ring *ring, 230 enum drm_sched_priority priority); 231 void amdgpu_ring_priority_put(struct amdgpu_ring *ring, 232 enum drm_sched_priority priority); 233 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 234 unsigned ring_size, struct amdgpu_irq_src *irq_src, 235 unsigned irq_type); 236 void amdgpu_ring_fini(struct amdgpu_ring *ring); 237 int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type, 238 int *blacklist, int num_blacklist, 239 bool lru_pipe_order, struct amdgpu_ring **ring); 240 void amdgpu_ring_lru_touch(struct amdgpu_device *adev, struct amdgpu_ring *ring); 241 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring, 242 uint32_t reg0, uint32_t val0, 243 uint32_t reg1, uint32_t val1); 244 245 static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring) 246 { 247 int i = 0; 248 while (i <= ring->buf_mask) 249 ring->ring[i++] = ring->funcs->nop; 250 251 } 252 253 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 254 { 255 if (ring->count_dw <= 0) 256 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 257 ring->ring[ring->wptr++ & ring->buf_mask] = v; 258 ring->wptr &= ring->ptr_mask; 259 ring->count_dw--; 260 } 261 262 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, 263 void *src, int count_dw) 264 { 265 unsigned occupied, chunk1, chunk2; 266 void *dst; 267 268 if (unlikely(ring->count_dw < count_dw)) 269 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 270 271 occupied = ring->wptr & ring->buf_mask; 272 dst = (void *)&ring->ring[occupied]; 273 chunk1 = ring->buf_mask + 1 - occupied; 274 chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1; 275 chunk2 = count_dw - chunk1; 276 chunk1 <<= 2; 277 chunk2 <<= 2; 278 279 if (chunk1) 280 memcpy(dst, src, chunk1); 281 282 if (chunk2) { 283 src += chunk1; 284 dst = (void *)ring->ring; 285 memcpy(dst, src, chunk2); 286 } 287 288 ring->wptr += count_dw; 289 ring->wptr &= ring->ptr_mask; 290 ring->count_dw -= count_dw; 291 } 292 293 #endif 294