1 /* 2 * Copyright 2017 Valve Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Andres Rodriguez <andresx7@gmail.com> 23 */ 24 25 #include <linux/fdtable.h> 26 #include <linux/pid.h> 27 #include <drm/amdgpu_drm.h> 28 #include "amdgpu.h" 29 30 #include "amdgpu_vm.h" 31 32 enum drm_sched_priority amdgpu_to_sched_priority(int amdgpu_priority); 33 enum drm_sched_priority amdgpu_to_sched_priority(int amdgpu_priority) 34 { 35 switch (amdgpu_priority) { 36 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 37 return DRM_SCHED_PRIORITY_HIGH_HW; 38 case AMDGPU_CTX_PRIORITY_HIGH: 39 return DRM_SCHED_PRIORITY_HIGH_SW; 40 case AMDGPU_CTX_PRIORITY_NORMAL: 41 return DRM_SCHED_PRIORITY_NORMAL; 42 case AMDGPU_CTX_PRIORITY_LOW: 43 case AMDGPU_CTX_PRIORITY_VERY_LOW: 44 return DRM_SCHED_PRIORITY_LOW; 45 case AMDGPU_CTX_PRIORITY_UNSET: 46 return DRM_SCHED_PRIORITY_UNSET; 47 default: 48 WARN(1, "Invalid context priority %d\n", amdgpu_priority); 49 return DRM_SCHED_PRIORITY_INVALID; 50 } 51 } 52 53 static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev, 54 int fd, 55 enum drm_sched_priority priority) 56 { 57 STUB(); 58 return -ENOSYS; 59 #if 0 60 struct file *filp = fget(fd); 61 struct drm_file *file; 62 struct amdgpu_fpriv *fpriv; 63 struct amdgpu_ctx *ctx; 64 uint32_t id; 65 66 if (!filp) 67 return -EINVAL; 68 69 file = filp->private_data; 70 fpriv = file->driver_priv; 71 idr_for_each_entry(&fpriv->ctx_mgr.ctx_handles, ctx, id) 72 amdgpu_ctx_priority_override(ctx, priority); 73 74 fput(filp); 75 76 return 0; 77 #endif 78 } 79 80 int amdgpu_sched_ioctl(struct drm_device *dev, void *data, 81 struct drm_file *filp); 82 int amdgpu_sched_ioctl(struct drm_device *dev, void *data, 83 struct drm_file *filp) 84 { 85 union drm_amdgpu_sched *args = data; 86 struct amdgpu_device *adev = dev->dev_private; 87 enum drm_sched_priority priority; 88 int r; 89 90 priority = amdgpu_to_sched_priority(args->in.priority); 91 if (args->in.flags || priority == DRM_SCHED_PRIORITY_INVALID) 92 return -EINVAL; 93 94 switch (args->in.op) { 95 case AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE: 96 r = amdgpu_sched_process_priority_override(adev, 97 args->in.fd, 98 priority); 99 break; 100 default: 101 DRM_ERROR("Invalid sched op specified: %d\n", args->in.op); 102 r = -EINVAL; 103 break; 104 } 105 106 return r; 107 } 108