1*b843c749SSergey Zigachev /*
2*b843c749SSergey Zigachev * Copyright 2007-8 Advanced Micro Devices, Inc.
3*b843c749SSergey Zigachev * Copyright 2008 Red Hat Inc.
4*b843c749SSergey Zigachev *
5*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a
6*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"),
7*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation
8*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the
10*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions:
11*b843c749SSergey Zigachev *
12*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in
13*b843c749SSergey Zigachev * all copies or substantial portions of the Software.
14*b843c749SSergey Zigachev *
15*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE.
22*b843c749SSergey Zigachev *
23*b843c749SSergey Zigachev * Authors: Dave Airlie
24*b843c749SSergey Zigachev * Alex Deucher
25*b843c749SSergey Zigachev * Jerome Glisse
26*b843c749SSergey Zigachev */
27*b843c749SSergey Zigachev #include <drm/drmP.h>
28*b843c749SSergey Zigachev #include <drm/amdgpu_drm.h>
29*b843c749SSergey Zigachev #include "amdgpu.h"
30*b843c749SSergey Zigachev
31*b843c749SSergey Zigachev #include "atom.h"
32*b843c749SSergey Zigachev #include "atom-bits.h"
33*b843c749SSergey Zigachev #include "atombios_encoders.h"
34*b843c749SSergey Zigachev #include "atombios_dp.h"
35*b843c749SSergey Zigachev #include "amdgpu_connectors.h"
36*b843c749SSergey Zigachev #include "amdgpu_atombios.h"
37*b843c749SSergey Zigachev #include <drm/drm_dp_helper.h>
38*b843c749SSergey Zigachev
39*b843c749SSergey Zigachev /* move these to drm_dp_helper.c/h */
40*b843c749SSergey Zigachev #define DP_LINK_CONFIGURATION_SIZE 9
41*b843c749SSergey Zigachev #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
42*b843c749SSergey Zigachev
43*b843c749SSergey Zigachev static char *voltage_names[] = {
44*b843c749SSergey Zigachev "0.4V", "0.6V", "0.8V", "1.2V"
45*b843c749SSergey Zigachev };
46*b843c749SSergey Zigachev static char *pre_emph_names[] = {
47*b843c749SSergey Zigachev "0dB", "3.5dB", "6dB", "9.5dB"
48*b843c749SSergey Zigachev };
49*b843c749SSergey Zigachev
50*b843c749SSergey Zigachev /***** amdgpu AUX functions *****/
51*b843c749SSergey Zigachev
52*b843c749SSergey Zigachev union aux_channel_transaction {
53*b843c749SSergey Zigachev PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
54*b843c749SSergey Zigachev PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
55*b843c749SSergey Zigachev };
56*b843c749SSergey Zigachev
amdgpu_atombios_dp_process_aux_ch(struct amdgpu_i2c_chan * chan,u8 * send,int send_bytes,u8 * recv,int recv_size,u8 delay,u8 * ack)57*b843c749SSergey Zigachev static int amdgpu_atombios_dp_process_aux_ch(struct amdgpu_i2c_chan *chan,
58*b843c749SSergey Zigachev u8 *send, int send_bytes,
59*b843c749SSergey Zigachev u8 *recv, int recv_size,
60*b843c749SSergey Zigachev u8 delay, u8 *ack)
61*b843c749SSergey Zigachev {
62*b843c749SSergey Zigachev struct drm_device *dev = chan->dev;
63*b843c749SSergey Zigachev struct amdgpu_device *adev = dev->dev_private;
64*b843c749SSergey Zigachev union aux_channel_transaction args;
65*b843c749SSergey Zigachev int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
66*b843c749SSergey Zigachev unsigned char *base;
67*b843c749SSergey Zigachev int recv_bytes;
68*b843c749SSergey Zigachev int r = 0;
69*b843c749SSergey Zigachev
70*b843c749SSergey Zigachev memset(&args, 0, sizeof(args));
71*b843c749SSergey Zigachev
72*b843c749SSergey Zigachev mutex_lock(&chan->mutex);
73*b843c749SSergey Zigachev
74*b843c749SSergey Zigachev base = (unsigned char *)(adev->mode_info.atom_context->scratch + 1);
75*b843c749SSergey Zigachev
76*b843c749SSergey Zigachev amdgpu_atombios_copy_swap(base, send, send_bytes, true);
77*b843c749SSergey Zigachev
78*b843c749SSergey Zigachev args.v2.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
79*b843c749SSergey Zigachev args.v2.lpDataOut = cpu_to_le16((u16)(16 + 4));
80*b843c749SSergey Zigachev args.v2.ucDataOutLen = 0;
81*b843c749SSergey Zigachev args.v2.ucChannelID = chan->rec.i2c_id;
82*b843c749SSergey Zigachev args.v2.ucDelay = delay / 10;
83*b843c749SSergey Zigachev args.v2.ucHPD_ID = chan->rec.hpd;
84*b843c749SSergey Zigachev
85*b843c749SSergey Zigachev amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
86*b843c749SSergey Zigachev
87*b843c749SSergey Zigachev *ack = args.v2.ucReplyStatus;
88*b843c749SSergey Zigachev
89*b843c749SSergey Zigachev /* timeout */
90*b843c749SSergey Zigachev if (args.v2.ucReplyStatus == 1) {
91*b843c749SSergey Zigachev r = -ETIMEDOUT;
92*b843c749SSergey Zigachev goto done;
93*b843c749SSergey Zigachev }
94*b843c749SSergey Zigachev
95*b843c749SSergey Zigachev /* flags not zero */
96*b843c749SSergey Zigachev if (args.v2.ucReplyStatus == 2) {
97*b843c749SSergey Zigachev DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
98*b843c749SSergey Zigachev r = -EIO;
99*b843c749SSergey Zigachev goto done;
100*b843c749SSergey Zigachev }
101*b843c749SSergey Zigachev
102*b843c749SSergey Zigachev /* error */
103*b843c749SSergey Zigachev if (args.v2.ucReplyStatus == 3) {
104*b843c749SSergey Zigachev DRM_DEBUG_KMS("dp_aux_ch error\n");
105*b843c749SSergey Zigachev r = -EIO;
106*b843c749SSergey Zigachev goto done;
107*b843c749SSergey Zigachev }
108*b843c749SSergey Zigachev
109*b843c749SSergey Zigachev recv_bytes = args.v1.ucDataOutLen;
110*b843c749SSergey Zigachev if (recv_bytes > recv_size)
111*b843c749SSergey Zigachev recv_bytes = recv_size;
112*b843c749SSergey Zigachev
113*b843c749SSergey Zigachev if (recv && recv_size)
114*b843c749SSergey Zigachev amdgpu_atombios_copy_swap(recv, base + 16, recv_bytes, false);
115*b843c749SSergey Zigachev
116*b843c749SSergey Zigachev r = recv_bytes;
117*b843c749SSergey Zigachev done:
118*b843c749SSergey Zigachev mutex_unlock(&chan->mutex);
119*b843c749SSergey Zigachev
120*b843c749SSergey Zigachev return r;
121*b843c749SSergey Zigachev }
122*b843c749SSergey Zigachev
123*b843c749SSergey Zigachev #define BARE_ADDRESS_SIZE 3
124*b843c749SSergey Zigachev #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
125*b843c749SSergey Zigachev
126*b843c749SSergey Zigachev static ssize_t
amdgpu_atombios_dp_aux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)127*b843c749SSergey Zigachev amdgpu_atombios_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
128*b843c749SSergey Zigachev {
129*b843c749SSergey Zigachev struct amdgpu_i2c_chan *chan =
130*b843c749SSergey Zigachev container_of(aux, struct amdgpu_i2c_chan, aux);
131*b843c749SSergey Zigachev int ret;
132*b843c749SSergey Zigachev u8 tx_buf[20];
133*b843c749SSergey Zigachev size_t tx_size;
134*b843c749SSergey Zigachev u8 ack, delay = 0;
135*b843c749SSergey Zigachev
136*b843c749SSergey Zigachev if (WARN_ON(msg->size > 16))
137*b843c749SSergey Zigachev return -E2BIG;
138*b843c749SSergey Zigachev
139*b843c749SSergey Zigachev tx_buf[0] = msg->address & 0xff;
140*b843c749SSergey Zigachev tx_buf[1] = msg->address >> 8;
141*b843c749SSergey Zigachev tx_buf[2] = (msg->request << 4) |
142*b843c749SSergey Zigachev ((msg->address >> 16) & 0xf);
143*b843c749SSergey Zigachev tx_buf[3] = msg->size ? (msg->size - 1) : 0;
144*b843c749SSergey Zigachev
145*b843c749SSergey Zigachev switch (msg->request & ~DP_AUX_I2C_MOT) {
146*b843c749SSergey Zigachev case DP_AUX_NATIVE_WRITE:
147*b843c749SSergey Zigachev case DP_AUX_I2C_WRITE:
148*b843c749SSergey Zigachev /* tx_size needs to be 4 even for bare address packets since the atom
149*b843c749SSergey Zigachev * table needs the info in tx_buf[3].
150*b843c749SSergey Zigachev */
151*b843c749SSergey Zigachev tx_size = HEADER_SIZE + msg->size;
152*b843c749SSergey Zigachev if (msg->size == 0)
153*b843c749SSergey Zigachev tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
154*b843c749SSergey Zigachev else
155*b843c749SSergey Zigachev tx_buf[3] |= tx_size << 4;
156*b843c749SSergey Zigachev memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
157*b843c749SSergey Zigachev ret = amdgpu_atombios_dp_process_aux_ch(chan,
158*b843c749SSergey Zigachev tx_buf, tx_size, NULL, 0, delay, &ack);
159*b843c749SSergey Zigachev if (ret >= 0)
160*b843c749SSergey Zigachev /* Return payload size. */
161*b843c749SSergey Zigachev ret = msg->size;
162*b843c749SSergey Zigachev break;
163*b843c749SSergey Zigachev case DP_AUX_NATIVE_READ:
164*b843c749SSergey Zigachev case DP_AUX_I2C_READ:
165*b843c749SSergey Zigachev /* tx_size needs to be 4 even for bare address packets since the atom
166*b843c749SSergey Zigachev * table needs the info in tx_buf[3].
167*b843c749SSergey Zigachev */
168*b843c749SSergey Zigachev tx_size = HEADER_SIZE;
169*b843c749SSergey Zigachev if (msg->size == 0)
170*b843c749SSergey Zigachev tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
171*b843c749SSergey Zigachev else
172*b843c749SSergey Zigachev tx_buf[3] |= tx_size << 4;
173*b843c749SSergey Zigachev ret = amdgpu_atombios_dp_process_aux_ch(chan,
174*b843c749SSergey Zigachev tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
175*b843c749SSergey Zigachev break;
176*b843c749SSergey Zigachev default:
177*b843c749SSergey Zigachev ret = -EINVAL;
178*b843c749SSergey Zigachev break;
179*b843c749SSergey Zigachev }
180*b843c749SSergey Zigachev
181*b843c749SSergey Zigachev if (ret >= 0)
182*b843c749SSergey Zigachev msg->reply = ack >> 4;
183*b843c749SSergey Zigachev
184*b843c749SSergey Zigachev return ret;
185*b843c749SSergey Zigachev }
186*b843c749SSergey Zigachev
amdgpu_atombios_dp_aux_init(struct amdgpu_connector * amdgpu_connector)187*b843c749SSergey Zigachev void amdgpu_atombios_dp_aux_init(struct amdgpu_connector *amdgpu_connector)
188*b843c749SSergey Zigachev {
189*b843c749SSergey Zigachev int ret;
190*b843c749SSergey Zigachev
191*b843c749SSergey Zigachev amdgpu_connector->ddc_bus->rec.hpd = amdgpu_connector->hpd.hpd;
192*b843c749SSergey Zigachev amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev;
193*b843c749SSergey Zigachev amdgpu_connector->ddc_bus->aux.transfer = amdgpu_atombios_dp_aux_transfer;
194*b843c749SSergey Zigachev ret = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux);
195*b843c749SSergey Zigachev if (!ret)
196*b843c749SSergey Zigachev amdgpu_connector->ddc_bus->has_aux = true;
197*b843c749SSergey Zigachev
198*b843c749SSergey Zigachev WARN(ret, "drm_dp_aux_register_i2c_bus() failed with error %d\n", ret);
199*b843c749SSergey Zigachev }
200*b843c749SSergey Zigachev
201*b843c749SSergey Zigachev /***** general DP utility functions *****/
202*b843c749SSergey Zigachev
203*b843c749SSergey Zigachev #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3
204*b843c749SSergey Zigachev #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3
205*b843c749SSergey Zigachev
amdgpu_atombios_dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE],int lane_count,u8 train_set[4])206*b843c749SSergey Zigachev static void amdgpu_atombios_dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE],
207*b843c749SSergey Zigachev int lane_count,
208*b843c749SSergey Zigachev u8 train_set[4])
209*b843c749SSergey Zigachev {
210*b843c749SSergey Zigachev u8 v = 0;
211*b843c749SSergey Zigachev u8 p = 0;
212*b843c749SSergey Zigachev int lane;
213*b843c749SSergey Zigachev
214*b843c749SSergey Zigachev for (lane = 0; lane < lane_count; lane++) {
215*b843c749SSergey Zigachev u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
216*b843c749SSergey Zigachev u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
217*b843c749SSergey Zigachev
218*b843c749SSergey Zigachev DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
219*b843c749SSergey Zigachev lane,
220*b843c749SSergey Zigachev voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
221*b843c749SSergey Zigachev pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
222*b843c749SSergey Zigachev
223*b843c749SSergey Zigachev if (this_v > v)
224*b843c749SSergey Zigachev v = this_v;
225*b843c749SSergey Zigachev if (this_p > p)
226*b843c749SSergey Zigachev p = this_p;
227*b843c749SSergey Zigachev }
228*b843c749SSergey Zigachev
229*b843c749SSergey Zigachev if (v >= DP_VOLTAGE_MAX)
230*b843c749SSergey Zigachev v |= DP_TRAIN_MAX_SWING_REACHED;
231*b843c749SSergey Zigachev
232*b843c749SSergey Zigachev if (p >= DP_PRE_EMPHASIS_MAX)
233*b843c749SSergey Zigachev p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
234*b843c749SSergey Zigachev
235*b843c749SSergey Zigachev DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
236*b843c749SSergey Zigachev voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
237*b843c749SSergey Zigachev pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
238*b843c749SSergey Zigachev
239*b843c749SSergey Zigachev for (lane = 0; lane < 4; lane++)
240*b843c749SSergey Zigachev train_set[lane] = v | p;
241*b843c749SSergey Zigachev }
242*b843c749SSergey Zigachev
243*b843c749SSergey Zigachev /* convert bits per color to bits per pixel */
244*b843c749SSergey Zigachev /* get bpc from the EDID */
amdgpu_atombios_dp_convert_bpc_to_bpp(int bpc)245*b843c749SSergey Zigachev static unsigned amdgpu_atombios_dp_convert_bpc_to_bpp(int bpc)
246*b843c749SSergey Zigachev {
247*b843c749SSergey Zigachev if (bpc == 0)
248*b843c749SSergey Zigachev return 24;
249*b843c749SSergey Zigachev else
250*b843c749SSergey Zigachev return bpc * 3;
251*b843c749SSergey Zigachev }
252*b843c749SSergey Zigachev
253*b843c749SSergey Zigachev /***** amdgpu specific DP functions *****/
254*b843c749SSergey Zigachev
amdgpu_atombios_dp_get_dp_link_config(struct drm_connector * connector,const u8 dpcd[DP_DPCD_SIZE],unsigned pix_clock,unsigned * dp_lanes,unsigned * dp_rate)255*b843c749SSergey Zigachev static int amdgpu_atombios_dp_get_dp_link_config(struct drm_connector *connector,
256*b843c749SSergey Zigachev const u8 dpcd[DP_DPCD_SIZE],
257*b843c749SSergey Zigachev unsigned pix_clock,
258*b843c749SSergey Zigachev unsigned *dp_lanes, unsigned *dp_rate)
259*b843c749SSergey Zigachev {
260*b843c749SSergey Zigachev unsigned bpp =
261*b843c749SSergey Zigachev amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector));
262*b843c749SSergey Zigachev static const unsigned link_rates[3] = { 162000, 270000, 540000 };
263*b843c749SSergey Zigachev unsigned max_link_rate = drm_dp_max_link_rate(dpcd);
264*b843c749SSergey Zigachev unsigned max_lane_num = drm_dp_max_lane_count(dpcd);
265*b843c749SSergey Zigachev unsigned lane_num, i, max_pix_clock;
266*b843c749SSergey Zigachev
267*b843c749SSergey Zigachev if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) ==
268*b843c749SSergey Zigachev ENCODER_OBJECT_ID_NUTMEG) {
269*b843c749SSergey Zigachev for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
270*b843c749SSergey Zigachev max_pix_clock = (lane_num * 270000 * 8) / bpp;
271*b843c749SSergey Zigachev if (max_pix_clock >= pix_clock) {
272*b843c749SSergey Zigachev *dp_lanes = lane_num;
273*b843c749SSergey Zigachev *dp_rate = 270000;
274*b843c749SSergey Zigachev return 0;
275*b843c749SSergey Zigachev }
276*b843c749SSergey Zigachev }
277*b843c749SSergey Zigachev } else {
278*b843c749SSergey Zigachev for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
279*b843c749SSergey Zigachev for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
280*b843c749SSergey Zigachev max_pix_clock = (lane_num * link_rates[i] * 8) / bpp;
281*b843c749SSergey Zigachev if (max_pix_clock >= pix_clock) {
282*b843c749SSergey Zigachev *dp_lanes = lane_num;
283*b843c749SSergey Zigachev *dp_rate = link_rates[i];
284*b843c749SSergey Zigachev return 0;
285*b843c749SSergey Zigachev }
286*b843c749SSergey Zigachev }
287*b843c749SSergey Zigachev }
288*b843c749SSergey Zigachev }
289*b843c749SSergey Zigachev
290*b843c749SSergey Zigachev return -EINVAL;
291*b843c749SSergey Zigachev }
292*b843c749SSergey Zigachev
amdgpu_atombios_dp_encoder_service(struct amdgpu_device * adev,int action,int dp_clock,u8 ucconfig,u8 lane_num)293*b843c749SSergey Zigachev static u8 amdgpu_atombios_dp_encoder_service(struct amdgpu_device *adev,
294*b843c749SSergey Zigachev int action, int dp_clock,
295*b843c749SSergey Zigachev u8 ucconfig, u8 lane_num)
296*b843c749SSergey Zigachev {
297*b843c749SSergey Zigachev DP_ENCODER_SERVICE_PARAMETERS args;
298*b843c749SSergey Zigachev int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
299*b843c749SSergey Zigachev
300*b843c749SSergey Zigachev memset(&args, 0, sizeof(args));
301*b843c749SSergey Zigachev args.ucLinkClock = dp_clock / 10;
302*b843c749SSergey Zigachev args.ucConfig = ucconfig;
303*b843c749SSergey Zigachev args.ucAction = action;
304*b843c749SSergey Zigachev args.ucLaneNum = lane_num;
305*b843c749SSergey Zigachev args.ucStatus = 0;
306*b843c749SSergey Zigachev
307*b843c749SSergey Zigachev amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
308*b843c749SSergey Zigachev return args.ucStatus;
309*b843c749SSergey Zigachev }
310*b843c749SSergey Zigachev
amdgpu_atombios_dp_get_sinktype(struct amdgpu_connector * amdgpu_connector)311*b843c749SSergey Zigachev u8 amdgpu_atombios_dp_get_sinktype(struct amdgpu_connector *amdgpu_connector)
312*b843c749SSergey Zigachev {
313*b843c749SSergey Zigachev struct drm_device *dev = amdgpu_connector->base.dev;
314*b843c749SSergey Zigachev struct amdgpu_device *adev = dev->dev_private;
315*b843c749SSergey Zigachev
316*b843c749SSergey Zigachev return amdgpu_atombios_dp_encoder_service(adev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
317*b843c749SSergey Zigachev amdgpu_connector->ddc_bus->rec.i2c_id, 0);
318*b843c749SSergey Zigachev }
319*b843c749SSergey Zigachev
amdgpu_atombios_dp_probe_oui(struct amdgpu_connector * amdgpu_connector)320*b843c749SSergey Zigachev static void amdgpu_atombios_dp_probe_oui(struct amdgpu_connector *amdgpu_connector)
321*b843c749SSergey Zigachev {
322*b843c749SSergey Zigachev struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv;
323*b843c749SSergey Zigachev u8 buf[3];
324*b843c749SSergey Zigachev
325*b843c749SSergey Zigachev if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
326*b843c749SSergey Zigachev return;
327*b843c749SSergey Zigachev
328*b843c749SSergey Zigachev if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
329*b843c749SSergey Zigachev DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
330*b843c749SSergey Zigachev buf[0], buf[1], buf[2]);
331*b843c749SSergey Zigachev
332*b843c749SSergey Zigachev if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
333*b843c749SSergey Zigachev DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
334*b843c749SSergey Zigachev buf[0], buf[1], buf[2]);
335*b843c749SSergey Zigachev }
336*b843c749SSergey Zigachev
amdgpu_atombios_dp_get_dpcd(struct amdgpu_connector * amdgpu_connector)337*b843c749SSergey Zigachev int amdgpu_atombios_dp_get_dpcd(struct amdgpu_connector *amdgpu_connector)
338*b843c749SSergey Zigachev {
339*b843c749SSergey Zigachev struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv;
340*b843c749SSergey Zigachev u8 msg[DP_DPCD_SIZE];
341*b843c749SSergey Zigachev int ret;
342*b843c749SSergey Zigachev
343*b843c749SSergey Zigachev ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_DPCD_REV,
344*b843c749SSergey Zigachev msg, DP_DPCD_SIZE);
345*b843c749SSergey Zigachev if (ret == DP_DPCD_SIZE) {
346*b843c749SSergey Zigachev memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
347*b843c749SSergey Zigachev
348*b843c749SSergey Zigachev DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
349*b843c749SSergey Zigachev dig_connector->dpcd);
350*b843c749SSergey Zigachev
351*b843c749SSergey Zigachev amdgpu_atombios_dp_probe_oui(amdgpu_connector);
352*b843c749SSergey Zigachev
353*b843c749SSergey Zigachev return 0;
354*b843c749SSergey Zigachev }
355*b843c749SSergey Zigachev
356*b843c749SSergey Zigachev dig_connector->dpcd[0] = 0;
357*b843c749SSergey Zigachev return -EINVAL;
358*b843c749SSergey Zigachev }
359*b843c749SSergey Zigachev
amdgpu_atombios_dp_get_panel_mode(struct drm_encoder * encoder,struct drm_connector * connector)360*b843c749SSergey Zigachev int amdgpu_atombios_dp_get_panel_mode(struct drm_encoder *encoder,
361*b843c749SSergey Zigachev struct drm_connector *connector)
362*b843c749SSergey Zigachev {
363*b843c749SSergey Zigachev struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
364*b843c749SSergey Zigachev struct amdgpu_connector_atom_dig *dig_connector;
365*b843c749SSergey Zigachev int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
366*b843c749SSergey Zigachev u16 dp_bridge = amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector);
367*b843c749SSergey Zigachev u8 tmp;
368*b843c749SSergey Zigachev
369*b843c749SSergey Zigachev if (!amdgpu_connector->con_priv)
370*b843c749SSergey Zigachev return panel_mode;
371*b843c749SSergey Zigachev
372*b843c749SSergey Zigachev dig_connector = amdgpu_connector->con_priv;
373*b843c749SSergey Zigachev
374*b843c749SSergey Zigachev if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
375*b843c749SSergey Zigachev /* DP bridge chips */
376*b843c749SSergey Zigachev if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
377*b843c749SSergey Zigachev DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
378*b843c749SSergey Zigachev if (tmp & 1)
379*b843c749SSergey Zigachev panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
380*b843c749SSergey Zigachev else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
381*b843c749SSergey Zigachev (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
382*b843c749SSergey Zigachev panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
383*b843c749SSergey Zigachev else
384*b843c749SSergey Zigachev panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
385*b843c749SSergey Zigachev }
386*b843c749SSergey Zigachev } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
387*b843c749SSergey Zigachev /* eDP */
388*b843c749SSergey Zigachev if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
389*b843c749SSergey Zigachev DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
390*b843c749SSergey Zigachev if (tmp & 1)
391*b843c749SSergey Zigachev panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
392*b843c749SSergey Zigachev }
393*b843c749SSergey Zigachev }
394*b843c749SSergey Zigachev
395*b843c749SSergey Zigachev return panel_mode;
396*b843c749SSergey Zigachev }
397*b843c749SSergey Zigachev
amdgpu_atombios_dp_set_link_config(struct drm_connector * connector,const struct drm_display_mode * mode)398*b843c749SSergey Zigachev void amdgpu_atombios_dp_set_link_config(struct drm_connector *connector,
399*b843c749SSergey Zigachev const struct drm_display_mode *mode)
400*b843c749SSergey Zigachev {
401*b843c749SSergey Zigachev struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
402*b843c749SSergey Zigachev struct amdgpu_connector_atom_dig *dig_connector;
403*b843c749SSergey Zigachev int ret;
404*b843c749SSergey Zigachev
405*b843c749SSergey Zigachev if (!amdgpu_connector->con_priv)
406*b843c749SSergey Zigachev return;
407*b843c749SSergey Zigachev dig_connector = amdgpu_connector->con_priv;
408*b843c749SSergey Zigachev
409*b843c749SSergey Zigachev if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
410*b843c749SSergey Zigachev (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
411*b843c749SSergey Zigachev ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd,
412*b843c749SSergey Zigachev mode->clock,
413*b843c749SSergey Zigachev &dig_connector->dp_lane_count,
414*b843c749SSergey Zigachev &dig_connector->dp_clock);
415*b843c749SSergey Zigachev if (ret) {
416*b843c749SSergey Zigachev dig_connector->dp_clock = 0;
417*b843c749SSergey Zigachev dig_connector->dp_lane_count = 0;
418*b843c749SSergey Zigachev }
419*b843c749SSergey Zigachev }
420*b843c749SSergey Zigachev }
421*b843c749SSergey Zigachev
amdgpu_atombios_dp_mode_valid_helper(struct drm_connector * connector,struct drm_display_mode * mode)422*b843c749SSergey Zigachev int amdgpu_atombios_dp_mode_valid_helper(struct drm_connector *connector,
423*b843c749SSergey Zigachev struct drm_display_mode *mode)
424*b843c749SSergey Zigachev {
425*b843c749SSergey Zigachev struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
426*b843c749SSergey Zigachev struct amdgpu_connector_atom_dig *dig_connector;
427*b843c749SSergey Zigachev unsigned dp_lanes, dp_clock;
428*b843c749SSergey Zigachev int ret;
429*b843c749SSergey Zigachev
430*b843c749SSergey Zigachev if (!amdgpu_connector->con_priv)
431*b843c749SSergey Zigachev return MODE_CLOCK_HIGH;
432*b843c749SSergey Zigachev dig_connector = amdgpu_connector->con_priv;
433*b843c749SSergey Zigachev
434*b843c749SSergey Zigachev ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd,
435*b843c749SSergey Zigachev mode->clock, &dp_lanes, &dp_clock);
436*b843c749SSergey Zigachev if (ret)
437*b843c749SSergey Zigachev return MODE_CLOCK_HIGH;
438*b843c749SSergey Zigachev
439*b843c749SSergey Zigachev if ((dp_clock == 540000) &&
440*b843c749SSergey Zigachev (!amdgpu_connector_is_dp12_capable(connector)))
441*b843c749SSergey Zigachev return MODE_CLOCK_HIGH;
442*b843c749SSergey Zigachev
443*b843c749SSergey Zigachev return MODE_OK;
444*b843c749SSergey Zigachev }
445*b843c749SSergey Zigachev
amdgpu_atombios_dp_needs_link_train(struct amdgpu_connector * amdgpu_connector)446*b843c749SSergey Zigachev bool amdgpu_atombios_dp_needs_link_train(struct amdgpu_connector *amdgpu_connector)
447*b843c749SSergey Zigachev {
448*b843c749SSergey Zigachev u8 link_status[DP_LINK_STATUS_SIZE];
449*b843c749SSergey Zigachev struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
450*b843c749SSergey Zigachev
451*b843c749SSergey Zigachev if (drm_dp_dpcd_read_link_status(&amdgpu_connector->ddc_bus->aux, link_status)
452*b843c749SSergey Zigachev <= 0)
453*b843c749SSergey Zigachev return false;
454*b843c749SSergey Zigachev if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
455*b843c749SSergey Zigachev return false;
456*b843c749SSergey Zigachev return true;
457*b843c749SSergey Zigachev }
458*b843c749SSergey Zigachev
amdgpu_atombios_dp_set_rx_power_state(struct drm_connector * connector,u8 power_state)459*b843c749SSergey Zigachev void amdgpu_atombios_dp_set_rx_power_state(struct drm_connector *connector,
460*b843c749SSergey Zigachev u8 power_state)
461*b843c749SSergey Zigachev {
462*b843c749SSergey Zigachev struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
463*b843c749SSergey Zigachev struct amdgpu_connector_atom_dig *dig_connector;
464*b843c749SSergey Zigachev
465*b843c749SSergey Zigachev if (!amdgpu_connector->con_priv)
466*b843c749SSergey Zigachev return;
467*b843c749SSergey Zigachev
468*b843c749SSergey Zigachev dig_connector = amdgpu_connector->con_priv;
469*b843c749SSergey Zigachev
470*b843c749SSergey Zigachev /* power up/down the sink */
471*b843c749SSergey Zigachev if (dig_connector->dpcd[0] >= 0x11) {
472*b843c749SSergey Zigachev drm_dp_dpcd_writeb(&amdgpu_connector->ddc_bus->aux,
473*b843c749SSergey Zigachev DP_SET_POWER, power_state);
474*b843c749SSergey Zigachev usleep_range(1000, 2000);
475*b843c749SSergey Zigachev }
476*b843c749SSergey Zigachev }
477*b843c749SSergey Zigachev
478*b843c749SSergey Zigachev struct amdgpu_atombios_dp_link_train_info {
479*b843c749SSergey Zigachev struct amdgpu_device *adev;
480*b843c749SSergey Zigachev struct drm_encoder *encoder;
481*b843c749SSergey Zigachev struct drm_connector *connector;
482*b843c749SSergey Zigachev int dp_clock;
483*b843c749SSergey Zigachev int dp_lane_count;
484*b843c749SSergey Zigachev bool tp3_supported;
485*b843c749SSergey Zigachev u8 dpcd[DP_RECEIVER_CAP_SIZE];
486*b843c749SSergey Zigachev u8 train_set[4];
487*b843c749SSergey Zigachev u8 link_status[DP_LINK_STATUS_SIZE];
488*b843c749SSergey Zigachev u8 tries;
489*b843c749SSergey Zigachev struct drm_dp_aux *aux;
490*b843c749SSergey Zigachev };
491*b843c749SSergey Zigachev
492*b843c749SSergey Zigachev static void
amdgpu_atombios_dp_update_vs_emph(struct amdgpu_atombios_dp_link_train_info * dp_info)493*b843c749SSergey Zigachev amdgpu_atombios_dp_update_vs_emph(struct amdgpu_atombios_dp_link_train_info *dp_info)
494*b843c749SSergey Zigachev {
495*b843c749SSergey Zigachev /* set the initial vs/emph on the source */
496*b843c749SSergey Zigachev amdgpu_atombios_encoder_setup_dig_transmitter(dp_info->encoder,
497*b843c749SSergey Zigachev ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
498*b843c749SSergey Zigachev 0, dp_info->train_set[0]); /* sets all lanes at once */
499*b843c749SSergey Zigachev
500*b843c749SSergey Zigachev /* set the vs/emph on the sink */
501*b843c749SSergey Zigachev drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
502*b843c749SSergey Zigachev dp_info->train_set, dp_info->dp_lane_count);
503*b843c749SSergey Zigachev }
504*b843c749SSergey Zigachev
505*b843c749SSergey Zigachev static void
amdgpu_atombios_dp_set_tp(struct amdgpu_atombios_dp_link_train_info * dp_info,int tp)506*b843c749SSergey Zigachev amdgpu_atombios_dp_set_tp(struct amdgpu_atombios_dp_link_train_info *dp_info, int tp)
507*b843c749SSergey Zigachev {
508*b843c749SSergey Zigachev int rtp = 0;
509*b843c749SSergey Zigachev
510*b843c749SSergey Zigachev /* set training pattern on the source */
511*b843c749SSergey Zigachev switch (tp) {
512*b843c749SSergey Zigachev case DP_TRAINING_PATTERN_1:
513*b843c749SSergey Zigachev rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
514*b843c749SSergey Zigachev break;
515*b843c749SSergey Zigachev case DP_TRAINING_PATTERN_2:
516*b843c749SSergey Zigachev rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
517*b843c749SSergey Zigachev break;
518*b843c749SSergey Zigachev case DP_TRAINING_PATTERN_3:
519*b843c749SSergey Zigachev rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
520*b843c749SSergey Zigachev break;
521*b843c749SSergey Zigachev }
522*b843c749SSergey Zigachev amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder, rtp, 0);
523*b843c749SSergey Zigachev
524*b843c749SSergey Zigachev /* enable training pattern on the sink */
525*b843c749SSergey Zigachev drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
526*b843c749SSergey Zigachev }
527*b843c749SSergey Zigachev
528*b843c749SSergey Zigachev static int
amdgpu_atombios_dp_link_train_init(struct amdgpu_atombios_dp_link_train_info * dp_info)529*b843c749SSergey Zigachev amdgpu_atombios_dp_link_train_init(struct amdgpu_atombios_dp_link_train_info *dp_info)
530*b843c749SSergey Zigachev {
531*b843c749SSergey Zigachev struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(dp_info->encoder);
532*b843c749SSergey Zigachev struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
533*b843c749SSergey Zigachev u8 tmp;
534*b843c749SSergey Zigachev
535*b843c749SSergey Zigachev /* power up the sink */
536*b843c749SSergey Zigachev amdgpu_atombios_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
537*b843c749SSergey Zigachev
538*b843c749SSergey Zigachev /* possibly enable downspread on the sink */
539*b843c749SSergey Zigachev if (dp_info->dpcd[3] & 0x1)
540*b843c749SSergey Zigachev drm_dp_dpcd_writeb(dp_info->aux,
541*b843c749SSergey Zigachev DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
542*b843c749SSergey Zigachev else
543*b843c749SSergey Zigachev drm_dp_dpcd_writeb(dp_info->aux,
544*b843c749SSergey Zigachev DP_DOWNSPREAD_CTRL, 0);
545*b843c749SSergey Zigachev
546*b843c749SSergey Zigachev if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)
547*b843c749SSergey Zigachev drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
548*b843c749SSergey Zigachev
549*b843c749SSergey Zigachev /* set the lane count on the sink */
550*b843c749SSergey Zigachev tmp = dp_info->dp_lane_count;
551*b843c749SSergey Zigachev if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
552*b843c749SSergey Zigachev tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
553*b843c749SSergey Zigachev drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
554*b843c749SSergey Zigachev
555*b843c749SSergey Zigachev /* set the link rate on the sink */
556*b843c749SSergey Zigachev tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
557*b843c749SSergey Zigachev drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
558*b843c749SSergey Zigachev
559*b843c749SSergey Zigachev /* start training on the source */
560*b843c749SSergey Zigachev amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder,
561*b843c749SSergey Zigachev ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
562*b843c749SSergey Zigachev
563*b843c749SSergey Zigachev /* disable the training pattern on the sink */
564*b843c749SSergey Zigachev drm_dp_dpcd_writeb(dp_info->aux,
565*b843c749SSergey Zigachev DP_TRAINING_PATTERN_SET,
566*b843c749SSergey Zigachev DP_TRAINING_PATTERN_DISABLE);
567*b843c749SSergey Zigachev
568*b843c749SSergey Zigachev return 0;
569*b843c749SSergey Zigachev }
570*b843c749SSergey Zigachev
571*b843c749SSergey Zigachev static int
amdgpu_atombios_dp_link_train_finish(struct amdgpu_atombios_dp_link_train_info * dp_info)572*b843c749SSergey Zigachev amdgpu_atombios_dp_link_train_finish(struct amdgpu_atombios_dp_link_train_info *dp_info)
573*b843c749SSergey Zigachev {
574*b843c749SSergey Zigachev udelay(400);
575*b843c749SSergey Zigachev
576*b843c749SSergey Zigachev /* disable the training pattern on the sink */
577*b843c749SSergey Zigachev drm_dp_dpcd_writeb(dp_info->aux,
578*b843c749SSergey Zigachev DP_TRAINING_PATTERN_SET,
579*b843c749SSergey Zigachev DP_TRAINING_PATTERN_DISABLE);
580*b843c749SSergey Zigachev
581*b843c749SSergey Zigachev /* disable the training pattern on the source */
582*b843c749SSergey Zigachev amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder,
583*b843c749SSergey Zigachev ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
584*b843c749SSergey Zigachev
585*b843c749SSergey Zigachev return 0;
586*b843c749SSergey Zigachev }
587*b843c749SSergey Zigachev
588*b843c749SSergey Zigachev static int
amdgpu_atombios_dp_link_train_cr(struct amdgpu_atombios_dp_link_train_info * dp_info)589*b843c749SSergey Zigachev amdgpu_atombios_dp_link_train_cr(struct amdgpu_atombios_dp_link_train_info *dp_info)
590*b843c749SSergey Zigachev {
591*b843c749SSergey Zigachev bool clock_recovery;
592*b843c749SSergey Zigachev u8 voltage;
593*b843c749SSergey Zigachev int i;
594*b843c749SSergey Zigachev
595*b843c749SSergey Zigachev amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
596*b843c749SSergey Zigachev memset(dp_info->train_set, 0, 4);
597*b843c749SSergey Zigachev amdgpu_atombios_dp_update_vs_emph(dp_info);
598*b843c749SSergey Zigachev
599*b843c749SSergey Zigachev udelay(400);
600*b843c749SSergey Zigachev
601*b843c749SSergey Zigachev /* clock recovery loop */
602*b843c749SSergey Zigachev clock_recovery = false;
603*b843c749SSergey Zigachev dp_info->tries = 0;
604*b843c749SSergey Zigachev voltage = 0xff;
605*b843c749SSergey Zigachev while (1) {
606*b843c749SSergey Zigachev drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
607*b843c749SSergey Zigachev
608*b843c749SSergey Zigachev if (drm_dp_dpcd_read_link_status(dp_info->aux,
609*b843c749SSergey Zigachev dp_info->link_status) <= 0) {
610*b843c749SSergey Zigachev DRM_ERROR("displayport link status failed\n");
611*b843c749SSergey Zigachev break;
612*b843c749SSergey Zigachev }
613*b843c749SSergey Zigachev
614*b843c749SSergey Zigachev if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
615*b843c749SSergey Zigachev clock_recovery = true;
616*b843c749SSergey Zigachev break;
617*b843c749SSergey Zigachev }
618*b843c749SSergey Zigachev
619*b843c749SSergey Zigachev for (i = 0; i < dp_info->dp_lane_count; i++) {
620*b843c749SSergey Zigachev if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
621*b843c749SSergey Zigachev break;
622*b843c749SSergey Zigachev }
623*b843c749SSergey Zigachev if (i == dp_info->dp_lane_count) {
624*b843c749SSergey Zigachev DRM_ERROR("clock recovery reached max voltage\n");
625*b843c749SSergey Zigachev break;
626*b843c749SSergey Zigachev }
627*b843c749SSergey Zigachev
628*b843c749SSergey Zigachev if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
629*b843c749SSergey Zigachev ++dp_info->tries;
630*b843c749SSergey Zigachev if (dp_info->tries == 5) {
631*b843c749SSergey Zigachev DRM_ERROR("clock recovery tried 5 times\n");
632*b843c749SSergey Zigachev break;
633*b843c749SSergey Zigachev }
634*b843c749SSergey Zigachev } else
635*b843c749SSergey Zigachev dp_info->tries = 0;
636*b843c749SSergey Zigachev
637*b843c749SSergey Zigachev voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
638*b843c749SSergey Zigachev
639*b843c749SSergey Zigachev /* Compute new train_set as requested by sink */
640*b843c749SSergey Zigachev amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count,
641*b843c749SSergey Zigachev dp_info->train_set);
642*b843c749SSergey Zigachev
643*b843c749SSergey Zigachev amdgpu_atombios_dp_update_vs_emph(dp_info);
644*b843c749SSergey Zigachev }
645*b843c749SSergey Zigachev if (!clock_recovery) {
646*b843c749SSergey Zigachev DRM_ERROR("clock recovery failed\n");
647*b843c749SSergey Zigachev return -1;
648*b843c749SSergey Zigachev } else {
649*b843c749SSergey Zigachev DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
650*b843c749SSergey Zigachev dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
651*b843c749SSergey Zigachev (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
652*b843c749SSergey Zigachev DP_TRAIN_PRE_EMPHASIS_SHIFT);
653*b843c749SSergey Zigachev return 0;
654*b843c749SSergey Zigachev }
655*b843c749SSergey Zigachev }
656*b843c749SSergey Zigachev
657*b843c749SSergey Zigachev static int
amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info * dp_info)658*b843c749SSergey Zigachev amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_info)
659*b843c749SSergey Zigachev {
660*b843c749SSergey Zigachev bool channel_eq;
661*b843c749SSergey Zigachev
662*b843c749SSergey Zigachev if (dp_info->tp3_supported)
663*b843c749SSergey Zigachev amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
664*b843c749SSergey Zigachev else
665*b843c749SSergey Zigachev amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
666*b843c749SSergey Zigachev
667*b843c749SSergey Zigachev /* channel equalization loop */
668*b843c749SSergey Zigachev dp_info->tries = 0;
669*b843c749SSergey Zigachev channel_eq = false;
670*b843c749SSergey Zigachev while (1) {
671*b843c749SSergey Zigachev drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
672*b843c749SSergey Zigachev
673*b843c749SSergey Zigachev if (drm_dp_dpcd_read_link_status(dp_info->aux,
674*b843c749SSergey Zigachev dp_info->link_status) <= 0) {
675*b843c749SSergey Zigachev DRM_ERROR("displayport link status failed\n");
676*b843c749SSergey Zigachev break;
677*b843c749SSergey Zigachev }
678*b843c749SSergey Zigachev
679*b843c749SSergey Zigachev if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
680*b843c749SSergey Zigachev channel_eq = true;
681*b843c749SSergey Zigachev break;
682*b843c749SSergey Zigachev }
683*b843c749SSergey Zigachev
684*b843c749SSergey Zigachev /* Try 5 times */
685*b843c749SSergey Zigachev if (dp_info->tries > 5) {
686*b843c749SSergey Zigachev DRM_ERROR("channel eq failed: 5 tries\n");
687*b843c749SSergey Zigachev break;
688*b843c749SSergey Zigachev }
689*b843c749SSergey Zigachev
690*b843c749SSergey Zigachev /* Compute new train_set as requested by sink */
691*b843c749SSergey Zigachev amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count,
692*b843c749SSergey Zigachev dp_info->train_set);
693*b843c749SSergey Zigachev
694*b843c749SSergey Zigachev amdgpu_atombios_dp_update_vs_emph(dp_info);
695*b843c749SSergey Zigachev dp_info->tries++;
696*b843c749SSergey Zigachev }
697*b843c749SSergey Zigachev
698*b843c749SSergey Zigachev if (!channel_eq) {
699*b843c749SSergey Zigachev DRM_ERROR("channel eq failed\n");
700*b843c749SSergey Zigachev return -1;
701*b843c749SSergey Zigachev } else {
702*b843c749SSergey Zigachev DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
703*b843c749SSergey Zigachev dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
704*b843c749SSergey Zigachev (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
705*b843c749SSergey Zigachev >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
706*b843c749SSergey Zigachev return 0;
707*b843c749SSergey Zigachev }
708*b843c749SSergey Zigachev }
709*b843c749SSergey Zigachev
amdgpu_atombios_dp_link_train(struct drm_encoder * encoder,struct drm_connector * connector)710*b843c749SSergey Zigachev void amdgpu_atombios_dp_link_train(struct drm_encoder *encoder,
711*b843c749SSergey Zigachev struct drm_connector *connector)
712*b843c749SSergey Zigachev {
713*b843c749SSergey Zigachev struct drm_device *dev = encoder->dev;
714*b843c749SSergey Zigachev struct amdgpu_device *adev = dev->dev_private;
715*b843c749SSergey Zigachev struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
716*b843c749SSergey Zigachev struct amdgpu_encoder_atom_dig *dig;
717*b843c749SSergey Zigachev struct amdgpu_connector *amdgpu_connector;
718*b843c749SSergey Zigachev struct amdgpu_connector_atom_dig *dig_connector;
719*b843c749SSergey Zigachev struct amdgpu_atombios_dp_link_train_info dp_info;
720*b843c749SSergey Zigachev u8 tmp;
721*b843c749SSergey Zigachev
722*b843c749SSergey Zigachev if (!amdgpu_encoder->enc_priv)
723*b843c749SSergey Zigachev return;
724*b843c749SSergey Zigachev dig = amdgpu_encoder->enc_priv;
725*b843c749SSergey Zigachev
726*b843c749SSergey Zigachev amdgpu_connector = to_amdgpu_connector(connector);
727*b843c749SSergey Zigachev if (!amdgpu_connector->con_priv)
728*b843c749SSergey Zigachev return;
729*b843c749SSergey Zigachev dig_connector = amdgpu_connector->con_priv;
730*b843c749SSergey Zigachev
731*b843c749SSergey Zigachev if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
732*b843c749SSergey Zigachev (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
733*b843c749SSergey Zigachev return;
734*b843c749SSergey Zigachev
735*b843c749SSergey Zigachev if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
736*b843c749SSergey Zigachev == 1) {
737*b843c749SSergey Zigachev if (tmp & DP_TPS3_SUPPORTED)
738*b843c749SSergey Zigachev dp_info.tp3_supported = true;
739*b843c749SSergey Zigachev else
740*b843c749SSergey Zigachev dp_info.tp3_supported = false;
741*b843c749SSergey Zigachev } else {
742*b843c749SSergey Zigachev dp_info.tp3_supported = false;
743*b843c749SSergey Zigachev }
744*b843c749SSergey Zigachev
745*b843c749SSergey Zigachev memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
746*b843c749SSergey Zigachev dp_info.adev = adev;
747*b843c749SSergey Zigachev dp_info.encoder = encoder;
748*b843c749SSergey Zigachev dp_info.connector = connector;
749*b843c749SSergey Zigachev dp_info.dp_lane_count = dig_connector->dp_lane_count;
750*b843c749SSergey Zigachev dp_info.dp_clock = dig_connector->dp_clock;
751*b843c749SSergey Zigachev dp_info.aux = &amdgpu_connector->ddc_bus->aux;
752*b843c749SSergey Zigachev
753*b843c749SSergey Zigachev if (amdgpu_atombios_dp_link_train_init(&dp_info))
754*b843c749SSergey Zigachev goto done;
755*b843c749SSergey Zigachev if (amdgpu_atombios_dp_link_train_cr(&dp_info))
756*b843c749SSergey Zigachev goto done;
757*b843c749SSergey Zigachev if (amdgpu_atombios_dp_link_train_ce(&dp_info))
758*b843c749SSergey Zigachev goto done;
759*b843c749SSergey Zigachev done:
760*b843c749SSergey Zigachev if (amdgpu_atombios_dp_link_train_finish(&dp_info))
761*b843c749SSergey Zigachev return;
762*b843c749SSergey Zigachev }
763