1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2012 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev * Authors: Alex Deucher 23*b843c749SSergey Zigachev */ 24*b843c749SSergey Zigachev #ifndef CIK_H 25*b843c749SSergey Zigachev #define CIK_H 26*b843c749SSergey Zigachev 27*b843c749SSergey Zigachev #define MC_SEQ_MISC0__MT__MASK 0xf0000000 28*b843c749SSergey Zigachev #define MC_SEQ_MISC0__MT__GDDR1 0x10000000 29*b843c749SSergey Zigachev #define MC_SEQ_MISC0__MT__DDR2 0x20000000 30*b843c749SSergey Zigachev #define MC_SEQ_MISC0__MT__GDDR3 0x30000000 31*b843c749SSergey Zigachev #define MC_SEQ_MISC0__MT__GDDR4 0x40000000 32*b843c749SSergey Zigachev #define MC_SEQ_MISC0__MT__GDDR5 0x50000000 33*b843c749SSergey Zigachev #define MC_SEQ_MISC0__MT__HBM 0x60000000 34*b843c749SSergey Zigachev #define MC_SEQ_MISC0__MT__DDR3 0xB0000000 35*b843c749SSergey Zigachev 36*b843c749SSergey Zigachev #define CP_ME_TABLE_SIZE 96 37*b843c749SSergey Zigachev 38*b843c749SSergey Zigachev /* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ 39*b843c749SSergey Zigachev #define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c) 40*b843c749SSergey Zigachev #define CRTC1_REGISTER_OFFSET (0x1e7c - 0x1b7c) 41*b843c749SSergey Zigachev #define CRTC2_REGISTER_OFFSET (0x417c - 0x1b7c) 42*b843c749SSergey Zigachev #define CRTC3_REGISTER_OFFSET (0x447c - 0x1b7c) 43*b843c749SSergey Zigachev #define CRTC4_REGISTER_OFFSET (0x477c - 0x1b7c) 44*b843c749SSergey Zigachev #define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c) 45*b843c749SSergey Zigachev 46*b843c749SSergey Zigachev /* hpd instance offsets */ 47*b843c749SSergey Zigachev #define HPD0_REGISTER_OFFSET (0x1807 - 0x1807) 48*b843c749SSergey Zigachev #define HPD1_REGISTER_OFFSET (0x180a - 0x1807) 49*b843c749SSergey Zigachev #define HPD2_REGISTER_OFFSET (0x180d - 0x1807) 50*b843c749SSergey Zigachev #define HPD3_REGISTER_OFFSET (0x1810 - 0x1807) 51*b843c749SSergey Zigachev #define HPD4_REGISTER_OFFSET (0x1813 - 0x1807) 52*b843c749SSergey Zigachev #define HPD5_REGISTER_OFFSET (0x1816 - 0x1807) 53*b843c749SSergey Zigachev 54*b843c749SSergey Zigachev #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 55*b843c749SSergey Zigachev #define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003 56*b843c749SSergey Zigachev 57*b843c749SSergey Zigachev #define AMDGPU_NUM_OF_VMIDS 8 58*b843c749SSergey Zigachev 59*b843c749SSergey Zigachev #define PIPEID(x) ((x) << 0) 60*b843c749SSergey Zigachev #define MEID(x) ((x) << 2) 61*b843c749SSergey Zigachev #define VMID(x) ((x) << 4) 62*b843c749SSergey Zigachev #define QUEUEID(x) ((x) << 8) 63*b843c749SSergey Zigachev 64*b843c749SSergey Zigachev #define mmCC_DRM_ID_STRAPS 0x1559 65*b843c749SSergey Zigachev #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000 66*b843c749SSergey Zigachev 67*b843c749SSergey Zigachev #define mmCHUB_CONTROL 0x619 68*b843c749SSergey Zigachev #define BYPASS_VM (1 << 0) 69*b843c749SSergey Zigachev 70*b843c749SSergey Zigachev #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 71*b843c749SSergey Zigachev 72*b843c749SSergey Zigachev #define mmGRPH_LUT_10BIT_BYPASS_CONTROL 0x1a02 73*b843c749SSergey Zigachev #define LUT_10BIT_BYPASS_EN (1 << 8) 74*b843c749SSergey Zigachev 75*b843c749SSergey Zigachev # define CURSOR_MONO 0 76*b843c749SSergey Zigachev # define CURSOR_24_1 1 77*b843c749SSergey Zigachev # define CURSOR_24_8_PRE_MULT 2 78*b843c749SSergey Zigachev # define CURSOR_24_8_UNPRE_MULT 3 79*b843c749SSergey Zigachev # define CURSOR_URGENT_ALWAYS 0 80*b843c749SSergey Zigachev # define CURSOR_URGENT_1_8 1 81*b843c749SSergey Zigachev # define CURSOR_URGENT_1_4 2 82*b843c749SSergey Zigachev # define CURSOR_URGENT_3_8 3 83*b843c749SSergey Zigachev # define CURSOR_URGENT_1_2 4 84*b843c749SSergey Zigachev 85*b843c749SSergey Zigachev # define GRPH_DEPTH_8BPP 0 86*b843c749SSergey Zigachev # define GRPH_DEPTH_16BPP 1 87*b843c749SSergey Zigachev # define GRPH_DEPTH_32BPP 2 88*b843c749SSergey Zigachev /* 8 BPP */ 89*b843c749SSergey Zigachev # define GRPH_FORMAT_INDEXED 0 90*b843c749SSergey Zigachev /* 16 BPP */ 91*b843c749SSergey Zigachev # define GRPH_FORMAT_ARGB1555 0 92*b843c749SSergey Zigachev # define GRPH_FORMAT_ARGB565 1 93*b843c749SSergey Zigachev # define GRPH_FORMAT_ARGB4444 2 94*b843c749SSergey Zigachev # define GRPH_FORMAT_AI88 3 95*b843c749SSergey Zigachev # define GRPH_FORMAT_MONO16 4 96*b843c749SSergey Zigachev # define GRPH_FORMAT_BGRA5551 5 97*b843c749SSergey Zigachev /* 32 BPP */ 98*b843c749SSergey Zigachev # define GRPH_FORMAT_ARGB8888 0 99*b843c749SSergey Zigachev # define GRPH_FORMAT_ARGB2101010 1 100*b843c749SSergey Zigachev # define GRPH_FORMAT_32BPP_DIG 2 101*b843c749SSergey Zigachev # define GRPH_FORMAT_8B_ARGB2101010 3 102*b843c749SSergey Zigachev # define GRPH_FORMAT_BGRA1010102 4 103*b843c749SSergey Zigachev # define GRPH_FORMAT_8B_BGRA1010102 5 104*b843c749SSergey Zigachev # define GRPH_FORMAT_RGB111110 6 105*b843c749SSergey Zigachev # define GRPH_FORMAT_BGR101111 7 106*b843c749SSergey Zigachev # define ADDR_SURF_MACRO_TILE_ASPECT_1 0 107*b843c749SSergey Zigachev # define ADDR_SURF_MACRO_TILE_ASPECT_2 1 108*b843c749SSergey Zigachev # define ADDR_SURF_MACRO_TILE_ASPECT_4 2 109*b843c749SSergey Zigachev # define ADDR_SURF_MACRO_TILE_ASPECT_8 3 110*b843c749SSergey Zigachev # define GRPH_ARRAY_LINEAR_GENERAL 0 111*b843c749SSergey Zigachev # define GRPH_ARRAY_LINEAR_ALIGNED 1 112*b843c749SSergey Zigachev # define GRPH_ARRAY_1D_TILED_THIN1 2 113*b843c749SSergey Zigachev # define GRPH_ARRAY_2D_TILED_THIN1 4 114*b843c749SSergey Zigachev # define DISPLAY_MICRO_TILING 0 115*b843c749SSergey Zigachev # define THIN_MICRO_TILING 1 116*b843c749SSergey Zigachev # define DEPTH_MICRO_TILING 2 117*b843c749SSergey Zigachev # define ROTATED_MICRO_TILING 4 118*b843c749SSergey Zigachev # define GRPH_ENDIAN_NONE 0 119*b843c749SSergey Zigachev # define GRPH_ENDIAN_8IN16 1 120*b843c749SSergey Zigachev # define GRPH_ENDIAN_8IN32 2 121*b843c749SSergey Zigachev # define GRPH_ENDIAN_8IN64 3 122*b843c749SSergey Zigachev # define GRPH_RED_SEL_R 0 123*b843c749SSergey Zigachev # define GRPH_RED_SEL_G 1 124*b843c749SSergey Zigachev # define GRPH_RED_SEL_B 2 125*b843c749SSergey Zigachev # define GRPH_RED_SEL_A 3 126*b843c749SSergey Zigachev # define GRPH_GREEN_SEL_G 0 127*b843c749SSergey Zigachev # define GRPH_GREEN_SEL_B 1 128*b843c749SSergey Zigachev # define GRPH_GREEN_SEL_A 2 129*b843c749SSergey Zigachev # define GRPH_GREEN_SEL_R 3 130*b843c749SSergey Zigachev # define GRPH_BLUE_SEL_B 0 131*b843c749SSergey Zigachev # define GRPH_BLUE_SEL_A 1 132*b843c749SSergey Zigachev # define GRPH_BLUE_SEL_R 2 133*b843c749SSergey Zigachev # define GRPH_BLUE_SEL_G 3 134*b843c749SSergey Zigachev # define GRPH_ALPHA_SEL_A 0 135*b843c749SSergey Zigachev # define GRPH_ALPHA_SEL_R 1 136*b843c749SSergey Zigachev # define GRPH_ALPHA_SEL_G 2 137*b843c749SSergey Zigachev # define GRPH_ALPHA_SEL_B 3 138*b843c749SSergey Zigachev # define INPUT_GAMMA_USE_LUT 0 139*b843c749SSergey Zigachev # define INPUT_GAMMA_BYPASS 1 140*b843c749SSergey Zigachev # define INPUT_GAMMA_SRGB_24 2 141*b843c749SSergey Zigachev # define INPUT_GAMMA_XVYCC_222 3 142*b843c749SSergey Zigachev 143*b843c749SSergey Zigachev # define INPUT_CSC_BYPASS 0 144*b843c749SSergey Zigachev # define INPUT_CSC_PROG_COEFF 1 145*b843c749SSergey Zigachev # define INPUT_CSC_PROG_SHARED_MATRIXA 2 146*b843c749SSergey Zigachev 147*b843c749SSergey Zigachev # define OUTPUT_CSC_BYPASS 0 148*b843c749SSergey Zigachev # define OUTPUT_CSC_TV_RGB 1 149*b843c749SSergey Zigachev # define OUTPUT_CSC_YCBCR_601 2 150*b843c749SSergey Zigachev # define OUTPUT_CSC_YCBCR_709 3 151*b843c749SSergey Zigachev # define OUTPUT_CSC_PROG_COEFF 4 152*b843c749SSergey Zigachev # define OUTPUT_CSC_PROG_SHARED_MATRIXB 5 153*b843c749SSergey Zigachev 154*b843c749SSergey Zigachev # define DEGAMMA_BYPASS 0 155*b843c749SSergey Zigachev # define DEGAMMA_SRGB_24 1 156*b843c749SSergey Zigachev # define DEGAMMA_XVYCC_222 2 157*b843c749SSergey Zigachev # define GAMUT_REMAP_BYPASS 0 158*b843c749SSergey Zigachev # define GAMUT_REMAP_PROG_COEFF 1 159*b843c749SSergey Zigachev # define GAMUT_REMAP_PROG_SHARED_MATRIXA 2 160*b843c749SSergey Zigachev # define GAMUT_REMAP_PROG_SHARED_MATRIXB 3 161*b843c749SSergey Zigachev 162*b843c749SSergey Zigachev # define REGAMMA_BYPASS 0 163*b843c749SSergey Zigachev # define REGAMMA_SRGB_24 1 164*b843c749SSergey Zigachev # define REGAMMA_XVYCC_222 2 165*b843c749SSergey Zigachev # define REGAMMA_PROG_A 3 166*b843c749SSergey Zigachev # define REGAMMA_PROG_B 4 167*b843c749SSergey Zigachev 168*b843c749SSergey Zigachev # define FMT_CLAMP_6BPC 0 169*b843c749SSergey Zigachev # define FMT_CLAMP_8BPC 1 170*b843c749SSergey Zigachev # define FMT_CLAMP_10BPC 2 171*b843c749SSergey Zigachev 172*b843c749SSergey Zigachev # define HDMI_24BIT_DEEP_COLOR 0 173*b843c749SSergey Zigachev # define HDMI_30BIT_DEEP_COLOR 1 174*b843c749SSergey Zigachev # define HDMI_36BIT_DEEP_COLOR 2 175*b843c749SSergey Zigachev # define HDMI_ACR_HW 0 176*b843c749SSergey Zigachev # define HDMI_ACR_32 1 177*b843c749SSergey Zigachev # define HDMI_ACR_44 2 178*b843c749SSergey Zigachev # define HDMI_ACR_48 3 179*b843c749SSergey Zigachev # define HDMI_ACR_X1 1 180*b843c749SSergey Zigachev # define HDMI_ACR_X2 2 181*b843c749SSergey Zigachev # define HDMI_ACR_X4 4 182*b843c749SSergey Zigachev # define AFMT_AVI_INFO_Y_RGB 0 183*b843c749SSergey Zigachev # define AFMT_AVI_INFO_Y_YCBCR422 1 184*b843c749SSergey Zigachev # define AFMT_AVI_INFO_Y_YCBCR444 2 185*b843c749SSergey Zigachev 186*b843c749SSergey Zigachev #define NO_AUTO 0 187*b843c749SSergey Zigachev #define ES_AUTO 1 188*b843c749SSergey Zigachev #define GS_AUTO 2 189*b843c749SSergey Zigachev #define ES_AND_GS_AUTO 3 190*b843c749SSergey Zigachev 191*b843c749SSergey Zigachev # define ARRAY_MODE(x) ((x) << 2) 192*b843c749SSergey Zigachev # define PIPE_CONFIG(x) ((x) << 6) 193*b843c749SSergey Zigachev # define TILE_SPLIT(x) ((x) << 11) 194*b843c749SSergey Zigachev # define MICRO_TILE_MODE_NEW(x) ((x) << 22) 195*b843c749SSergey Zigachev # define SAMPLE_SPLIT(x) ((x) << 25) 196*b843c749SSergey Zigachev # define BANK_WIDTH(x) ((x) << 0) 197*b843c749SSergey Zigachev # define BANK_HEIGHT(x) ((x) << 2) 198*b843c749SSergey Zigachev # define MACRO_TILE_ASPECT(x) ((x) << 4) 199*b843c749SSergey Zigachev # define NUM_BANKS(x) ((x) << 6) 200*b843c749SSergey Zigachev 201*b843c749SSergey Zigachev #define MSG_ENTER_RLC_SAFE_MODE 1 202*b843c749SSergey Zigachev #define MSG_EXIT_RLC_SAFE_MODE 0 203*b843c749SSergey Zigachev 204*b843c749SSergey Zigachev /* 205*b843c749SSergey Zigachev * PM4 206*b843c749SSergey Zigachev */ 207*b843c749SSergey Zigachev #define PACKET_TYPE0 0 208*b843c749SSergey Zigachev #define PACKET_TYPE1 1 209*b843c749SSergey Zigachev #define PACKET_TYPE2 2 210*b843c749SSergey Zigachev #define PACKET_TYPE3 3 211*b843c749SSergey Zigachev 212*b843c749SSergey Zigachev #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 213*b843c749SSergey Zigachev #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 214*b843c749SSergey Zigachev #define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) 215*b843c749SSergey Zigachev #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 216*b843c749SSergey Zigachev #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 217*b843c749SSergey Zigachev ((reg) & 0xFFFF) | \ 218*b843c749SSergey Zigachev ((n) & 0x3FFF) << 16) 219*b843c749SSergey Zigachev #define CP_PACKET2 0x80000000 220*b843c749SSergey Zigachev #define PACKET2_PAD_SHIFT 0 221*b843c749SSergey Zigachev #define PACKET2_PAD_MASK (0x3fffffff << 0) 222*b843c749SSergey Zigachev 223*b843c749SSergey Zigachev #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 224*b843c749SSergey Zigachev 225*b843c749SSergey Zigachev #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 226*b843c749SSergey Zigachev (((op) & 0xFF) << 8) | \ 227*b843c749SSergey Zigachev ((n) & 0x3FFF) << 16) 228*b843c749SSergey Zigachev 229*b843c749SSergey Zigachev #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 230*b843c749SSergey Zigachev 231*b843c749SSergey Zigachev /* Packet 3 types */ 232*b843c749SSergey Zigachev #define PACKET3_NOP 0x10 233*b843c749SSergey Zigachev #define PACKET3_SET_BASE 0x11 234*b843c749SSergey Zigachev #define PACKET3_BASE_INDEX(x) ((x) << 0) 235*b843c749SSergey Zigachev #define CE_PARTITION_BASE 3 236*b843c749SSergey Zigachev #define PACKET3_CLEAR_STATE 0x12 237*b843c749SSergey Zigachev #define PACKET3_INDEX_BUFFER_SIZE 0x13 238*b843c749SSergey Zigachev #define PACKET3_DISPATCH_DIRECT 0x15 239*b843c749SSergey Zigachev #define PACKET3_DISPATCH_INDIRECT 0x16 240*b843c749SSergey Zigachev #define PACKET3_ATOMIC_GDS 0x1D 241*b843c749SSergey Zigachev #define PACKET3_ATOMIC_MEM 0x1E 242*b843c749SSergey Zigachev #define PACKET3_OCCLUSION_QUERY 0x1F 243*b843c749SSergey Zigachev #define PACKET3_SET_PREDICATION 0x20 244*b843c749SSergey Zigachev #define PACKET3_REG_RMW 0x21 245*b843c749SSergey Zigachev #define PACKET3_COND_EXEC 0x22 246*b843c749SSergey Zigachev #define PACKET3_PRED_EXEC 0x23 247*b843c749SSergey Zigachev #define PACKET3_DRAW_INDIRECT 0x24 248*b843c749SSergey Zigachev #define PACKET3_DRAW_INDEX_INDIRECT 0x25 249*b843c749SSergey Zigachev #define PACKET3_INDEX_BASE 0x26 250*b843c749SSergey Zigachev #define PACKET3_DRAW_INDEX_2 0x27 251*b843c749SSergey Zigachev #define PACKET3_CONTEXT_CONTROL 0x28 252*b843c749SSergey Zigachev #define PACKET3_INDEX_TYPE 0x2A 253*b843c749SSergey Zigachev #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 254*b843c749SSergey Zigachev #define PACKET3_DRAW_INDEX_AUTO 0x2D 255*b843c749SSergey Zigachev #define PACKET3_NUM_INSTANCES 0x2F 256*b843c749SSergey Zigachev #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 257*b843c749SSergey Zigachev #define PACKET3_INDIRECT_BUFFER_CONST 0x33 258*b843c749SSergey Zigachev #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 259*b843c749SSergey Zigachev #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 260*b843c749SSergey Zigachev #define PACKET3_DRAW_PREAMBLE 0x36 261*b843c749SSergey Zigachev #define PACKET3_WRITE_DATA 0x37 262*b843c749SSergey Zigachev #define WRITE_DATA_DST_SEL(x) ((x) << 8) 263*b843c749SSergey Zigachev /* 0 - register 264*b843c749SSergey Zigachev * 1 - memory (sync - via GRBM) 265*b843c749SSergey Zigachev * 2 - gl2 266*b843c749SSergey Zigachev * 3 - gds 267*b843c749SSergey Zigachev * 4 - reserved 268*b843c749SSergey Zigachev * 5 - memory (async - direct) 269*b843c749SSergey Zigachev */ 270*b843c749SSergey Zigachev #define WR_ONE_ADDR (1 << 16) 271*b843c749SSergey Zigachev #define WR_CONFIRM (1 << 20) 272*b843c749SSergey Zigachev #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 273*b843c749SSergey Zigachev /* 0 - LRU 274*b843c749SSergey Zigachev * 1 - Stream 275*b843c749SSergey Zigachev */ 276*b843c749SSergey Zigachev #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 277*b843c749SSergey Zigachev /* 0 - me 278*b843c749SSergey Zigachev * 1 - pfp 279*b843c749SSergey Zigachev * 2 - ce 280*b843c749SSergey Zigachev */ 281*b843c749SSergey Zigachev #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 282*b843c749SSergey Zigachev #define PACKET3_MEM_SEMAPHORE 0x39 283*b843c749SSergey Zigachev # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 284*b843c749SSergey Zigachev # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 285*b843c749SSergey Zigachev # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ 286*b843c749SSergey Zigachev # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 287*b843c749SSergey Zigachev # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 288*b843c749SSergey Zigachev #define PACKET3_COPY_DW 0x3B 289*b843c749SSergey Zigachev #define PACKET3_WAIT_REG_MEM 0x3C 290*b843c749SSergey Zigachev #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 291*b843c749SSergey Zigachev /* 0 - always 292*b843c749SSergey Zigachev * 1 - < 293*b843c749SSergey Zigachev * 2 - <= 294*b843c749SSergey Zigachev * 3 - == 295*b843c749SSergey Zigachev * 4 - != 296*b843c749SSergey Zigachev * 5 - >= 297*b843c749SSergey Zigachev * 6 - > 298*b843c749SSergey Zigachev */ 299*b843c749SSergey Zigachev #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 300*b843c749SSergey Zigachev /* 0 - reg 301*b843c749SSergey Zigachev * 1 - mem 302*b843c749SSergey Zigachev */ 303*b843c749SSergey Zigachev #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 304*b843c749SSergey Zigachev /* 0 - wait_reg_mem 305*b843c749SSergey Zigachev * 1 - wr_wait_wr_reg 306*b843c749SSergey Zigachev */ 307*b843c749SSergey Zigachev #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 308*b843c749SSergey Zigachev /* 0 - me 309*b843c749SSergey Zigachev * 1 - pfp 310*b843c749SSergey Zigachev */ 311*b843c749SSergey Zigachev #define PACKET3_INDIRECT_BUFFER 0x3F 312*b843c749SSergey Zigachev #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) 313*b843c749SSergey Zigachev #define INDIRECT_BUFFER_VALID (1 << 23) 314*b843c749SSergey Zigachev #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 315*b843c749SSergey Zigachev /* 0 - LRU 316*b843c749SSergey Zigachev * 1 - Stream 317*b843c749SSergey Zigachev * 2 - Bypass 318*b843c749SSergey Zigachev */ 319*b843c749SSergey Zigachev #define PACKET3_COPY_DATA 0x40 320*b843c749SSergey Zigachev #define PACKET3_PFP_SYNC_ME 0x42 321*b843c749SSergey Zigachev #define PACKET3_SURFACE_SYNC 0x43 322*b843c749SSergey Zigachev # define PACKET3_DEST_BASE_0_ENA (1 << 0) 323*b843c749SSergey Zigachev # define PACKET3_DEST_BASE_1_ENA (1 << 1) 324*b843c749SSergey Zigachev # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 325*b843c749SSergey Zigachev # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 326*b843c749SSergey Zigachev # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 327*b843c749SSergey Zigachev # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 328*b843c749SSergey Zigachev # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 329*b843c749SSergey Zigachev # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 330*b843c749SSergey Zigachev # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 331*b843c749SSergey Zigachev # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 332*b843c749SSergey Zigachev # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 333*b843c749SSergey Zigachev # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) 334*b843c749SSergey Zigachev # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ 335*b843c749SSergey Zigachev # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ 336*b843c749SSergey Zigachev # define PACKET3_DEST_BASE_2_ENA (1 << 19) 337*b843c749SSergey Zigachev # define PACKET3_DEST_BASE_3_ENA (1 << 21) 338*b843c749SSergey Zigachev # define PACKET3_TCL1_ACTION_ENA (1 << 22) 339*b843c749SSergey Zigachev # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ 340*b843c749SSergey Zigachev # define PACKET3_CB_ACTION_ENA (1 << 25) 341*b843c749SSergey Zigachev # define PACKET3_DB_ACTION_ENA (1 << 26) 342*b843c749SSergey Zigachev # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 343*b843c749SSergey Zigachev # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) 344*b843c749SSergey Zigachev # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 345*b843c749SSergey Zigachev #define PACKET3_COND_WRITE 0x45 346*b843c749SSergey Zigachev #define PACKET3_EVENT_WRITE 0x46 347*b843c749SSergey Zigachev #define EVENT_TYPE(x) ((x) << 0) 348*b843c749SSergey Zigachev #define EVENT_INDEX(x) ((x) << 8) 349*b843c749SSergey Zigachev /* 0 - any non-TS event 350*b843c749SSergey Zigachev * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 351*b843c749SSergey Zigachev * 2 - SAMPLE_PIPELINESTAT 352*b843c749SSergey Zigachev * 3 - SAMPLE_STREAMOUTSTAT* 353*b843c749SSergey Zigachev * 4 - *S_PARTIAL_FLUSH 354*b843c749SSergey Zigachev * 5 - EOP events 355*b843c749SSergey Zigachev * 6 - EOS events 356*b843c749SSergey Zigachev */ 357*b843c749SSergey Zigachev #define PACKET3_EVENT_WRITE_EOP 0x47 358*b843c749SSergey Zigachev #define EOP_TCL1_VOL_ACTION_EN (1 << 12) 359*b843c749SSergey Zigachev #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ 360*b843c749SSergey Zigachev #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ 361*b843c749SSergey Zigachev #define EOP_TCL1_ACTION_EN (1 << 16) 362*b843c749SSergey Zigachev #define EOP_TC_ACTION_EN (1 << 17) /* L2 */ 363*b843c749SSergey Zigachev #define EOP_TCL2_VOLATILE (1 << 24) 364*b843c749SSergey Zigachev #define EOP_CACHE_POLICY(x) ((x) << 25) 365*b843c749SSergey Zigachev /* 0 - LRU 366*b843c749SSergey Zigachev * 1 - Stream 367*b843c749SSergey Zigachev * 2 - Bypass 368*b843c749SSergey Zigachev */ 369*b843c749SSergey Zigachev #define DATA_SEL(x) ((x) << 29) 370*b843c749SSergey Zigachev /* 0 - discard 371*b843c749SSergey Zigachev * 1 - send low 32bit data 372*b843c749SSergey Zigachev * 2 - send 64bit data 373*b843c749SSergey Zigachev * 3 - send 64bit GPU counter value 374*b843c749SSergey Zigachev * 4 - send 64bit sys counter value 375*b843c749SSergey Zigachev */ 376*b843c749SSergey Zigachev #define INT_SEL(x) ((x) << 24) 377*b843c749SSergey Zigachev /* 0 - none 378*b843c749SSergey Zigachev * 1 - interrupt only (DATA_SEL = 0) 379*b843c749SSergey Zigachev * 2 - interrupt when data write is confirmed 380*b843c749SSergey Zigachev */ 381*b843c749SSergey Zigachev #define DST_SEL(x) ((x) << 16) 382*b843c749SSergey Zigachev /* 0 - MC 383*b843c749SSergey Zigachev * 1 - TC/L2 384*b843c749SSergey Zigachev */ 385*b843c749SSergey Zigachev #define PACKET3_EVENT_WRITE_EOS 0x48 386*b843c749SSergey Zigachev #define PACKET3_RELEASE_MEM 0x49 387*b843c749SSergey Zigachev #define PACKET3_PREAMBLE_CNTL 0x4A 388*b843c749SSergey Zigachev # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 389*b843c749SSergey Zigachev # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 390*b843c749SSergey Zigachev #define PACKET3_DMA_DATA 0x50 391*b843c749SSergey Zigachev /* 1. header 392*b843c749SSergey Zigachev * 2. CONTROL 393*b843c749SSergey Zigachev * 3. SRC_ADDR_LO or DATA [31:0] 394*b843c749SSergey Zigachev * 4. SRC_ADDR_HI [31:0] 395*b843c749SSergey Zigachev * 5. DST_ADDR_LO [31:0] 396*b843c749SSergey Zigachev * 6. DST_ADDR_HI [7:0] 397*b843c749SSergey Zigachev * 7. COMMAND [30:21] | BYTE_COUNT [20:0] 398*b843c749SSergey Zigachev */ 399*b843c749SSergey Zigachev /* CONTROL */ 400*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) 401*b843c749SSergey Zigachev /* 0 - ME 402*b843c749SSergey Zigachev * 1 - PFP 403*b843c749SSergey Zigachev */ 404*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) 405*b843c749SSergey Zigachev /* 0 - LRU 406*b843c749SSergey Zigachev * 1 - Stream 407*b843c749SSergey Zigachev * 2 - Bypass 408*b843c749SSergey Zigachev */ 409*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15) 410*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 411*b843c749SSergey Zigachev /* 0 - DST_ADDR using DAS 412*b843c749SSergey Zigachev * 1 - GDS 413*b843c749SSergey Zigachev * 3 - DST_ADDR using L2 414*b843c749SSergey Zigachev */ 415*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) 416*b843c749SSergey Zigachev /* 0 - LRU 417*b843c749SSergey Zigachev * 1 - Stream 418*b843c749SSergey Zigachev * 2 - Bypass 419*b843c749SSergey Zigachev */ 420*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27) 421*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 422*b843c749SSergey Zigachev /* 0 - SRC_ADDR using SAS 423*b843c749SSergey Zigachev * 1 - GDS 424*b843c749SSergey Zigachev * 2 - DATA 425*b843c749SSergey Zigachev * 3 - SRC_ADDR using L2 426*b843c749SSergey Zigachev */ 427*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_CP_SYNC (1 << 31) 428*b843c749SSergey Zigachev /* COMMAND */ 429*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_DIS_WC (1 << 21) 430*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22) 431*b843c749SSergey Zigachev /* 0 - none 432*b843c749SSergey Zigachev * 1 - 8 in 16 433*b843c749SSergey Zigachev * 2 - 8 in 32 434*b843c749SSergey Zigachev * 3 - 8 in 64 435*b843c749SSergey Zigachev */ 436*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24) 437*b843c749SSergey Zigachev /* 0 - none 438*b843c749SSergey Zigachev * 1 - 8 in 16 439*b843c749SSergey Zigachev * 2 - 8 in 32 440*b843c749SSergey Zigachev * 3 - 8 in 64 441*b843c749SSergey Zigachev */ 442*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_CMD_SAS (1 << 26) 443*b843c749SSergey Zigachev /* 0 - memory 444*b843c749SSergey Zigachev * 1 - register 445*b843c749SSergey Zigachev */ 446*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_CMD_DAS (1 << 27) 447*b843c749SSergey Zigachev /* 0 - memory 448*b843c749SSergey Zigachev * 1 - register 449*b843c749SSergey Zigachev */ 450*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 451*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 452*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 453*b843c749SSergey Zigachev #define PACKET3_AQUIRE_MEM 0x58 454*b843c749SSergey Zigachev #define PACKET3_REWIND 0x59 455*b843c749SSergey Zigachev #define PACKET3_LOAD_UCONFIG_REG 0x5E 456*b843c749SSergey Zigachev #define PACKET3_LOAD_SH_REG 0x5F 457*b843c749SSergey Zigachev #define PACKET3_LOAD_CONFIG_REG 0x60 458*b843c749SSergey Zigachev #define PACKET3_LOAD_CONTEXT_REG 0x61 459*b843c749SSergey Zigachev #define PACKET3_SET_CONFIG_REG 0x68 460*b843c749SSergey Zigachev #define PACKET3_SET_CONFIG_REG_START 0x00002000 461*b843c749SSergey Zigachev #define PACKET3_SET_CONFIG_REG_END 0x00002c00 462*b843c749SSergey Zigachev #define PACKET3_SET_CONTEXT_REG 0x69 463*b843c749SSergey Zigachev #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 464*b843c749SSergey Zigachev #define PACKET3_SET_CONTEXT_REG_END 0x0000a400 465*b843c749SSergey Zigachev #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 466*b843c749SSergey Zigachev #define PACKET3_SET_SH_REG 0x76 467*b843c749SSergey Zigachev #define PACKET3_SET_SH_REG_START 0x00002c00 468*b843c749SSergey Zigachev #define PACKET3_SET_SH_REG_END 0x00003000 469*b843c749SSergey Zigachev #define PACKET3_SET_SH_REG_OFFSET 0x77 470*b843c749SSergey Zigachev #define PACKET3_SET_QUEUE_REG 0x78 471*b843c749SSergey Zigachev #define PACKET3_SET_UCONFIG_REG 0x79 472*b843c749SSergey Zigachev #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 473*b843c749SSergey Zigachev #define PACKET3_SET_UCONFIG_REG_END 0x0000c400 474*b843c749SSergey Zigachev #define PACKET3_SCRATCH_RAM_WRITE 0x7D 475*b843c749SSergey Zigachev #define PACKET3_SCRATCH_RAM_READ 0x7E 476*b843c749SSergey Zigachev #define PACKET3_LOAD_CONST_RAM 0x80 477*b843c749SSergey Zigachev #define PACKET3_WRITE_CONST_RAM 0x81 478*b843c749SSergey Zigachev #define PACKET3_DUMP_CONST_RAM 0x83 479*b843c749SSergey Zigachev #define PACKET3_INCREMENT_CE_COUNTER 0x84 480*b843c749SSergey Zigachev #define PACKET3_INCREMENT_DE_COUNTER 0x85 481*b843c749SSergey Zigachev #define PACKET3_WAIT_ON_CE_COUNTER 0x86 482*b843c749SSergey Zigachev #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 483*b843c749SSergey Zigachev #define PACKET3_SWITCH_BUFFER 0x8B 484*b843c749SSergey Zigachev 485*b843c749SSergey Zigachev /* SDMA - first instance at 0xd000, second at 0xd800 */ 486*b843c749SSergey Zigachev #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ 487*b843c749SSergey Zigachev #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ 488*b843c749SSergey Zigachev #define SDMA_MAX_INSTANCE 2 489*b843c749SSergey Zigachev 490*b843c749SSergey Zigachev #define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \ 491*b843c749SSergey Zigachev (((sub_op) & 0xFF) << 8) | \ 492*b843c749SSergey Zigachev (((op) & 0xFF) << 0)) 493*b843c749SSergey Zigachev /* sDMA opcodes */ 494*b843c749SSergey Zigachev #define SDMA_OPCODE_NOP 0 495*b843c749SSergey Zigachev # define SDMA_NOP_COUNT(x) (((x) & 0x3FFF) << 16) 496*b843c749SSergey Zigachev #define SDMA_OPCODE_COPY 1 497*b843c749SSergey Zigachev # define SDMA_COPY_SUB_OPCODE_LINEAR 0 498*b843c749SSergey Zigachev # define SDMA_COPY_SUB_OPCODE_TILED 1 499*b843c749SSergey Zigachev # define SDMA_COPY_SUB_OPCODE_SOA 3 500*b843c749SSergey Zigachev # define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4 501*b843c749SSergey Zigachev # define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5 502*b843c749SSergey Zigachev # define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6 503*b843c749SSergey Zigachev #define SDMA_OPCODE_WRITE 2 504*b843c749SSergey Zigachev # define SDMA_WRITE_SUB_OPCODE_LINEAR 0 505*b843c749SSergey Zigachev # define SDMA_WRITE_SUB_OPCODE_TILED 1 506*b843c749SSergey Zigachev #define SDMA_OPCODE_INDIRECT_BUFFER 4 507*b843c749SSergey Zigachev #define SDMA_OPCODE_FENCE 5 508*b843c749SSergey Zigachev #define SDMA_OPCODE_TRAP 6 509*b843c749SSergey Zigachev #define SDMA_OPCODE_SEMAPHORE 7 510*b843c749SSergey Zigachev # define SDMA_SEMAPHORE_EXTRA_O (1 << 13) 511*b843c749SSergey Zigachev /* 0 - increment 512*b843c749SSergey Zigachev * 1 - write 1 513*b843c749SSergey Zigachev */ 514*b843c749SSergey Zigachev # define SDMA_SEMAPHORE_EXTRA_S (1 << 14) 515*b843c749SSergey Zigachev /* 0 - wait 516*b843c749SSergey Zigachev * 1 - signal 517*b843c749SSergey Zigachev */ 518*b843c749SSergey Zigachev # define SDMA_SEMAPHORE_EXTRA_M (1 << 15) 519*b843c749SSergey Zigachev /* mailbox */ 520*b843c749SSergey Zigachev #define SDMA_OPCODE_POLL_REG_MEM 8 521*b843c749SSergey Zigachev # define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10) 522*b843c749SSergey Zigachev /* 0 - wait_reg_mem 523*b843c749SSergey Zigachev * 1 - wr_wait_wr_reg 524*b843c749SSergey Zigachev */ 525*b843c749SSergey Zigachev # define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12) 526*b843c749SSergey Zigachev /* 0 - always 527*b843c749SSergey Zigachev * 1 - < 528*b843c749SSergey Zigachev * 2 - <= 529*b843c749SSergey Zigachev * 3 - == 530*b843c749SSergey Zigachev * 4 - != 531*b843c749SSergey Zigachev * 5 - >= 532*b843c749SSergey Zigachev * 6 - > 533*b843c749SSergey Zigachev */ 534*b843c749SSergey Zigachev # define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15) 535*b843c749SSergey Zigachev /* 0 = register 536*b843c749SSergey Zigachev * 1 = memory 537*b843c749SSergey Zigachev */ 538*b843c749SSergey Zigachev #define SDMA_OPCODE_COND_EXEC 9 539*b843c749SSergey Zigachev #define SDMA_OPCODE_CONSTANT_FILL 11 540*b843c749SSergey Zigachev # define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14) 541*b843c749SSergey Zigachev /* 0 = byte fill 542*b843c749SSergey Zigachev * 2 = DW fill 543*b843c749SSergey Zigachev */ 544*b843c749SSergey Zigachev #define SDMA_OPCODE_GENERATE_PTE_PDE 12 545*b843c749SSergey Zigachev #define SDMA_OPCODE_TIMESTAMP 13 546*b843c749SSergey Zigachev # define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0 547*b843c749SSergey Zigachev # define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1 548*b843c749SSergey Zigachev # define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2 549*b843c749SSergey Zigachev #define SDMA_OPCODE_SRBM_WRITE 14 550*b843c749SSergey Zigachev # define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12) 551*b843c749SSergey Zigachev /* byte mask */ 552*b843c749SSergey Zigachev 553*b843c749SSergey Zigachev #define VCE_CMD_NO_OP 0x00000000 554*b843c749SSergey Zigachev #define VCE_CMD_END 0x00000001 555*b843c749SSergey Zigachev #define VCE_CMD_IB 0x00000002 556*b843c749SSergey Zigachev #define VCE_CMD_FENCE 0x00000003 557*b843c749SSergey Zigachev #define VCE_CMD_TRAP 0x00000004 558*b843c749SSergey Zigachev #define VCE_CMD_IB_AUTO 0x00000005 559*b843c749SSergey Zigachev #define VCE_CMD_SEMAPHORE 0x00000006 560*b843c749SSergey Zigachev 561*b843c749SSergey Zigachev /* if PTR32, these are the bases for scratch and lds */ 562*b843c749SSergey Zigachev #define PRIVATE_BASE(x) ((x) << 0) /* scratch */ 563*b843c749SSergey Zigachev #define SHARED_BASE(x) ((x) << 16) /* LDS */ 564*b843c749SSergey Zigachev 565*b843c749SSergey Zigachev #define KFD_CIK_SDMA_QUEUE_OFFSET (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL) 566*b843c749SSergey Zigachev 567*b843c749SSergey Zigachev /* valid for both DEFAULT_MTYPE and APE1_MTYPE */ 568*b843c749SSergey Zigachev enum { 569*b843c749SSergey Zigachev MTYPE_CACHED = 0, 570*b843c749SSergey Zigachev MTYPE_NONCACHED = 3 571*b843c749SSergey Zigachev }; 572*b843c749SSergey Zigachev 573*b843c749SSergey Zigachev /* mmPA_SC_RASTER_CONFIG mask */ 574*b843c749SSergey Zigachev #define RB_MAP_PKR0(x) ((x) << 0) 575*b843c749SSergey Zigachev #define RB_MAP_PKR0_MASK (0x3 << 0) 576*b843c749SSergey Zigachev #define RB_MAP_PKR1(x) ((x) << 2) 577*b843c749SSergey Zigachev #define RB_MAP_PKR1_MASK (0x3 << 2) 578*b843c749SSergey Zigachev #define RB_XSEL2(x) ((x) << 4) 579*b843c749SSergey Zigachev #define RB_XSEL2_MASK (0x3 << 4) 580*b843c749SSergey Zigachev #define RB_XSEL (1 << 6) 581*b843c749SSergey Zigachev #define RB_YSEL (1 << 7) 582*b843c749SSergey Zigachev #define PKR_MAP(x) ((x) << 8) 583*b843c749SSergey Zigachev #define PKR_MAP_MASK (0x3 << 8) 584*b843c749SSergey Zigachev #define PKR_XSEL(x) ((x) << 10) 585*b843c749SSergey Zigachev #define PKR_XSEL_MASK (0x3 << 10) 586*b843c749SSergey Zigachev #define PKR_YSEL(x) ((x) << 12) 587*b843c749SSergey Zigachev #define PKR_YSEL_MASK (0x3 << 12) 588*b843c749SSergey Zigachev #define SC_MAP(x) ((x) << 16) 589*b843c749SSergey Zigachev #define SC_MAP_MASK (0x3 << 16) 590*b843c749SSergey Zigachev #define SC_XSEL(x) ((x) << 18) 591*b843c749SSergey Zigachev #define SC_XSEL_MASK (0x3 << 18) 592*b843c749SSergey Zigachev #define SC_YSEL(x) ((x) << 20) 593*b843c749SSergey Zigachev #define SC_YSEL_MASK (0x3 << 20) 594*b843c749SSergey Zigachev #define SE_MAP(x) ((x) << 24) 595*b843c749SSergey Zigachev #define SE_MAP_MASK (0x3 << 24) 596*b843c749SSergey Zigachev #define SE_XSEL(x) ((x) << 26) 597*b843c749SSergey Zigachev #define SE_XSEL_MASK (0x3 << 26) 598*b843c749SSergey Zigachev #define SE_YSEL(x) ((x) << 28) 599*b843c749SSergey Zigachev #define SE_YSEL_MASK (0x3 << 28) 600*b843c749SSergey Zigachev 601*b843c749SSergey Zigachev /* mmPA_SC_RASTER_CONFIG_1 mask */ 602*b843c749SSergey Zigachev #define SE_PAIR_MAP(x) ((x) << 0) 603*b843c749SSergey Zigachev #define SE_PAIR_MAP_MASK (0x3 << 0) 604*b843c749SSergey Zigachev #define SE_PAIR_XSEL(x) ((x) << 2) 605*b843c749SSergey Zigachev #define SE_PAIR_XSEL_MASK (0x3 << 2) 606*b843c749SSergey Zigachev #define SE_PAIR_YSEL(x) ((x) << 4) 607*b843c749SSergey Zigachev #define SE_PAIR_YSEL_MASK (0x3 << 4) 608*b843c749SSergey Zigachev 609*b843c749SSergey Zigachev #endif 610