1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drmP.h> 24 #include "amdgpu.h" 25 #include "amdgpu_pm.h" 26 #include "amdgpu_i2c.h" 27 #include "vid.h" 28 #include "atom.h" 29 #include "amdgpu_atombios.h" 30 #include "atombios_crtc.h" 31 #include "atombios_encoders.h" 32 #include "amdgpu_pll.h" 33 #include "amdgpu_connectors.h" 34 #include "dce_v11_0.h" 35 36 #include "dce/dce_11_0_d.h" 37 #include "dce/dce_11_0_sh_mask.h" 38 #include "dce/dce_11_0_enum.h" 39 #include "oss/oss_3_0_d.h" 40 #include "oss/oss_3_0_sh_mask.h" 41 #include "gmc/gmc_8_1_d.h" 42 #include "gmc/gmc_8_1_sh_mask.h" 43 44 #include "ivsrcid/ivsrcid_vislands30.h" 45 46 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev); 47 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev); 48 49 static const u32 crtc_offsets[] = 50 { 51 CRTC0_REGISTER_OFFSET, 52 CRTC1_REGISTER_OFFSET, 53 CRTC2_REGISTER_OFFSET, 54 CRTC3_REGISTER_OFFSET, 55 CRTC4_REGISTER_OFFSET, 56 CRTC5_REGISTER_OFFSET, 57 CRTC6_REGISTER_OFFSET 58 }; 59 60 static const u32 hpd_offsets[] = 61 { 62 HPD0_REGISTER_OFFSET, 63 HPD1_REGISTER_OFFSET, 64 HPD2_REGISTER_OFFSET, 65 HPD3_REGISTER_OFFSET, 66 HPD4_REGISTER_OFFSET, 67 HPD5_REGISTER_OFFSET 68 }; 69 70 static const uint32_t dig_offsets[] = { 71 DIG0_REGISTER_OFFSET, 72 DIG1_REGISTER_OFFSET, 73 DIG2_REGISTER_OFFSET, 74 DIG3_REGISTER_OFFSET, 75 DIG4_REGISTER_OFFSET, 76 DIG5_REGISTER_OFFSET, 77 DIG6_REGISTER_OFFSET, 78 DIG7_REGISTER_OFFSET, 79 DIG8_REGISTER_OFFSET 80 }; 81 82 static const struct { 83 uint32_t reg; 84 uint32_t vblank; 85 uint32_t vline; 86 uint32_t hpd; 87 88 } interrupt_status_offsets[] = { { 89 .reg = mmDISP_INTERRUPT_STATUS, 90 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 91 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 92 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 93 }, { 94 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 95 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 96 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 97 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 98 }, { 99 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 100 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 101 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 102 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 103 }, { 104 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 105 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 106 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 107 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 108 }, { 109 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 110 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 111 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 112 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 113 }, { 114 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 115 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 116 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 117 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 118 } }; 119 120 static const u32 cz_golden_settings_a11[] = 121 { 122 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, 123 mmFBC_MISC, 0x1f311fff, 0x14300000, 124 }; 125 126 static const u32 cz_mgcg_cgcg_init[] = 127 { 128 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 129 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 130 }; 131 132 static const u32 stoney_golden_settings_a11[] = 133 { 134 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, 135 mmFBC_MISC, 0x1f311fff, 0x14302000, 136 }; 137 138 static const u32 polaris11_golden_settings_a11[] = 139 { 140 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 141 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 142 mmFBC_DEBUG1, 0xffffffff, 0x00000008, 143 mmFBC_MISC, 0x9f313fff, 0x14302008, 144 mmHDMI_CONTROL, 0x313f031f, 0x00000011, 145 }; 146 147 static const u32 polaris10_golden_settings_a11[] = 148 { 149 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 150 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 151 mmFBC_MISC, 0x9f313fff, 0x14302008, 152 mmHDMI_CONTROL, 0x313f031f, 0x00000011, 153 }; 154 155 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) 156 { 157 switch (adev->asic_type) { 158 case CHIP_CARRIZO: 159 amdgpu_device_program_register_sequence(adev, 160 cz_mgcg_cgcg_init, 161 ARRAY_SIZE(cz_mgcg_cgcg_init)); 162 amdgpu_device_program_register_sequence(adev, 163 cz_golden_settings_a11, 164 ARRAY_SIZE(cz_golden_settings_a11)); 165 break; 166 case CHIP_STONEY: 167 amdgpu_device_program_register_sequence(adev, 168 stoney_golden_settings_a11, 169 ARRAY_SIZE(stoney_golden_settings_a11)); 170 break; 171 case CHIP_POLARIS11: 172 case CHIP_POLARIS12: 173 amdgpu_device_program_register_sequence(adev, 174 polaris11_golden_settings_a11, 175 ARRAY_SIZE(polaris11_golden_settings_a11)); 176 break; 177 case CHIP_POLARIS10: 178 case CHIP_VEGAM: 179 amdgpu_device_program_register_sequence(adev, 180 polaris10_golden_settings_a11, 181 ARRAY_SIZE(polaris10_golden_settings_a11)); 182 break; 183 default: 184 break; 185 } 186 } 187 188 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev, 189 u32 block_offset, u32 reg) 190 { 191 unsigned long flags; 192 u32 r; 193 194 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 195 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 196 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 197 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 198 199 return r; 200 } 201 202 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev, 203 u32 block_offset, u32 reg, u32 v) 204 { 205 unsigned long flags; 206 207 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 208 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 209 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 210 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 211 } 212 213 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 214 { 215 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 216 return 0; 217 else 218 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 219 } 220 221 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev) 222 { 223 unsigned i; 224 225 /* Enable pflip interrupts */ 226 for (i = 0; i < adev->mode_info.num_crtc; i++) 227 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 228 } 229 230 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 231 { 232 unsigned i; 233 234 /* Disable pflip interrupts */ 235 for (i = 0; i < adev->mode_info.num_crtc; i++) 236 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 237 } 238 239 /** 240 * dce_v11_0_page_flip - pageflip callback. 241 * 242 * @adev: amdgpu_device pointer 243 * @crtc_id: crtc to cleanup pageflip on 244 * @crtc_base: new address of the crtc (GPU MC address) 245 * 246 * Triggers the actual pageflip by updating the primary 247 * surface base address. 248 */ 249 static void dce_v11_0_page_flip(struct amdgpu_device *adev, 250 int crtc_id, u64 crtc_base, bool async) 251 { 252 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 253 u32 tmp; 254 255 /* flip immediate for async, default is vsync */ 256 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 257 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 258 GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0); 259 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 260 /* update the scanout addresses */ 261 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 262 upper_32_bits(crtc_base)); 263 /* writing to the low address triggers the update */ 264 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 265 lower_32_bits(crtc_base)); 266 /* post the write */ 267 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 268 } 269 270 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 271 u32 *vbl, u32 *position) 272 { 273 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 274 return -EINVAL; 275 276 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 277 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 278 279 return 0; 280 } 281 282 /** 283 * dce_v11_0_hpd_sense - hpd sense callback. 284 * 285 * @adev: amdgpu_device pointer 286 * @hpd: hpd (hotplug detect) pin 287 * 288 * Checks if a digital monitor is connected (evergreen+). 289 * Returns true if connected, false if not connected. 290 */ 291 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev, 292 enum amdgpu_hpd_id hpd) 293 { 294 bool connected = false; 295 296 if (hpd >= adev->mode_info.num_hpd) 297 return connected; 298 299 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) & 300 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK) 301 connected = true; 302 303 return connected; 304 } 305 306 /** 307 * dce_v11_0_hpd_set_polarity - hpd set polarity callback. 308 * 309 * @adev: amdgpu_device pointer 310 * @hpd: hpd (hotplug detect) pin 311 * 312 * Set the polarity of the hpd pin (evergreen+). 313 */ 314 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev, 315 enum amdgpu_hpd_id hpd) 316 { 317 u32 tmp; 318 bool connected = dce_v11_0_hpd_sense(adev, hpd); 319 320 if (hpd >= adev->mode_info.num_hpd) 321 return; 322 323 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 324 if (connected) 325 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); 326 else 327 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); 328 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 329 } 330 331 /** 332 * dce_v11_0_hpd_init - hpd setup callback. 333 * 334 * @adev: amdgpu_device pointer 335 * 336 * Setup the hpd pins used by the card (evergreen+). 337 * Enable the pin, set the polarity, and enable the hpd interrupts. 338 */ 339 static void dce_v11_0_hpd_init(struct amdgpu_device *adev) 340 { 341 struct drm_device *dev = adev->ddev; 342 struct drm_connector *connector; 343 u32 tmp; 344 345 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 346 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 347 348 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 349 continue; 350 351 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 352 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 353 /* don't try to enable hpd on eDP or LVDS avoid breaking the 354 * aux dp channel on imac and help (but not completely fix) 355 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 356 * also avoid interrupt storms during dpms. 357 */ 358 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 359 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 360 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 361 continue; 362 } 363 364 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 365 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); 366 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 367 368 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]); 369 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 370 DC_HPD_CONNECT_INT_DELAY, 371 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS); 372 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 373 DC_HPD_DISCONNECT_INT_DELAY, 374 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); 375 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 376 377 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 378 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 379 } 380 } 381 382 /** 383 * dce_v11_0_hpd_fini - hpd tear down callback. 384 * 385 * @adev: amdgpu_device pointer 386 * 387 * Tear down the hpd pins used by the card (evergreen+). 388 * Disable the hpd interrupts. 389 */ 390 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev) 391 { 392 struct drm_device *dev = adev->ddev; 393 struct drm_connector *connector; 394 u32 tmp; 395 396 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 397 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 398 399 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 400 continue; 401 402 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 403 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); 404 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 405 406 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 407 } 408 } 409 410 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 411 { 412 return mmDC_GPIO_HPD_A; 413 } 414 415 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev) 416 { 417 u32 crtc_hung = 0; 418 u32 crtc_status[6]; 419 u32 i, j, tmp; 420 421 for (i = 0; i < adev->mode_info.num_crtc; i++) { 422 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 423 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { 424 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 425 crtc_hung |= (1 << i); 426 } 427 } 428 429 for (j = 0; j < 10; j++) { 430 for (i = 0; i < adev->mode_info.num_crtc; i++) { 431 if (crtc_hung & (1 << i)) { 432 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 433 if (tmp != crtc_status[i]) 434 crtc_hung &= ~(1 << i); 435 } 436 } 437 if (crtc_hung == 0) 438 return false; 439 udelay(100); 440 } 441 442 return true; 443 } 444 445 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev, 446 bool render) 447 { 448 u32 tmp; 449 450 /* Lockout access through VGA aperture*/ 451 tmp = RREG32(mmVGA_HDP_CONTROL); 452 if (render) 453 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); 454 else 455 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 456 WREG32(mmVGA_HDP_CONTROL, tmp); 457 458 /* disable VGA render */ 459 tmp = RREG32(mmVGA_RENDER_CONTROL); 460 if (render) 461 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); 462 else 463 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 464 WREG32(mmVGA_RENDER_CONTROL, tmp); 465 } 466 467 static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev) 468 { 469 int num_crtc = 0; 470 471 switch (adev->asic_type) { 472 case CHIP_CARRIZO: 473 num_crtc = 3; 474 break; 475 case CHIP_STONEY: 476 num_crtc = 2; 477 break; 478 case CHIP_POLARIS10: 479 case CHIP_VEGAM: 480 num_crtc = 6; 481 break; 482 case CHIP_POLARIS11: 483 case CHIP_POLARIS12: 484 num_crtc = 5; 485 break; 486 default: 487 num_crtc = 0; 488 } 489 return num_crtc; 490 } 491 492 void dce_v11_0_disable_dce(struct amdgpu_device *adev) 493 { 494 /*Disable VGA render and enabled crtc, if has DCE engine*/ 495 if (amdgpu_atombios_has_dce_engine_info(adev)) { 496 u32 tmp; 497 int crtc_enabled, i; 498 499 dce_v11_0_set_vga_render_state(adev, false); 500 501 /*Disable crtc*/ 502 for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) { 503 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), 504 CRTC_CONTROL, CRTC_MASTER_EN); 505 if (crtc_enabled) { 506 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 507 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 508 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); 509 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 510 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 511 } 512 } 513 } 514 } 515 516 static void dce_v11_0_program_fmt(struct drm_encoder *encoder) 517 { 518 struct drm_device *dev = encoder->dev; 519 struct amdgpu_device *adev = dev->dev_private; 520 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 521 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 522 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 523 int bpc = 0; 524 u32 tmp = 0; 525 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 526 527 if (connector) { 528 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 529 bpc = amdgpu_connector_get_monitor_bpc(connector); 530 dither = amdgpu_connector->dither; 531 } 532 533 /* LVDS/eDP FMT is set up by atom */ 534 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 535 return; 536 537 /* not needed for analog */ 538 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 539 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 540 return; 541 542 if (bpc == 0) 543 return; 544 545 switch (bpc) { 546 case 6: 547 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 548 /* XXX sort out optimal dither settings */ 549 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 550 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 551 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 552 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); 553 } else { 554 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 555 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); 556 } 557 break; 558 case 8: 559 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 560 /* XXX sort out optimal dither settings */ 561 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 562 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 563 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 564 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 565 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); 566 } else { 567 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 568 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); 569 } 570 break; 571 case 10: 572 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 573 /* XXX sort out optimal dither settings */ 574 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 575 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 576 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 577 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 578 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); 579 } else { 580 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 581 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); 582 } 583 break; 584 default: 585 /* not needed */ 586 break; 587 } 588 589 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 590 } 591 592 593 /* display watermark setup */ 594 /** 595 * dce_v11_0_line_buffer_adjust - Set up the line buffer 596 * 597 * @adev: amdgpu_device pointer 598 * @amdgpu_crtc: the selected display controller 599 * @mode: the current display mode on the selected display 600 * controller 601 * 602 * Setup up the line buffer allocation for 603 * the selected display controller (CIK). 604 * Returns the line buffer size in pixels. 605 */ 606 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev, 607 struct amdgpu_crtc *amdgpu_crtc, 608 struct drm_display_mode *mode) 609 { 610 u32 tmp, buffer_alloc, i, mem_cfg; 611 u32 pipe_offset = amdgpu_crtc->crtc_id; 612 /* 613 * Line Buffer Setup 614 * There are 6 line buffers, one for each display controllers. 615 * There are 3 partitions per LB. Select the number of partitions 616 * to enable based on the display width. For display widths larger 617 * than 4096, you need use to use 2 display controllers and combine 618 * them using the stereo blender. 619 */ 620 if (amdgpu_crtc->base.enabled && mode) { 621 if (mode->crtc_hdisplay < 1920) { 622 mem_cfg = 1; 623 buffer_alloc = 2; 624 } else if (mode->crtc_hdisplay < 2560) { 625 mem_cfg = 2; 626 buffer_alloc = 2; 627 } else if (mode->crtc_hdisplay < 4096) { 628 mem_cfg = 0; 629 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 630 } else { 631 DRM_DEBUG_KMS("Mode too big for LB!\n"); 632 mem_cfg = 0; 633 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 634 } 635 } else { 636 mem_cfg = 1; 637 buffer_alloc = 0; 638 } 639 640 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); 641 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); 642 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); 643 644 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 645 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); 646 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); 647 648 for (i = 0; i < adev->usec_timeout; i++) { 649 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 650 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) 651 break; 652 udelay(1); 653 } 654 655 if (amdgpu_crtc->base.enabled && mode) { 656 switch (mem_cfg) { 657 case 0: 658 default: 659 return 4096 * 2; 660 case 1: 661 return 1920 * 2; 662 case 2: 663 return 2560 * 2; 664 } 665 } 666 667 /* controller not enabled, so no lb used */ 668 return 0; 669 } 670 671 /** 672 * cik_get_number_of_dram_channels - get the number of dram channels 673 * 674 * @adev: amdgpu_device pointer 675 * 676 * Look up the number of video ram channels (CIK). 677 * Used for display watermark bandwidth calculations 678 * Returns the number of dram channels 679 */ 680 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) 681 { 682 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 683 684 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 685 case 0: 686 default: 687 return 1; 688 case 1: 689 return 2; 690 case 2: 691 return 4; 692 case 3: 693 return 8; 694 case 4: 695 return 3; 696 case 5: 697 return 6; 698 case 6: 699 return 10; 700 case 7: 701 return 12; 702 case 8: 703 return 16; 704 } 705 } 706 707 struct dce10_wm_params { 708 u32 dram_channels; /* number of dram channels */ 709 u32 yclk; /* bandwidth per dram data pin in kHz */ 710 u32 sclk; /* engine clock in kHz */ 711 u32 disp_clk; /* display clock in kHz */ 712 u32 src_width; /* viewport width */ 713 u32 active_time; /* active display time in ns */ 714 u32 blank_time; /* blank time in ns */ 715 bool interlaced; /* mode is interlaced */ 716 fixed20_12 vsc; /* vertical scale ratio */ 717 u32 num_heads; /* number of active crtcs */ 718 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 719 u32 lb_size; /* line buffer allocated to pipe */ 720 u32 vtaps; /* vertical scaler taps */ 721 }; 722 723 /** 724 * dce_v11_0_dram_bandwidth - get the dram bandwidth 725 * 726 * @wm: watermark calculation data 727 * 728 * Calculate the raw dram bandwidth (CIK). 729 * Used for display watermark bandwidth calculations 730 * Returns the dram bandwidth in MBytes/s 731 */ 732 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm) 733 { 734 /* Calculate raw DRAM Bandwidth */ 735 fixed20_12 dram_efficiency; /* 0.7 */ 736 fixed20_12 yclk, dram_channels, bandwidth; 737 fixed20_12 a; 738 739 a.full = dfixed_const(1000); 740 yclk.full = dfixed_const(wm->yclk); 741 yclk.full = dfixed_div(yclk, a); 742 dram_channels.full = dfixed_const(wm->dram_channels * 4); 743 a.full = dfixed_const(10); 744 dram_efficiency.full = dfixed_const(7); 745 dram_efficiency.full = dfixed_div(dram_efficiency, a); 746 bandwidth.full = dfixed_mul(dram_channels, yclk); 747 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 748 749 return dfixed_trunc(bandwidth); 750 } 751 752 /** 753 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display 754 * 755 * @wm: watermark calculation data 756 * 757 * Calculate the dram bandwidth used for display (CIK). 758 * Used for display watermark bandwidth calculations 759 * Returns the dram bandwidth for display in MBytes/s 760 */ 761 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) 762 { 763 /* Calculate DRAM Bandwidth and the part allocated to display. */ 764 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 765 fixed20_12 yclk, dram_channels, bandwidth; 766 fixed20_12 a; 767 768 a.full = dfixed_const(1000); 769 yclk.full = dfixed_const(wm->yclk); 770 yclk.full = dfixed_div(yclk, a); 771 dram_channels.full = dfixed_const(wm->dram_channels * 4); 772 a.full = dfixed_const(10); 773 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 774 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 775 bandwidth.full = dfixed_mul(dram_channels, yclk); 776 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 777 778 return dfixed_trunc(bandwidth); 779 } 780 781 /** 782 * dce_v11_0_data_return_bandwidth - get the data return bandwidth 783 * 784 * @wm: watermark calculation data 785 * 786 * Calculate the data return bandwidth used for display (CIK). 787 * Used for display watermark bandwidth calculations 788 * Returns the data return bandwidth in MBytes/s 789 */ 790 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm) 791 { 792 /* Calculate the display Data return Bandwidth */ 793 fixed20_12 return_efficiency; /* 0.8 */ 794 fixed20_12 sclk, bandwidth; 795 fixed20_12 a; 796 797 a.full = dfixed_const(1000); 798 sclk.full = dfixed_const(wm->sclk); 799 sclk.full = dfixed_div(sclk, a); 800 a.full = dfixed_const(10); 801 return_efficiency.full = dfixed_const(8); 802 return_efficiency.full = dfixed_div(return_efficiency, a); 803 a.full = dfixed_const(32); 804 bandwidth.full = dfixed_mul(a, sclk); 805 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 806 807 return dfixed_trunc(bandwidth); 808 } 809 810 /** 811 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth 812 * 813 * @wm: watermark calculation data 814 * 815 * Calculate the dmif bandwidth used for display (CIK). 816 * Used for display watermark bandwidth calculations 817 * Returns the dmif bandwidth in MBytes/s 818 */ 819 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm) 820 { 821 /* Calculate the DMIF Request Bandwidth */ 822 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 823 fixed20_12 disp_clk, bandwidth; 824 fixed20_12 a, b; 825 826 a.full = dfixed_const(1000); 827 disp_clk.full = dfixed_const(wm->disp_clk); 828 disp_clk.full = dfixed_div(disp_clk, a); 829 a.full = dfixed_const(32); 830 b.full = dfixed_mul(a, disp_clk); 831 832 a.full = dfixed_const(10); 833 disp_clk_request_efficiency.full = dfixed_const(8); 834 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 835 836 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 837 838 return dfixed_trunc(bandwidth); 839 } 840 841 /** 842 * dce_v11_0_available_bandwidth - get the min available bandwidth 843 * 844 * @wm: watermark calculation data 845 * 846 * Calculate the min available bandwidth used for display (CIK). 847 * Used for display watermark bandwidth calculations 848 * Returns the min available bandwidth in MBytes/s 849 */ 850 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm) 851 { 852 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 853 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm); 854 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm); 855 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm); 856 857 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 858 } 859 860 /** 861 * dce_v11_0_average_bandwidth - get the average available bandwidth 862 * 863 * @wm: watermark calculation data 864 * 865 * Calculate the average available bandwidth used for display (CIK). 866 * Used for display watermark bandwidth calculations 867 * Returns the average available bandwidth in MBytes/s 868 */ 869 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm) 870 { 871 /* Calculate the display mode Average Bandwidth 872 * DisplayMode should contain the source and destination dimensions, 873 * timing, etc. 874 */ 875 fixed20_12 bpp; 876 fixed20_12 line_time; 877 fixed20_12 src_width; 878 fixed20_12 bandwidth; 879 fixed20_12 a; 880 881 a.full = dfixed_const(1000); 882 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 883 line_time.full = dfixed_div(line_time, a); 884 bpp.full = dfixed_const(wm->bytes_per_pixel); 885 src_width.full = dfixed_const(wm->src_width); 886 bandwidth.full = dfixed_mul(src_width, bpp); 887 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 888 bandwidth.full = dfixed_div(bandwidth, line_time); 889 890 return dfixed_trunc(bandwidth); 891 } 892 893 /** 894 * dce_v11_0_latency_watermark - get the latency watermark 895 * 896 * @wm: watermark calculation data 897 * 898 * Calculate the latency watermark (CIK). 899 * Used for display watermark bandwidth calculations 900 * Returns the latency watermark in ns 901 */ 902 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm) 903 { 904 /* First calculate the latency in ns */ 905 u32 mc_latency = 2000; /* 2000 ns. */ 906 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm); 907 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 908 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 909 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 910 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 911 (wm->num_heads * cursor_line_pair_return_time); 912 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 913 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 914 u32 tmp, dmif_size = 12288; 915 fixed20_12 a, b, c; 916 917 if (wm->num_heads == 0) 918 return 0; 919 920 a.full = dfixed_const(2); 921 b.full = dfixed_const(1); 922 if ((wm->vsc.full > a.full) || 923 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 924 (wm->vtaps >= 5) || 925 ((wm->vsc.full >= a.full) && wm->interlaced)) 926 max_src_lines_per_dst_line = 4; 927 else 928 max_src_lines_per_dst_line = 2; 929 930 a.full = dfixed_const(available_bandwidth); 931 b.full = dfixed_const(wm->num_heads); 932 a.full = dfixed_div(a, b); 933 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); 934 tmp = min(dfixed_trunc(a), tmp); 935 936 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); 937 938 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 939 b.full = dfixed_const(1000); 940 c.full = dfixed_const(lb_fill_bw); 941 b.full = dfixed_div(c, b); 942 a.full = dfixed_div(a, b); 943 line_fill_time = dfixed_trunc(a); 944 945 if (line_fill_time < wm->active_time) 946 return latency; 947 else 948 return latency + (line_fill_time - wm->active_time); 949 950 } 951 952 /** 953 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check 954 * average and available dram bandwidth 955 * 956 * @wm: watermark calculation data 957 * 958 * Check if the display average bandwidth fits in the display 959 * dram bandwidth (CIK). 960 * Used for display watermark bandwidth calculations 961 * Returns true if the display fits, false if not. 962 */ 963 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm) 964 { 965 if (dce_v11_0_average_bandwidth(wm) <= 966 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 967 return true; 968 else 969 return false; 970 } 971 972 /** 973 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check 974 * average and available bandwidth 975 * 976 * @wm: watermark calculation data 977 * 978 * Check if the display average bandwidth fits in the display 979 * available bandwidth (CIK). 980 * Used for display watermark bandwidth calculations 981 * Returns true if the display fits, false if not. 982 */ 983 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm) 984 { 985 if (dce_v11_0_average_bandwidth(wm) <= 986 (dce_v11_0_available_bandwidth(wm) / wm->num_heads)) 987 return true; 988 else 989 return false; 990 } 991 992 /** 993 * dce_v11_0_check_latency_hiding - check latency hiding 994 * 995 * @wm: watermark calculation data 996 * 997 * Check latency hiding (CIK). 998 * Used for display watermark bandwidth calculations 999 * Returns true if the display fits, false if not. 1000 */ 1001 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm) 1002 { 1003 u32 lb_partitions = wm->lb_size / wm->src_width; 1004 u32 line_time = wm->active_time + wm->blank_time; 1005 u32 latency_tolerant_lines; 1006 u32 latency_hiding; 1007 fixed20_12 a; 1008 1009 a.full = dfixed_const(1); 1010 if (wm->vsc.full > a.full) 1011 latency_tolerant_lines = 1; 1012 else { 1013 if (lb_partitions <= (wm->vtaps + 1)) 1014 latency_tolerant_lines = 1; 1015 else 1016 latency_tolerant_lines = 2; 1017 } 1018 1019 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 1020 1021 if (dce_v11_0_latency_watermark(wm) <= latency_hiding) 1022 return true; 1023 else 1024 return false; 1025 } 1026 1027 /** 1028 * dce_v11_0_program_watermarks - program display watermarks 1029 * 1030 * @adev: amdgpu_device pointer 1031 * @amdgpu_crtc: the selected display controller 1032 * @lb_size: line buffer size 1033 * @num_heads: number of display controllers in use 1034 * 1035 * Calculate and program the display watermarks for the 1036 * selected display controller (CIK). 1037 */ 1038 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev, 1039 struct amdgpu_crtc *amdgpu_crtc, 1040 u32 lb_size, u32 num_heads) 1041 { 1042 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 1043 struct dce10_wm_params wm_low, wm_high; 1044 u32 active_time; 1045 u32 line_time = 0; 1046 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1047 u32 tmp, wm_mask, lb_vblank_lead_lines = 0; 1048 1049 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1050 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, 1051 (u32)mode->clock); 1052 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, 1053 (u32)mode->clock); 1054 line_time = min(line_time, (u32)65535); 1055 1056 /* watermark for high clocks */ 1057 if (adev->pm.dpm_enabled) { 1058 wm_high.yclk = 1059 amdgpu_dpm_get_mclk(adev, false) * 10; 1060 wm_high.sclk = 1061 amdgpu_dpm_get_sclk(adev, false) * 10; 1062 } else { 1063 wm_high.yclk = adev->pm.current_mclk * 10; 1064 wm_high.sclk = adev->pm.current_sclk * 10; 1065 } 1066 1067 wm_high.disp_clk = mode->clock; 1068 wm_high.src_width = mode->crtc_hdisplay; 1069 wm_high.active_time = active_time; 1070 wm_high.blank_time = line_time - wm_high.active_time; 1071 wm_high.interlaced = false; 1072 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1073 wm_high.interlaced = true; 1074 wm_high.vsc = amdgpu_crtc->vsc; 1075 wm_high.vtaps = 1; 1076 if (amdgpu_crtc->rmx_type != RMX_OFF) 1077 wm_high.vtaps = 2; 1078 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1079 wm_high.lb_size = lb_size; 1080 wm_high.dram_channels = cik_get_number_of_dram_channels(adev); 1081 wm_high.num_heads = num_heads; 1082 1083 /* set for high clocks */ 1084 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535); 1085 1086 /* possibly force display priority to high */ 1087 /* should really do this at mode validation time... */ 1088 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 1089 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 1090 !dce_v11_0_check_latency_hiding(&wm_high) || 1091 (adev->mode_info.disp_priority == 2)) { 1092 DRM_DEBUG_KMS("force priority to high\n"); 1093 } 1094 1095 /* watermark for low clocks */ 1096 if (adev->pm.dpm_enabled) { 1097 wm_low.yclk = 1098 amdgpu_dpm_get_mclk(adev, true) * 10; 1099 wm_low.sclk = 1100 amdgpu_dpm_get_sclk(adev, true) * 10; 1101 } else { 1102 wm_low.yclk = adev->pm.current_mclk * 10; 1103 wm_low.sclk = adev->pm.current_sclk * 10; 1104 } 1105 1106 wm_low.disp_clk = mode->clock; 1107 wm_low.src_width = mode->crtc_hdisplay; 1108 wm_low.active_time = active_time; 1109 wm_low.blank_time = line_time - wm_low.active_time; 1110 wm_low.interlaced = false; 1111 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1112 wm_low.interlaced = true; 1113 wm_low.vsc = amdgpu_crtc->vsc; 1114 wm_low.vtaps = 1; 1115 if (amdgpu_crtc->rmx_type != RMX_OFF) 1116 wm_low.vtaps = 2; 1117 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1118 wm_low.lb_size = lb_size; 1119 wm_low.dram_channels = cik_get_number_of_dram_channels(adev); 1120 wm_low.num_heads = num_heads; 1121 1122 /* set for low clocks */ 1123 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535); 1124 1125 /* possibly force display priority to high */ 1126 /* should really do this at mode validation time... */ 1127 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 1128 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 1129 !dce_v11_0_check_latency_hiding(&wm_low) || 1130 (adev->mode_info.disp_priority == 2)) { 1131 DRM_DEBUG_KMS("force priority to high\n"); 1132 } 1133 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 1134 } 1135 1136 /* select wm A */ 1137 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1138 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); 1139 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1140 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1141 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); 1142 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1143 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1144 /* select wm B */ 1145 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); 1146 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1147 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1148 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); 1149 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1150 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1151 /* restore original selection */ 1152 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); 1153 1154 /* save values for DPM */ 1155 amdgpu_crtc->line_time = line_time; 1156 amdgpu_crtc->wm_high = latency_watermark_a; 1157 amdgpu_crtc->wm_low = latency_watermark_b; 1158 /* Save number of lines the linebuffer leads before the scanout */ 1159 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1160 } 1161 1162 /** 1163 * dce_v11_0_bandwidth_update - program display watermarks 1164 * 1165 * @adev: amdgpu_device pointer 1166 * 1167 * Calculate and program the display watermarks and line 1168 * buffer allocation (CIK). 1169 */ 1170 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev) 1171 { 1172 struct drm_display_mode *mode = NULL; 1173 u32 num_heads = 0, lb_size; 1174 int i; 1175 1176 amdgpu_display_update_priority(adev); 1177 1178 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1179 if (adev->mode_info.crtcs[i]->base.enabled) 1180 num_heads++; 1181 } 1182 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1183 mode = &adev->mode_info.crtcs[i]->base.mode; 1184 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); 1185 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i], 1186 lb_size, num_heads); 1187 } 1188 } 1189 1190 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev) 1191 { 1192 int i; 1193 u32 offset, tmp; 1194 1195 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1196 offset = adev->mode_info.audio.pin[i].offset; 1197 tmp = RREG32_AUDIO_ENDPT(offset, 1198 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1199 if (((tmp & 1200 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> 1201 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) 1202 adev->mode_info.audio.pin[i].connected = false; 1203 else 1204 adev->mode_info.audio.pin[i].connected = true; 1205 } 1206 } 1207 1208 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev) 1209 { 1210 int i; 1211 1212 dce_v11_0_audio_get_connected_pins(adev); 1213 1214 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1215 if (adev->mode_info.audio.pin[i].connected) 1216 return &adev->mode_info.audio.pin[i]; 1217 } 1218 DRM_ERROR("No connected audio pins found!\n"); 1219 return NULL; 1220 } 1221 1222 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder) 1223 { 1224 struct amdgpu_device *adev = encoder->dev->dev_private; 1225 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1226 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1227 u32 tmp; 1228 1229 if (!dig || !dig->afmt || !dig->afmt->pin) 1230 return; 1231 1232 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); 1233 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); 1234 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); 1235 } 1236 1237 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder, 1238 struct drm_display_mode *mode) 1239 { 1240 struct amdgpu_device *adev = encoder->dev->dev_private; 1241 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1242 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1243 struct drm_connector *connector; 1244 struct amdgpu_connector *amdgpu_connector = NULL; 1245 u32 tmp; 1246 int interlace = 0; 1247 1248 if (!dig || !dig->afmt || !dig->afmt->pin) 1249 return; 1250 1251 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1252 if (connector->encoder == encoder) { 1253 amdgpu_connector = to_amdgpu_connector(connector); 1254 break; 1255 } 1256 } 1257 1258 if (!amdgpu_connector) { 1259 DRM_ERROR("Couldn't find encoder's connector\n"); 1260 return; 1261 } 1262 1263 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1264 interlace = 1; 1265 if (connector->latency_present[interlace]) { 1266 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1267 VIDEO_LIPSYNC, connector->video_latency[interlace]); 1268 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1269 AUDIO_LIPSYNC, connector->audio_latency[interlace]); 1270 } else { 1271 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1272 VIDEO_LIPSYNC, 0); 1273 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1274 AUDIO_LIPSYNC, 0); 1275 } 1276 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1277 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1278 } 1279 1280 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1281 { 1282 struct amdgpu_device *adev = encoder->dev->dev_private; 1283 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1284 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1285 struct drm_connector *connector; 1286 struct amdgpu_connector *amdgpu_connector = NULL; 1287 u32 tmp; 1288 u8 *sadb = NULL; 1289 int sad_count; 1290 1291 if (!dig || !dig->afmt || !dig->afmt->pin) 1292 return; 1293 1294 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1295 if (connector->encoder == encoder) { 1296 amdgpu_connector = to_amdgpu_connector(connector); 1297 break; 1298 } 1299 } 1300 1301 if (!amdgpu_connector) { 1302 DRM_ERROR("Couldn't find encoder's connector\n"); 1303 return; 1304 } 1305 1306 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); 1307 if (sad_count < 0) { 1308 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1309 sad_count = 0; 1310 } 1311 1312 /* program the speaker allocation */ 1313 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1314 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1315 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1316 DP_CONNECTION, 0); 1317 /* set HDMI mode */ 1318 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1319 HDMI_CONNECTION, 1); 1320 if (sad_count) 1321 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1322 SPEAKER_ALLOCATION, sadb[0]); 1323 else 1324 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1325 SPEAKER_ALLOCATION, 5); /* stereo */ 1326 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1327 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1328 1329 kfree(sadb); 1330 } 1331 1332 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder) 1333 { 1334 struct amdgpu_device *adev = encoder->dev->dev_private; 1335 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1336 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1337 struct drm_connector *connector; 1338 struct amdgpu_connector *amdgpu_connector = NULL; 1339 struct cea_sad *sads; 1340 int i, sad_count; 1341 1342 static const u16 eld_reg_to_type[][2] = { 1343 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1344 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1345 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1346 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1347 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1348 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1349 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1350 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1351 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1352 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1353 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1354 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1355 }; 1356 1357 if (!dig || !dig->afmt || !dig->afmt->pin) 1358 return; 1359 1360 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1361 if (connector->encoder == encoder) { 1362 amdgpu_connector = to_amdgpu_connector(connector); 1363 break; 1364 } 1365 } 1366 1367 if (!amdgpu_connector) { 1368 DRM_ERROR("Couldn't find encoder's connector\n"); 1369 return; 1370 } 1371 1372 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); 1373 if (sad_count <= 0) { 1374 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1375 return; 1376 } 1377 BUG_ON(!sads); 1378 1379 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1380 u32 tmp = 0; 1381 u8 stereo_freqs = 0; 1382 int max_channels = -1; 1383 int j; 1384 1385 for (j = 0; j < sad_count; j++) { 1386 struct cea_sad *sad = &sads[j]; 1387 1388 if (sad->format == eld_reg_to_type[i][1]) { 1389 if (sad->channels > max_channels) { 1390 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1391 MAX_CHANNELS, sad->channels); 1392 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1393 DESCRIPTOR_BYTE_2, sad->byte2); 1394 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1395 SUPPORTED_FREQUENCIES, sad->freq); 1396 max_channels = sad->channels; 1397 } 1398 1399 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1400 stereo_freqs |= sad->freq; 1401 else 1402 break; 1403 } 1404 } 1405 1406 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1407 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); 1408 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); 1409 } 1410 1411 kfree(sads); 1412 } 1413 1414 static void dce_v11_0_audio_enable(struct amdgpu_device *adev, 1415 struct amdgpu_audio_pin *pin, 1416 bool enable) 1417 { 1418 if (!pin) 1419 return; 1420 1421 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1422 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1423 } 1424 1425 static const u32 pin_offsets[] = 1426 { 1427 AUD0_REGISTER_OFFSET, 1428 AUD1_REGISTER_OFFSET, 1429 AUD2_REGISTER_OFFSET, 1430 AUD3_REGISTER_OFFSET, 1431 AUD4_REGISTER_OFFSET, 1432 AUD5_REGISTER_OFFSET, 1433 AUD6_REGISTER_OFFSET, 1434 AUD7_REGISTER_OFFSET, 1435 }; 1436 1437 static int dce_v11_0_audio_init(struct amdgpu_device *adev) 1438 { 1439 int i; 1440 1441 if (!amdgpu_audio) 1442 return 0; 1443 1444 adev->mode_info.audio.enabled = true; 1445 1446 switch (adev->asic_type) { 1447 case CHIP_CARRIZO: 1448 case CHIP_STONEY: 1449 adev->mode_info.audio.num_pins = 7; 1450 break; 1451 case CHIP_POLARIS10: 1452 case CHIP_VEGAM: 1453 adev->mode_info.audio.num_pins = 8; 1454 break; 1455 case CHIP_POLARIS11: 1456 case CHIP_POLARIS12: 1457 adev->mode_info.audio.num_pins = 6; 1458 break; 1459 default: 1460 return -EINVAL; 1461 } 1462 1463 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1464 adev->mode_info.audio.pin[i].channels = -1; 1465 adev->mode_info.audio.pin[i].rate = -1; 1466 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1467 adev->mode_info.audio.pin[i].status_bits = 0; 1468 adev->mode_info.audio.pin[i].category_code = 0; 1469 adev->mode_info.audio.pin[i].connected = false; 1470 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1471 adev->mode_info.audio.pin[i].id = i; 1472 /* disable audio. it will be set up later */ 1473 /* XXX remove once we switch to ip funcs */ 1474 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1475 } 1476 1477 return 0; 1478 } 1479 1480 static void dce_v11_0_audio_fini(struct amdgpu_device *adev) 1481 { 1482 int i; 1483 1484 if (!amdgpu_audio) 1485 return; 1486 1487 if (!adev->mode_info.audio.enabled) 1488 return; 1489 1490 for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1491 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1492 1493 adev->mode_info.audio.enabled = false; 1494 } 1495 1496 /* 1497 * update the N and CTS parameters for a given pixel clock rate 1498 */ 1499 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) 1500 { 1501 struct drm_device *dev = encoder->dev; 1502 struct amdgpu_device *adev = dev->dev_private; 1503 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1504 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1505 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1506 u32 tmp; 1507 1508 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); 1509 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); 1510 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); 1511 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); 1512 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); 1513 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); 1514 1515 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); 1516 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); 1517 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); 1518 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); 1519 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); 1520 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); 1521 1522 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); 1523 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); 1524 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); 1525 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); 1526 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); 1527 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); 1528 1529 } 1530 1531 /* 1532 * build a HDMI Video Info Frame 1533 */ 1534 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, 1535 void *buffer, size_t size) 1536 { 1537 struct drm_device *dev = encoder->dev; 1538 struct amdgpu_device *adev = dev->dev_private; 1539 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1540 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1541 uint8_t *frame = buffer + 3; 1542 uint8_t *header = buffer; 1543 1544 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, 1545 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 1546 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, 1547 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 1548 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, 1549 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 1550 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, 1551 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 1552 } 1553 1554 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1555 { 1556 struct drm_device *dev = encoder->dev; 1557 struct amdgpu_device *adev = dev->dev_private; 1558 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1559 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1560 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1561 u32 dto_phase = 24 * 1000; 1562 u32 dto_modulo = clock; 1563 u32 tmp; 1564 1565 if (!dig || !dig->afmt) 1566 return; 1567 1568 /* XXX two dtos; generally use dto0 for hdmi */ 1569 /* Express [24MHz / target pixel clock] as an exact rational 1570 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1571 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1572 */ 1573 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); 1574 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, 1575 amdgpu_crtc->crtc_id); 1576 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); 1577 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); 1578 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); 1579 } 1580 1581 /* 1582 * update the info frames with the data from the current display mode 1583 */ 1584 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder, 1585 struct drm_display_mode *mode) 1586 { 1587 struct drm_device *dev = encoder->dev; 1588 struct amdgpu_device *adev = dev->dev_private; 1589 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1590 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1591 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1592 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1593 struct hdmi_avi_infoframe frame; 1594 ssize_t err; 1595 u32 tmp; 1596 int bpc = 8; 1597 1598 if (!dig || !dig->afmt) 1599 return; 1600 1601 /* Silent, r600_hdmi_enable will raise WARN for us */ 1602 if (!dig->afmt->enabled) 1603 return; 1604 1605 /* hdmi deep color mode general control packets setup, if bpc > 8 */ 1606 if (encoder->crtc) { 1607 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1608 bpc = amdgpu_crtc->bpc; 1609 } 1610 1611 /* disable audio prior to setting up hw */ 1612 dig->afmt->pin = dce_v11_0_audio_get_pin(adev); 1613 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); 1614 1615 dce_v11_0_audio_set_dto(encoder, mode->clock); 1616 1617 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1618 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); 1619 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ 1620 1621 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); 1622 1623 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); 1624 switch (bpc) { 1625 case 0: 1626 case 6: 1627 case 8: 1628 case 16: 1629 default: 1630 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); 1631 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 1632 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", 1633 connector->name, bpc); 1634 break; 1635 case 10: 1636 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1637 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); 1638 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", 1639 connector->name); 1640 break; 1641 case 12: 1642 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1643 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); 1644 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", 1645 connector->name); 1646 break; 1647 } 1648 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); 1649 1650 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1651 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ 1652 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ 1653 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ 1654 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); 1655 1656 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1657 /* enable audio info frames (frames won't be set until audio is enabled) */ 1658 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 1659 /* required for audio info values to be updated */ 1660 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); 1661 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1662 1663 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); 1664 /* required for audio info values to be updated */ 1665 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1666 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1667 1668 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1669 /* anything other than 0 */ 1670 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); 1671 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1672 1673 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ 1674 1675 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1676 /* set the default audio delay */ 1677 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); 1678 /* should be suffient for all audio modes and small enough for all hblanks */ 1679 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); 1680 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1681 1682 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1683 /* allow 60958 channel status fields to be updated */ 1684 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1685 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1686 1687 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); 1688 if (bpc > 8) 1689 /* clear SW CTS value */ 1690 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); 1691 else 1692 /* select SW CTS value */ 1693 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); 1694 /* allow hw to sent ACR packets when required */ 1695 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); 1696 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); 1697 1698 dce_v11_0_afmt_update_ACR(encoder, mode->clock); 1699 1700 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); 1701 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); 1702 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); 1703 1704 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); 1705 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1706 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); 1707 1708 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); 1709 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); 1710 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); 1711 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); 1712 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); 1713 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); 1714 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1715 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); 1716 1717 dce_v11_0_audio_write_speaker_allocation(encoder); 1718 1719 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, 1720 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); 1721 1722 dce_v11_0_afmt_audio_select_pin(encoder); 1723 dce_v11_0_audio_write_sad_regs(encoder); 1724 dce_v11_0_audio_write_latency_fields(encoder, mode); 1725 1726 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false); 1727 if (err < 0) { 1728 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1729 return; 1730 } 1731 1732 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1733 if (err < 0) { 1734 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1735 return; 1736 } 1737 1738 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 1739 1740 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1741 /* enable AVI info frames */ 1742 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); 1743 /* required for audio info values to be updated */ 1744 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); 1745 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1746 1747 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1748 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); 1749 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1750 1751 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1752 /* send audio packets */ 1753 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1754 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1755 1756 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); 1757 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); 1758 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); 1759 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); 1760 1761 /* enable audio after to setting up hw */ 1762 dce_v11_0_audio_enable(adev, dig->afmt->pin, true); 1763 } 1764 1765 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1766 { 1767 struct drm_device *dev = encoder->dev; 1768 struct amdgpu_device *adev = dev->dev_private; 1769 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1770 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1771 1772 if (!dig || !dig->afmt) 1773 return; 1774 1775 /* Silent, r600_hdmi_enable will raise WARN for us */ 1776 if (enable && dig->afmt->enabled) 1777 return; 1778 if (!enable && !dig->afmt->enabled) 1779 return; 1780 1781 if (!enable && dig->afmt->pin) { 1782 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); 1783 dig->afmt->pin = NULL; 1784 } 1785 1786 dig->afmt->enabled = enable; 1787 1788 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1789 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1790 } 1791 1792 static int dce_v11_0_afmt_init(struct amdgpu_device *adev) 1793 { 1794 int i; 1795 1796 for (i = 0; i < adev->mode_info.num_dig; i++) 1797 adev->mode_info.afmt[i] = NULL; 1798 1799 /* DCE11 has audio blocks tied to DIG encoders */ 1800 for (i = 0; i < adev->mode_info.num_dig; i++) { 1801 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 1802 if (adev->mode_info.afmt[i]) { 1803 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1804 adev->mode_info.afmt[i]->id = i; 1805 } else { 1806 int j; 1807 for (j = 0; j < i; j++) { 1808 kfree(adev->mode_info.afmt[j]); 1809 adev->mode_info.afmt[j] = NULL; 1810 } 1811 return -ENOMEM; 1812 } 1813 } 1814 return 0; 1815 } 1816 1817 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev) 1818 { 1819 int i; 1820 1821 for (i = 0; i < adev->mode_info.num_dig; i++) { 1822 kfree(adev->mode_info.afmt[i]); 1823 adev->mode_info.afmt[i] = NULL; 1824 } 1825 } 1826 1827 static const u32 vga_control_regs[6] = 1828 { 1829 mmD1VGA_CONTROL, 1830 mmD2VGA_CONTROL, 1831 mmD3VGA_CONTROL, 1832 mmD4VGA_CONTROL, 1833 mmD5VGA_CONTROL, 1834 mmD6VGA_CONTROL, 1835 }; 1836 1837 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable) 1838 { 1839 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1840 struct drm_device *dev = crtc->dev; 1841 struct amdgpu_device *adev = dev->dev_private; 1842 u32 vga_control; 1843 1844 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 1845 if (enable) 1846 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); 1847 else 1848 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); 1849 } 1850 1851 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable) 1852 { 1853 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1854 struct drm_device *dev = crtc->dev; 1855 struct amdgpu_device *adev = dev->dev_private; 1856 1857 if (enable) 1858 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); 1859 else 1860 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); 1861 } 1862 1863 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, 1864 struct drm_framebuffer *fb, 1865 int x, int y, int atomic) 1866 { 1867 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1868 struct drm_device *dev = crtc->dev; 1869 struct amdgpu_device *adev = dev->dev_private; 1870 struct drm_framebuffer *target_fb; 1871 struct drm_gem_object *obj; 1872 struct amdgpu_bo *abo; 1873 uint64_t fb_location, tiling_flags; 1874 uint32_t fb_format, fb_pitch_pixels; 1875 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); 1876 u32 pipe_config; 1877 u32 tmp, viewport_w, viewport_h; 1878 int r; 1879 bool bypass_lut = false; 1880 struct drm_format_name_buf format_name; 1881 1882 /* no fb bound */ 1883 if (!atomic && !crtc->primary->fb) { 1884 DRM_DEBUG_KMS("No FB bound\n"); 1885 return 0; 1886 } 1887 1888 if (atomic) 1889 target_fb = fb; 1890 else 1891 target_fb = crtc->primary->fb; 1892 1893 /* If atomic, assume fb object is pinned & idle & fenced and 1894 * just update base pointers 1895 */ 1896 obj = target_fb->obj[0]; 1897 abo = gem_to_amdgpu_bo(obj); 1898 r = amdgpu_bo_reserve(abo, false); 1899 if (unlikely(r != 0)) 1900 return r; 1901 1902 if (!atomic) { 1903 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); 1904 if (unlikely(r != 0)) { 1905 amdgpu_bo_unreserve(abo); 1906 return -EINVAL; 1907 } 1908 } 1909 fb_location = amdgpu_bo_gpu_offset(abo); 1910 1911 amdgpu_bo_get_tiling_flags(abo, (u64 *)&tiling_flags); 1912 amdgpu_bo_unreserve(abo); 1913 1914 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 1915 1916 switch (target_fb->format->format) { 1917 case DRM_FORMAT_C8: 1918 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); 1919 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 1920 break; 1921 case DRM_FORMAT_XRGB4444: 1922 case DRM_FORMAT_ARGB4444: 1923 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1924 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2); 1925 #ifdef __BIG_ENDIAN 1926 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1927 ENDIAN_8IN16); 1928 #endif 1929 break; 1930 case DRM_FORMAT_XRGB1555: 1931 case DRM_FORMAT_ARGB1555: 1932 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1933 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 1934 #ifdef __BIG_ENDIAN 1935 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1936 ENDIAN_8IN16); 1937 #endif 1938 break; 1939 case DRM_FORMAT_BGRX5551: 1940 case DRM_FORMAT_BGRA5551: 1941 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1942 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5); 1943 #ifdef __BIG_ENDIAN 1944 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1945 ENDIAN_8IN16); 1946 #endif 1947 break; 1948 case DRM_FORMAT_RGB565: 1949 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1950 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 1951 #ifdef __BIG_ENDIAN 1952 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1953 ENDIAN_8IN16); 1954 #endif 1955 break; 1956 case DRM_FORMAT_XRGB8888: 1957 case DRM_FORMAT_ARGB8888: 1958 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 1959 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 1960 #ifdef __BIG_ENDIAN 1961 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1962 ENDIAN_8IN32); 1963 #endif 1964 break; 1965 case DRM_FORMAT_XRGB2101010: 1966 case DRM_FORMAT_ARGB2101010: 1967 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 1968 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 1969 #ifdef __BIG_ENDIAN 1970 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1971 ENDIAN_8IN32); 1972 #endif 1973 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1974 bypass_lut = true; 1975 break; 1976 case DRM_FORMAT_BGRX1010102: 1977 case DRM_FORMAT_BGRA1010102: 1978 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 1979 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4); 1980 #ifdef __BIG_ENDIAN 1981 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1982 ENDIAN_8IN32); 1983 #endif 1984 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1985 bypass_lut = true; 1986 break; 1987 default: 1988 DRM_ERROR("Unsupported screen format %s\n", 1989 drm_get_format_name(target_fb->format->format, &format_name)); 1990 return -EINVAL; 1991 } 1992 1993 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 1994 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 1995 1996 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 1997 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 1998 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 1999 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2000 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2001 2002 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); 2003 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2004 ARRAY_2D_TILED_THIN1); 2005 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT, 2006 tile_split); 2007 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); 2008 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh); 2009 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, 2010 mtaspect); 2011 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, 2012 ADDR_SURF_MICRO_TILING_DISPLAY); 2013 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 2014 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2015 ARRAY_1D_TILED_THIN1); 2016 } 2017 2018 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG, 2019 pipe_config); 2020 2021 dce_v11_0_vga_enable(crtc, false); 2022 2023 /* Make sure surface address is updated at vertical blank rather than 2024 * horizontal blank 2025 */ 2026 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 2027 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 2028 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); 2029 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2030 2031 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2032 upper_32_bits(fb_location)); 2033 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2034 upper_32_bits(fb_location)); 2035 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2036 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2037 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2038 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); 2039 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2040 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 2041 2042 /* 2043 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 2044 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 2045 * retain the full precision throughout the pipeline. 2046 */ 2047 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); 2048 if (bypass_lut) 2049 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); 2050 else 2051 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); 2052 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); 2053 2054 if (bypass_lut) 2055 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2056 2057 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2058 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2059 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2060 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2061 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2062 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2063 2064 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; 2065 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2066 2067 dce_v11_0_grph_enable(crtc, true); 2068 2069 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2070 target_fb->height); 2071 2072 x &= ~3; 2073 y &= ~1; 2074 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2075 (x << 16) | y); 2076 viewport_w = crtc->mode.hdisplay; 2077 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2078 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2079 (viewport_w << 16) | viewport_h); 2080 2081 /* set pageflip to happen anywhere in vblank interval */ 2082 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); 2083 2084 if (!atomic && fb && fb != crtc->primary->fb) { 2085 abo = gem_to_amdgpu_bo(fb->obj[0]); 2086 r = amdgpu_bo_reserve(abo, true); 2087 if (unlikely(r != 0)) 2088 return r; 2089 amdgpu_bo_unpin(abo); 2090 amdgpu_bo_unreserve(abo); 2091 } 2092 2093 /* Bytes per pixel may have changed */ 2094 dce_v11_0_bandwidth_update(adev); 2095 2096 return 0; 2097 } 2098 2099 static void dce_v11_0_set_interleave(struct drm_crtc *crtc, 2100 struct drm_display_mode *mode) 2101 { 2102 struct drm_device *dev = crtc->dev; 2103 struct amdgpu_device *adev = dev->dev_private; 2104 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2105 u32 tmp; 2106 2107 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); 2108 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2109 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); 2110 else 2111 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); 2112 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); 2113 } 2114 2115 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc) 2116 { 2117 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2118 struct drm_device *dev = crtc->dev; 2119 struct amdgpu_device *adev = dev->dev_private; 2120 u16 *r, *g, *b; 2121 int i; 2122 u32 tmp; 2123 2124 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2125 2126 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2127 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); 2128 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2129 2130 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); 2131 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); 2132 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2133 2134 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2135 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); 2136 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2137 2138 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2139 2140 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2141 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2142 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2143 2144 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2145 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2146 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2147 2148 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2149 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2150 2151 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2152 r = crtc->gamma_store; 2153 g = r + crtc->gamma_size; 2154 b = g + crtc->gamma_size; 2155 for (i = 0; i < 256; i++) { 2156 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2157 ((*r++ & 0xffc0) << 14) | 2158 ((*g++ & 0xffc0) << 4) | 2159 (*b++ >> 6)); 2160 } 2161 2162 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2163 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); 2164 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); 2165 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0); 2166 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2167 2168 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); 2169 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); 2170 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2171 2172 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2173 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); 2174 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2175 2176 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2177 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); 2178 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2179 2180 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2181 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); 2182 /* XXX this only needs to be programmed once per crtc at startup, 2183 * not sure where the best place for it is 2184 */ 2185 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); 2186 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); 2187 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2188 } 2189 2190 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder) 2191 { 2192 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2193 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2194 2195 switch (amdgpu_encoder->encoder_id) { 2196 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2197 if (dig->linkb) 2198 return 1; 2199 else 2200 return 0; 2201 break; 2202 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2203 if (dig->linkb) 2204 return 3; 2205 else 2206 return 2; 2207 break; 2208 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2209 if (dig->linkb) 2210 return 5; 2211 else 2212 return 4; 2213 break; 2214 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2215 return 6; 2216 break; 2217 default: 2218 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2219 return 0; 2220 } 2221 } 2222 2223 /** 2224 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc. 2225 * 2226 * @crtc: drm crtc 2227 * 2228 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2229 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2230 * monitors a dedicated PPLL must be used. If a particular board has 2231 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2232 * as there is no need to program the PLL itself. If we are not able to 2233 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2234 * avoid messing up an existing monitor. 2235 * 2236 * Asic specific PLL information 2237 * 2238 * DCE 10.x 2239 * Tonga 2240 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 2241 * CI 2242 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 2243 * 2244 */ 2245 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc) 2246 { 2247 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2248 struct drm_device *dev = crtc->dev; 2249 struct amdgpu_device *adev = dev->dev_private; 2250 u32 pll_in_use; 2251 int pll; 2252 2253 if ((adev->asic_type == CHIP_POLARIS10) || 2254 (adev->asic_type == CHIP_POLARIS11) || 2255 (adev->asic_type == CHIP_POLARIS12) || 2256 (adev->asic_type == CHIP_VEGAM)) { 2257 struct amdgpu_encoder *amdgpu_encoder = 2258 to_amdgpu_encoder(amdgpu_crtc->encoder); 2259 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2260 2261 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2262 return ATOM_DP_DTO; 2263 2264 switch (amdgpu_encoder->encoder_id) { 2265 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2266 if (dig->linkb) 2267 return ATOM_COMBOPHY_PLL1; 2268 else 2269 return ATOM_COMBOPHY_PLL0; 2270 break; 2271 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2272 if (dig->linkb) 2273 return ATOM_COMBOPHY_PLL3; 2274 else 2275 return ATOM_COMBOPHY_PLL2; 2276 break; 2277 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2278 if (dig->linkb) 2279 return ATOM_COMBOPHY_PLL5; 2280 else 2281 return ATOM_COMBOPHY_PLL4; 2282 break; 2283 default: 2284 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2285 return ATOM_PPLL_INVALID; 2286 } 2287 } 2288 2289 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2290 if (adev->clock.dp_extclk) 2291 /* skip PPLL programming if using ext clock */ 2292 return ATOM_PPLL_INVALID; 2293 else { 2294 /* use the same PPLL for all DP monitors */ 2295 pll = amdgpu_pll_get_shared_dp_ppll(crtc); 2296 if (pll != ATOM_PPLL_INVALID) 2297 return pll; 2298 } 2299 } else { 2300 /* use the same PPLL for all monitors with the same clock */ 2301 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2302 if (pll != ATOM_PPLL_INVALID) 2303 return pll; 2304 } 2305 2306 /* XXX need to determine what plls are available on each DCE11 part */ 2307 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2308 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) { 2309 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2310 return ATOM_PPLL1; 2311 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2312 return ATOM_PPLL0; 2313 DRM_ERROR("unable to allocate a PPLL\n"); 2314 return ATOM_PPLL_INVALID; 2315 } else { 2316 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2317 return ATOM_PPLL2; 2318 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2319 return ATOM_PPLL1; 2320 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2321 return ATOM_PPLL0; 2322 DRM_ERROR("unable to allocate a PPLL\n"); 2323 return ATOM_PPLL_INVALID; 2324 } 2325 return ATOM_PPLL_INVALID; 2326 } 2327 2328 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2329 { 2330 struct amdgpu_device *adev = crtc->dev->dev_private; 2331 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2332 uint32_t cur_lock; 2333 2334 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2335 if (lock) 2336 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1); 2337 else 2338 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0); 2339 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2340 } 2341 2342 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc) 2343 { 2344 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2345 struct amdgpu_device *adev = crtc->dev->dev_private; 2346 u32 tmp; 2347 2348 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2349 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); 2350 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2351 } 2352 2353 static void dce_v11_0_show_cursor(struct drm_crtc *crtc) 2354 { 2355 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2356 struct amdgpu_device *adev = crtc->dev->dev_private; 2357 u32 tmp; 2358 2359 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2360 upper_32_bits(amdgpu_crtc->cursor_addr)); 2361 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2362 lower_32_bits(amdgpu_crtc->cursor_addr)); 2363 2364 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2365 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); 2366 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); 2367 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2368 } 2369 2370 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc, 2371 int x, int y) 2372 { 2373 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2374 struct amdgpu_device *adev = crtc->dev->dev_private; 2375 int xorigin = 0, yorigin = 0; 2376 2377 amdgpu_crtc->cursor_x = x; 2378 amdgpu_crtc->cursor_y = y; 2379 2380 /* avivo cursor are offset into the total surface */ 2381 x += crtc->x; 2382 y += crtc->y; 2383 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2384 2385 if (x < 0) { 2386 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2387 x = 0; 2388 } 2389 if (y < 0) { 2390 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2391 y = 0; 2392 } 2393 2394 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2395 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2396 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2397 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2398 2399 return 0; 2400 } 2401 2402 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc, 2403 int x, int y) 2404 { 2405 int ret; 2406 2407 dce_v11_0_lock_cursor(crtc, true); 2408 ret = dce_v11_0_cursor_move_locked(crtc, x, y); 2409 dce_v11_0_lock_cursor(crtc, false); 2410 2411 return ret; 2412 } 2413 2414 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, 2415 struct drm_file *file_priv, 2416 uint32_t handle, 2417 uint32_t width, 2418 uint32_t height, 2419 int32_t hot_x, 2420 int32_t hot_y) 2421 { 2422 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2423 struct drm_gem_object *obj; 2424 struct amdgpu_bo *aobj; 2425 int ret; 2426 2427 if (!handle) { 2428 /* turn off cursor */ 2429 dce_v11_0_hide_cursor(crtc); 2430 obj = NULL; 2431 goto unpin; 2432 } 2433 2434 if ((width > amdgpu_crtc->max_cursor_width) || 2435 (height > amdgpu_crtc->max_cursor_height)) { 2436 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2437 return -EINVAL; 2438 } 2439 2440 obj = drm_gem_object_lookup(file_priv, handle); 2441 if (!obj) { 2442 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2443 return -ENOENT; 2444 } 2445 2446 aobj = gem_to_amdgpu_bo(obj); 2447 ret = amdgpu_bo_reserve(aobj, false); 2448 if (ret != 0) { 2449 drm_gem_object_put_unlocked(obj); 2450 return ret; 2451 } 2452 2453 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); 2454 amdgpu_bo_unreserve(aobj); 2455 if (ret) { 2456 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2457 drm_gem_object_put_unlocked(obj); 2458 return ret; 2459 } 2460 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); 2461 2462 dce_v11_0_lock_cursor(crtc, true); 2463 2464 if (width != amdgpu_crtc->cursor_width || 2465 height != amdgpu_crtc->cursor_height || 2466 hot_x != amdgpu_crtc->cursor_hot_x || 2467 hot_y != amdgpu_crtc->cursor_hot_y) { 2468 int x, y; 2469 2470 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2471 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2472 2473 dce_v11_0_cursor_move_locked(crtc, x, y); 2474 2475 amdgpu_crtc->cursor_width = width; 2476 amdgpu_crtc->cursor_height = height; 2477 amdgpu_crtc->cursor_hot_x = hot_x; 2478 amdgpu_crtc->cursor_hot_y = hot_y; 2479 } 2480 2481 dce_v11_0_show_cursor(crtc); 2482 dce_v11_0_lock_cursor(crtc, false); 2483 2484 unpin: 2485 if (amdgpu_crtc->cursor_bo) { 2486 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2487 ret = amdgpu_bo_reserve(aobj, true); 2488 if (likely(ret == 0)) { 2489 amdgpu_bo_unpin(aobj); 2490 amdgpu_bo_unreserve(aobj); 2491 } 2492 drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo); 2493 } 2494 2495 amdgpu_crtc->cursor_bo = obj; 2496 return 0; 2497 } 2498 2499 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc) 2500 { 2501 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2502 2503 if (amdgpu_crtc->cursor_bo) { 2504 dce_v11_0_lock_cursor(crtc, true); 2505 2506 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2507 amdgpu_crtc->cursor_y); 2508 2509 dce_v11_0_show_cursor(crtc); 2510 2511 dce_v11_0_lock_cursor(crtc, false); 2512 } 2513 } 2514 2515 static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2516 u16 *blue, uint32_t size, 2517 struct drm_modeset_acquire_ctx *ctx) 2518 { 2519 dce_v11_0_crtc_load_lut(crtc); 2520 2521 return 0; 2522 } 2523 2524 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc) 2525 { 2526 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2527 2528 drm_crtc_cleanup(crtc); 2529 kfree(amdgpu_crtc); 2530 } 2531 2532 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = { 2533 .cursor_set2 = dce_v11_0_crtc_cursor_set2, 2534 .cursor_move = dce_v11_0_crtc_cursor_move, 2535 .gamma_set = dce_v11_0_crtc_gamma_set, 2536 .set_config = amdgpu_display_crtc_set_config, 2537 .destroy = dce_v11_0_crtc_destroy, 2538 .page_flip_target = amdgpu_display_crtc_page_flip_target, 2539 }; 2540 2541 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2542 { 2543 struct drm_device *dev = crtc->dev; 2544 struct amdgpu_device *adev = dev->dev_private; 2545 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2546 unsigned type; 2547 2548 switch (mode) { 2549 case DRM_MODE_DPMS_ON: 2550 amdgpu_crtc->enabled = true; 2551 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2552 dce_v11_0_vga_enable(crtc, true); 2553 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2554 dce_v11_0_vga_enable(crtc, false); 2555 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2556 type = amdgpu_display_crtc_idx_to_irq_type(adev, 2557 amdgpu_crtc->crtc_id); 2558 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2559 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2560 drm_crtc_vblank_on(crtc); 2561 dce_v11_0_crtc_load_lut(crtc); 2562 break; 2563 case DRM_MODE_DPMS_STANDBY: 2564 case DRM_MODE_DPMS_SUSPEND: 2565 case DRM_MODE_DPMS_OFF: 2566 drm_crtc_vblank_off(crtc); 2567 if (amdgpu_crtc->enabled) { 2568 dce_v11_0_vga_enable(crtc, true); 2569 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2570 dce_v11_0_vga_enable(crtc, false); 2571 } 2572 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2573 amdgpu_crtc->enabled = false; 2574 break; 2575 } 2576 /* adjust pm to dpms */ 2577 amdgpu_pm_compute_clocks(adev); 2578 } 2579 2580 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc) 2581 { 2582 /* disable crtc pair power gating before programming */ 2583 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2584 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2585 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2586 } 2587 2588 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc) 2589 { 2590 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2591 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2592 } 2593 2594 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc) 2595 { 2596 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2597 struct drm_device *dev = crtc->dev; 2598 struct amdgpu_device *adev = dev->dev_private; 2599 struct amdgpu_atom_ss ss; 2600 int i; 2601 2602 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2603 if (crtc->primary->fb) { 2604 int r; 2605 struct amdgpu_bo *abo; 2606 2607 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); 2608 r = amdgpu_bo_reserve(abo, true); 2609 if (unlikely(r)) 2610 DRM_ERROR("failed to reserve abo before unpin\n"); 2611 else { 2612 amdgpu_bo_unpin(abo); 2613 amdgpu_bo_unreserve(abo); 2614 } 2615 } 2616 /* disable the GRPH */ 2617 dce_v11_0_grph_enable(crtc, false); 2618 2619 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2620 2621 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2622 if (adev->mode_info.crtcs[i] && 2623 adev->mode_info.crtcs[i]->enabled && 2624 i != amdgpu_crtc->crtc_id && 2625 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2626 /* one other crtc is using this pll don't turn 2627 * off the pll 2628 */ 2629 goto done; 2630 } 2631 } 2632 2633 switch (amdgpu_crtc->pll_id) { 2634 case ATOM_PPLL0: 2635 case ATOM_PPLL1: 2636 case ATOM_PPLL2: 2637 /* disable the ppll */ 2638 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2639 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2640 break; 2641 case ATOM_COMBOPHY_PLL0: 2642 case ATOM_COMBOPHY_PLL1: 2643 case ATOM_COMBOPHY_PLL2: 2644 case ATOM_COMBOPHY_PLL3: 2645 case ATOM_COMBOPHY_PLL4: 2646 case ATOM_COMBOPHY_PLL5: 2647 /* disable the ppll */ 2648 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id, 2649 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2650 break; 2651 default: 2652 break; 2653 } 2654 done: 2655 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2656 amdgpu_crtc->adjusted_clock = 0; 2657 amdgpu_crtc->encoder = NULL; 2658 amdgpu_crtc->connector = NULL; 2659 } 2660 2661 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc, 2662 struct drm_display_mode *mode, 2663 struct drm_display_mode *adjusted_mode, 2664 int x, int y, struct drm_framebuffer *old_fb) 2665 { 2666 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2667 struct drm_device *dev = crtc->dev; 2668 struct amdgpu_device *adev = dev->dev_private; 2669 2670 if (!amdgpu_crtc->adjusted_clock) 2671 return -EINVAL; 2672 2673 if ((adev->asic_type == CHIP_POLARIS10) || 2674 (adev->asic_type == CHIP_POLARIS11) || 2675 (adev->asic_type == CHIP_POLARIS12) || 2676 (adev->asic_type == CHIP_VEGAM)) { 2677 struct amdgpu_encoder *amdgpu_encoder = 2678 to_amdgpu_encoder(amdgpu_crtc->encoder); 2679 int encoder_mode = 2680 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder); 2681 2682 /* SetPixelClock calculates the plls and ss values now */ 2683 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, 2684 amdgpu_crtc->pll_id, 2685 encoder_mode, amdgpu_encoder->encoder_id, 2686 adjusted_mode->clock, 0, 0, 0, 0, 2687 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss); 2688 } else { 2689 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2690 } 2691 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2692 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2693 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2694 amdgpu_atombios_crtc_scaler_setup(crtc); 2695 dce_v11_0_cursor_reset(crtc); 2696 /* update the hw version fpr dpm */ 2697 amdgpu_crtc->hw_mode = *adjusted_mode; 2698 2699 return 0; 2700 } 2701 2702 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc, 2703 const struct drm_display_mode *mode, 2704 struct drm_display_mode *adjusted_mode) 2705 { 2706 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2707 struct drm_device *dev = crtc->dev; 2708 struct drm_encoder *encoder; 2709 2710 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2711 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2712 if (encoder->crtc == crtc) { 2713 amdgpu_crtc->encoder = encoder; 2714 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2715 break; 2716 } 2717 } 2718 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2719 amdgpu_crtc->encoder = NULL; 2720 amdgpu_crtc->connector = NULL; 2721 return false; 2722 } 2723 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2724 return false; 2725 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2726 return false; 2727 /* pick pll */ 2728 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc); 2729 /* if we can't get a PPLL for a non-DP encoder, fail */ 2730 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2731 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2732 return false; 2733 2734 return true; 2735 } 2736 2737 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2738 struct drm_framebuffer *old_fb) 2739 { 2740 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2741 } 2742 2743 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2744 struct drm_framebuffer *fb, 2745 int x, int y, enum mode_set_atomic state) 2746 { 2747 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1); 2748 } 2749 2750 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = { 2751 .dpms = dce_v11_0_crtc_dpms, 2752 .mode_fixup = dce_v11_0_crtc_mode_fixup, 2753 .mode_set = dce_v11_0_crtc_mode_set, 2754 .mode_set_base = dce_v11_0_crtc_set_base, 2755 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic, 2756 .prepare = dce_v11_0_crtc_prepare, 2757 .commit = dce_v11_0_crtc_commit, 2758 .disable = dce_v11_0_crtc_disable, 2759 }; 2760 2761 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index) 2762 { 2763 struct amdgpu_crtc *amdgpu_crtc; 2764 2765 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2766 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2767 if (amdgpu_crtc == NULL) 2768 return -ENOMEM; 2769 2770 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs); 2771 2772 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2773 amdgpu_crtc->crtc_id = index; 2774 adev->mode_info.crtcs[index] = amdgpu_crtc; 2775 2776 amdgpu_crtc->max_cursor_width = 128; 2777 amdgpu_crtc->max_cursor_height = 128; 2778 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2779 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2780 2781 switch (amdgpu_crtc->crtc_id) { 2782 case 0: 2783 default: 2784 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; 2785 break; 2786 case 1: 2787 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; 2788 break; 2789 case 2: 2790 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; 2791 break; 2792 case 3: 2793 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; 2794 break; 2795 case 4: 2796 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; 2797 break; 2798 case 5: 2799 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; 2800 break; 2801 } 2802 2803 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2804 amdgpu_crtc->adjusted_clock = 0; 2805 amdgpu_crtc->encoder = NULL; 2806 amdgpu_crtc->connector = NULL; 2807 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs); 2808 2809 return 0; 2810 } 2811 2812 static int dce_v11_0_early_init(void *handle) 2813 { 2814 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2815 2816 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg; 2817 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg; 2818 2819 dce_v11_0_set_display_funcs(adev); 2820 2821 adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev); 2822 2823 switch (adev->asic_type) { 2824 case CHIP_CARRIZO: 2825 adev->mode_info.num_hpd = 6; 2826 adev->mode_info.num_dig = 9; 2827 break; 2828 case CHIP_STONEY: 2829 adev->mode_info.num_hpd = 6; 2830 adev->mode_info.num_dig = 9; 2831 break; 2832 case CHIP_POLARIS10: 2833 case CHIP_VEGAM: 2834 adev->mode_info.num_hpd = 6; 2835 adev->mode_info.num_dig = 6; 2836 break; 2837 case CHIP_POLARIS11: 2838 case CHIP_POLARIS12: 2839 adev->mode_info.num_hpd = 5; 2840 adev->mode_info.num_dig = 5; 2841 break; 2842 default: 2843 /* FIXME: not supported yet */ 2844 return -EINVAL; 2845 } 2846 2847 dce_v11_0_set_irq_funcs(adev); 2848 2849 return 0; 2850 } 2851 2852 static int dce_v11_0_sw_init(void *handle) 2853 { 2854 int r, i; 2855 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2856 2857 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2858 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); 2859 if (r) 2860 return r; 2861 } 2862 2863 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) { 2864 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq); 2865 if (r) 2866 return r; 2867 } 2868 2869 /* HPD hotplug */ 2870 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 2871 if (r) 2872 return r; 2873 2874 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; 2875 2876 adev->ddev->mode_config.async_page_flip = true; 2877 2878 adev->ddev->mode_config.max_width = 16384; 2879 adev->ddev->mode_config.max_height = 16384; 2880 2881 adev->ddev->mode_config.preferred_depth = 24; 2882 adev->ddev->mode_config.prefer_shadow = 1; 2883 2884 adev->ddev->mode_config.fb_base = adev->gmc.aper_base; 2885 2886 r = amdgpu_display_modeset_create_props(adev); 2887 if (r) 2888 return r; 2889 2890 adev->ddev->mode_config.max_width = 16384; 2891 adev->ddev->mode_config.max_height = 16384; 2892 2893 2894 /* allocate crtcs */ 2895 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2896 r = dce_v11_0_crtc_init(adev, i); 2897 if (r) 2898 return r; 2899 } 2900 2901 if (amdgpu_atombios_get_connector_info_from_object_table(adev)) 2902 amdgpu_display_print_display_setup(adev->ddev); 2903 else 2904 return -EINVAL; 2905 2906 /* setup afmt */ 2907 r = dce_v11_0_afmt_init(adev); 2908 if (r) 2909 return r; 2910 2911 r = dce_v11_0_audio_init(adev); 2912 if (r) 2913 return r; 2914 2915 drm_kms_helper_poll_init(adev->ddev); 2916 2917 adev->mode_info.mode_config_initialized = true; 2918 return 0; 2919 } 2920 2921 static int dce_v11_0_sw_fini(void *handle) 2922 { 2923 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2924 2925 kfree(adev->mode_info.bios_hardcoded_edid); 2926 2927 drm_kms_helper_poll_fini(adev->ddev); 2928 2929 dce_v11_0_audio_fini(adev); 2930 2931 dce_v11_0_afmt_fini(adev); 2932 2933 drm_mode_config_cleanup(adev->ddev); 2934 adev->mode_info.mode_config_initialized = false; 2935 2936 return 0; 2937 } 2938 2939 static int dce_v11_0_hw_init(void *handle) 2940 { 2941 int i; 2942 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2943 2944 dce_v11_0_init_golden_registers(adev); 2945 2946 /* disable vga render */ 2947 dce_v11_0_set_vga_render_state(adev, false); 2948 /* init dig PHYs, disp eng pll */ 2949 amdgpu_atombios_crtc_powergate_init(adev); 2950 amdgpu_atombios_encoder_init_dig(adev); 2951 if ((adev->asic_type == CHIP_POLARIS10) || 2952 (adev->asic_type == CHIP_POLARIS11) || 2953 (adev->asic_type == CHIP_POLARIS12) || 2954 (adev->asic_type == CHIP_VEGAM)) { 2955 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk, 2956 DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS); 2957 amdgpu_atombios_crtc_set_dce_clock(adev, 0, 2958 DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS); 2959 } else { 2960 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 2961 } 2962 2963 /* initialize hpd */ 2964 dce_v11_0_hpd_init(adev); 2965 2966 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2967 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2968 } 2969 2970 dce_v11_0_pageflip_interrupt_init(adev); 2971 2972 return 0; 2973 } 2974 2975 static int dce_v11_0_hw_fini(void *handle) 2976 { 2977 int i; 2978 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2979 2980 dce_v11_0_hpd_fini(adev); 2981 2982 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2983 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2984 } 2985 2986 dce_v11_0_pageflip_interrupt_fini(adev); 2987 2988 return 0; 2989 } 2990 2991 static int dce_v11_0_suspend(void *handle) 2992 { 2993 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2994 2995 adev->mode_info.bl_level = 2996 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); 2997 2998 return dce_v11_0_hw_fini(handle); 2999 } 3000 3001 static int dce_v11_0_resume(void *handle) 3002 { 3003 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3004 int ret; 3005 3006 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, 3007 adev->mode_info.bl_level); 3008 3009 ret = dce_v11_0_hw_init(handle); 3010 3011 /* turn on the BL */ 3012 if (adev->mode_info.bl_encoder) { 3013 u8 bl_level = amdgpu_display_backlight_get_level(adev, 3014 adev->mode_info.bl_encoder); 3015 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 3016 bl_level); 3017 } 3018 3019 return ret; 3020 } 3021 3022 static bool dce_v11_0_is_idle(void *handle) 3023 { 3024 return true; 3025 } 3026 3027 static int dce_v11_0_wait_for_idle(void *handle) 3028 { 3029 return 0; 3030 } 3031 3032 static int dce_v11_0_soft_reset(void *handle) 3033 { 3034 u32 srbm_soft_reset = 0, tmp; 3035 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3036 3037 if (dce_v11_0_is_display_hung(adev)) 3038 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 3039 3040 if (srbm_soft_reset) { 3041 tmp = RREG32(mmSRBM_SOFT_RESET); 3042 tmp |= srbm_soft_reset; 3043 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 3044 WREG32(mmSRBM_SOFT_RESET, tmp); 3045 tmp = RREG32(mmSRBM_SOFT_RESET); 3046 3047 udelay(50); 3048 3049 tmp &= ~srbm_soft_reset; 3050 WREG32(mmSRBM_SOFT_RESET, tmp); 3051 tmp = RREG32(mmSRBM_SOFT_RESET); 3052 3053 /* Wait a little for things to settle down */ 3054 udelay(50); 3055 } 3056 return 0; 3057 } 3058 3059 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 3060 int crtc, 3061 enum amdgpu_interrupt_state state) 3062 { 3063 u32 lb_interrupt_mask; 3064 3065 if (crtc >= adev->mode_info.num_crtc) { 3066 DRM_DEBUG("invalid crtc %d\n", crtc); 3067 return; 3068 } 3069 3070 switch (state) { 3071 case AMDGPU_IRQ_STATE_DISABLE: 3072 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3073 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3074 VBLANK_INTERRUPT_MASK, 0); 3075 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3076 break; 3077 case AMDGPU_IRQ_STATE_ENABLE: 3078 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3079 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3080 VBLANK_INTERRUPT_MASK, 1); 3081 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3082 break; 3083 default: 3084 break; 3085 } 3086 } 3087 3088 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 3089 int crtc, 3090 enum amdgpu_interrupt_state state) 3091 { 3092 u32 lb_interrupt_mask; 3093 3094 if (crtc >= adev->mode_info.num_crtc) { 3095 DRM_DEBUG("invalid crtc %d\n", crtc); 3096 return; 3097 } 3098 3099 switch (state) { 3100 case AMDGPU_IRQ_STATE_DISABLE: 3101 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3102 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3103 VLINE_INTERRUPT_MASK, 0); 3104 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3105 break; 3106 case AMDGPU_IRQ_STATE_ENABLE: 3107 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3108 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3109 VLINE_INTERRUPT_MASK, 1); 3110 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3111 break; 3112 default: 3113 break; 3114 } 3115 } 3116 3117 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev, 3118 struct amdgpu_irq_src *source, 3119 unsigned hpd, 3120 enum amdgpu_interrupt_state state) 3121 { 3122 u32 tmp; 3123 3124 if (hpd >= adev->mode_info.num_hpd) { 3125 DRM_DEBUG("invalid hdp %d\n", hpd); 3126 return 0; 3127 } 3128 3129 switch (state) { 3130 case AMDGPU_IRQ_STATE_DISABLE: 3131 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3132 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 3133 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3134 break; 3135 case AMDGPU_IRQ_STATE_ENABLE: 3136 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3137 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); 3138 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3139 break; 3140 default: 3141 break; 3142 } 3143 3144 return 0; 3145 } 3146 3147 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev, 3148 struct amdgpu_irq_src *source, 3149 unsigned type, 3150 enum amdgpu_interrupt_state state) 3151 { 3152 switch (type) { 3153 case AMDGPU_CRTC_IRQ_VBLANK1: 3154 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state); 3155 break; 3156 case AMDGPU_CRTC_IRQ_VBLANK2: 3157 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state); 3158 break; 3159 case AMDGPU_CRTC_IRQ_VBLANK3: 3160 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state); 3161 break; 3162 case AMDGPU_CRTC_IRQ_VBLANK4: 3163 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state); 3164 break; 3165 case AMDGPU_CRTC_IRQ_VBLANK5: 3166 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state); 3167 break; 3168 case AMDGPU_CRTC_IRQ_VBLANK6: 3169 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state); 3170 break; 3171 case AMDGPU_CRTC_IRQ_VLINE1: 3172 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state); 3173 break; 3174 case AMDGPU_CRTC_IRQ_VLINE2: 3175 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state); 3176 break; 3177 case AMDGPU_CRTC_IRQ_VLINE3: 3178 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state); 3179 break; 3180 case AMDGPU_CRTC_IRQ_VLINE4: 3181 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state); 3182 break; 3183 case AMDGPU_CRTC_IRQ_VLINE5: 3184 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state); 3185 break; 3186 case AMDGPU_CRTC_IRQ_VLINE6: 3187 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state); 3188 break; 3189 default: 3190 break; 3191 } 3192 return 0; 3193 } 3194 3195 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev, 3196 struct amdgpu_irq_src *src, 3197 unsigned type, 3198 enum amdgpu_interrupt_state state) 3199 { 3200 u32 reg; 3201 3202 if (type >= adev->mode_info.num_crtc) { 3203 DRM_ERROR("invalid pageflip crtc %d\n", type); 3204 return -EINVAL; 3205 } 3206 3207 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 3208 if (state == AMDGPU_IRQ_STATE_DISABLE) 3209 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3210 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3211 else 3212 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3213 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3214 3215 return 0; 3216 } 3217 3218 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev, 3219 struct amdgpu_irq_src *source, 3220 struct amdgpu_iv_entry *entry) 3221 { 3222 unsigned long flags; 3223 unsigned crtc_id; 3224 struct amdgpu_crtc *amdgpu_crtc; 3225 struct amdgpu_flip_work *works; 3226 3227 crtc_id = (entry->src_id - 8) >> 1; 3228 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3229 3230 if (crtc_id >= adev->mode_info.num_crtc) { 3231 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3232 return -EINVAL; 3233 } 3234 3235 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 3236 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3237 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 3238 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3239 3240 /* IRQ could occur when in initial stage */ 3241 if(amdgpu_crtc == NULL) 3242 return 0; 3243 3244 spin_lock_irqsave(&adev->ddev->event_lock, flags); 3245 works = amdgpu_crtc->pflip_works; 3246 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 3247 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3248 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3249 amdgpu_crtc->pflip_status, 3250 AMDGPU_FLIP_SUBMITTED); 3251 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3252 return 0; 3253 } 3254 3255 /* page flip completed. clean up */ 3256 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3257 amdgpu_crtc->pflip_works = NULL; 3258 3259 /* wakeup usersapce */ 3260 if(works->event) 3261 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); 3262 3263 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3264 3265 drm_crtc_vblank_put(&amdgpu_crtc->base); 3266 schedule_work(&works->unpin_work); 3267 3268 return 0; 3269 } 3270 3271 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev, 3272 int hpd) 3273 { 3274 u32 tmp; 3275 3276 if (hpd >= adev->mode_info.num_hpd) { 3277 DRM_DEBUG("invalid hdp %d\n", hpd); 3278 return; 3279 } 3280 3281 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3282 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); 3283 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3284 } 3285 3286 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev, 3287 int crtc) 3288 { 3289 u32 tmp; 3290 3291 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { 3292 DRM_DEBUG("invalid crtc %d\n", crtc); 3293 return; 3294 } 3295 3296 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); 3297 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); 3298 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); 3299 } 3300 3301 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev, 3302 int crtc) 3303 { 3304 u32 tmp; 3305 3306 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { 3307 DRM_DEBUG("invalid crtc %d\n", crtc); 3308 return; 3309 } 3310 3311 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); 3312 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); 3313 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); 3314 } 3315 3316 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev, 3317 struct amdgpu_irq_src *source, 3318 struct amdgpu_iv_entry *entry) 3319 { 3320 unsigned crtc = entry->src_id - 1; 3321 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3322 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, 3323 crtc); 3324 3325 switch (entry->src_data[0]) { 3326 case 0: /* vblank */ 3327 if (disp_int & interrupt_status_offsets[crtc].vblank) 3328 dce_v11_0_crtc_vblank_int_ack(adev, crtc); 3329 else 3330 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3331 3332 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3333 drm_handle_vblank(adev->ddev, crtc); 3334 } 3335 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3336 3337 break; 3338 case 1: /* vline */ 3339 if (disp_int & interrupt_status_offsets[crtc].vline) 3340 dce_v11_0_crtc_vline_int_ack(adev, crtc); 3341 else 3342 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3343 3344 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3345 3346 break; 3347 default: 3348 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3349 break; 3350 } 3351 3352 return 0; 3353 } 3354 3355 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev, 3356 struct amdgpu_irq_src *source, 3357 struct amdgpu_iv_entry *entry) 3358 { 3359 uint32_t disp_int, mask; 3360 unsigned hpd; 3361 3362 if (entry->src_data[0] >= adev->mode_info.num_hpd) { 3363 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3364 return 0; 3365 } 3366 3367 hpd = entry->src_data[0]; 3368 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3369 mask = interrupt_status_offsets[hpd].hpd; 3370 3371 if (disp_int & mask) { 3372 dce_v11_0_hpd_int_ack(adev, hpd); 3373 schedule_work(&adev->hotplug_work); 3374 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3375 } 3376 3377 return 0; 3378 } 3379 3380 static int dce_v11_0_set_clockgating_state(void *handle, 3381 enum amd_clockgating_state state) 3382 { 3383 return 0; 3384 } 3385 3386 static int dce_v11_0_set_powergating_state(void *handle, 3387 enum amd_powergating_state state) 3388 { 3389 return 0; 3390 } 3391 3392 static const struct amd_ip_funcs dce_v11_0_ip_funcs = { 3393 .name = "dce_v11_0", 3394 .early_init = dce_v11_0_early_init, 3395 .late_init = NULL, 3396 .sw_init = dce_v11_0_sw_init, 3397 .sw_fini = dce_v11_0_sw_fini, 3398 .hw_init = dce_v11_0_hw_init, 3399 .hw_fini = dce_v11_0_hw_fini, 3400 .suspend = dce_v11_0_suspend, 3401 .resume = dce_v11_0_resume, 3402 .is_idle = dce_v11_0_is_idle, 3403 .wait_for_idle = dce_v11_0_wait_for_idle, 3404 .soft_reset = dce_v11_0_soft_reset, 3405 .set_clockgating_state = dce_v11_0_set_clockgating_state, 3406 .set_powergating_state = dce_v11_0_set_powergating_state, 3407 }; 3408 3409 static void 3410 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder, 3411 struct drm_display_mode *mode, 3412 struct drm_display_mode *adjusted_mode) 3413 { 3414 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3415 3416 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3417 3418 /* need to call this here rather than in prepare() since we need some crtc info */ 3419 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3420 3421 /* set scaler clears this on some chips */ 3422 dce_v11_0_set_interleave(encoder->crtc, mode); 3423 3424 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 3425 dce_v11_0_afmt_enable(encoder, true); 3426 dce_v11_0_afmt_setmode(encoder, adjusted_mode); 3427 } 3428 } 3429 3430 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder) 3431 { 3432 struct amdgpu_device *adev = encoder->dev->dev_private; 3433 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3434 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3435 3436 if ((amdgpu_encoder->active_device & 3437 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3438 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3439 ENCODER_OBJECT_ID_NONE)) { 3440 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3441 if (dig) { 3442 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder); 3443 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3444 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3445 } 3446 } 3447 3448 amdgpu_atombios_scratch_regs_lock(adev, true); 3449 3450 if (connector) { 3451 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3452 3453 /* select the clock/data port if it uses a router */ 3454 if (amdgpu_connector->router.cd_valid) 3455 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3456 3457 /* turn eDP panel on for mode set */ 3458 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3459 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3460 ATOM_TRANSMITTER_ACTION_POWER_ON); 3461 } 3462 3463 /* this is needed for the pll/ss setup to work correctly in some cases */ 3464 amdgpu_atombios_encoder_set_crtc_source(encoder); 3465 /* set up the FMT blocks */ 3466 dce_v11_0_program_fmt(encoder); 3467 } 3468 3469 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder) 3470 { 3471 struct drm_device *dev = encoder->dev; 3472 struct amdgpu_device *adev = dev->dev_private; 3473 3474 /* need to call this here as we need the crtc set up */ 3475 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3476 amdgpu_atombios_scratch_regs_lock(adev, false); 3477 } 3478 3479 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder) 3480 { 3481 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3482 struct amdgpu_encoder_atom_dig *dig; 3483 3484 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3485 3486 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3487 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 3488 dce_v11_0_afmt_enable(encoder, false); 3489 dig = amdgpu_encoder->enc_priv; 3490 dig->dig_encoder = -1; 3491 } 3492 amdgpu_encoder->active_device = 0; 3493 } 3494 3495 /* these are handled by the primary encoders */ 3496 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder) 3497 { 3498 3499 } 3500 3501 static void dce_v11_0_ext_commit(struct drm_encoder *encoder) 3502 { 3503 3504 } 3505 3506 static void 3507 dce_v11_0_ext_mode_set(struct drm_encoder *encoder, 3508 struct drm_display_mode *mode, 3509 struct drm_display_mode *adjusted_mode) 3510 { 3511 3512 } 3513 3514 static void dce_v11_0_ext_disable(struct drm_encoder *encoder) 3515 { 3516 3517 } 3518 3519 static void 3520 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode) 3521 { 3522 3523 } 3524 3525 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = { 3526 .dpms = dce_v11_0_ext_dpms, 3527 .prepare = dce_v11_0_ext_prepare, 3528 .mode_set = dce_v11_0_ext_mode_set, 3529 .commit = dce_v11_0_ext_commit, 3530 .disable = dce_v11_0_ext_disable, 3531 /* no detect for TMDS/LVDS yet */ 3532 }; 3533 3534 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = { 3535 .dpms = amdgpu_atombios_encoder_dpms, 3536 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3537 .prepare = dce_v11_0_encoder_prepare, 3538 .mode_set = dce_v11_0_encoder_mode_set, 3539 .commit = dce_v11_0_encoder_commit, 3540 .disable = dce_v11_0_encoder_disable, 3541 .detect = amdgpu_atombios_encoder_dig_detect, 3542 }; 3543 3544 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = { 3545 .dpms = amdgpu_atombios_encoder_dpms, 3546 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3547 .prepare = dce_v11_0_encoder_prepare, 3548 .mode_set = dce_v11_0_encoder_mode_set, 3549 .commit = dce_v11_0_encoder_commit, 3550 .detect = amdgpu_atombios_encoder_dac_detect, 3551 }; 3552 3553 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder) 3554 { 3555 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3556 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3557 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3558 kfree(amdgpu_encoder->enc_priv); 3559 drm_encoder_cleanup(encoder); 3560 kfree(amdgpu_encoder); 3561 } 3562 3563 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = { 3564 .destroy = dce_v11_0_encoder_destroy, 3565 }; 3566 3567 static void dce_v11_0_encoder_add(struct amdgpu_device *adev, 3568 uint32_t encoder_enum, 3569 uint32_t supported_device, 3570 u16 caps) 3571 { 3572 struct drm_device *dev = adev->ddev; 3573 struct drm_encoder *encoder; 3574 struct amdgpu_encoder *amdgpu_encoder; 3575 3576 /* see if we already added it */ 3577 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3578 amdgpu_encoder = to_amdgpu_encoder(encoder); 3579 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3580 amdgpu_encoder->devices |= supported_device; 3581 return; 3582 } 3583 3584 } 3585 3586 /* add a new one */ 3587 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3588 if (!amdgpu_encoder) 3589 return; 3590 3591 encoder = &amdgpu_encoder->base; 3592 switch (adev->mode_info.num_crtc) { 3593 case 1: 3594 encoder->possible_crtcs = 0x1; 3595 break; 3596 case 2: 3597 default: 3598 encoder->possible_crtcs = 0x3; 3599 break; 3600 case 3: 3601 encoder->possible_crtcs = 0x7; 3602 break; 3603 case 4: 3604 encoder->possible_crtcs = 0xf; 3605 break; 3606 case 5: 3607 encoder->possible_crtcs = 0x1f; 3608 break; 3609 case 6: 3610 encoder->possible_crtcs = 0x3f; 3611 break; 3612 } 3613 3614 amdgpu_encoder->enc_priv = NULL; 3615 3616 amdgpu_encoder->encoder_enum = encoder_enum; 3617 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3618 amdgpu_encoder->devices = supported_device; 3619 amdgpu_encoder->rmx_type = RMX_OFF; 3620 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3621 amdgpu_encoder->is_ext_encoder = false; 3622 amdgpu_encoder->caps = caps; 3623 3624 switch (amdgpu_encoder->encoder_id) { 3625 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3626 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3627 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3628 DRM_MODE_ENCODER_DAC, NULL); 3629 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs); 3630 break; 3631 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3632 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3633 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3634 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3635 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3636 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3637 amdgpu_encoder->rmx_type = RMX_FULL; 3638 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3639 DRM_MODE_ENCODER_LVDS, NULL); 3640 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3641 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3642 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3643 DRM_MODE_ENCODER_DAC, NULL); 3644 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3645 } else { 3646 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3647 DRM_MODE_ENCODER_TMDS, NULL); 3648 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3649 } 3650 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs); 3651 break; 3652 case ENCODER_OBJECT_ID_SI170B: 3653 case ENCODER_OBJECT_ID_CH7303: 3654 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3655 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3656 case ENCODER_OBJECT_ID_TITFP513: 3657 case ENCODER_OBJECT_ID_VT1623: 3658 case ENCODER_OBJECT_ID_HDMI_SI1930: 3659 case ENCODER_OBJECT_ID_TRAVIS: 3660 case ENCODER_OBJECT_ID_NUTMEG: 3661 /* these are handled by the primary encoders */ 3662 amdgpu_encoder->is_ext_encoder = true; 3663 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3664 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3665 DRM_MODE_ENCODER_LVDS, NULL); 3666 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3667 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3668 DRM_MODE_ENCODER_DAC, NULL); 3669 else 3670 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3671 DRM_MODE_ENCODER_TMDS, NULL); 3672 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs); 3673 break; 3674 } 3675 } 3676 3677 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = { 3678 .bandwidth_update = &dce_v11_0_bandwidth_update, 3679 .vblank_get_counter = &dce_v11_0_vblank_get_counter, 3680 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3681 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3682 .hpd_sense = &dce_v11_0_hpd_sense, 3683 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity, 3684 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg, 3685 .page_flip = &dce_v11_0_page_flip, 3686 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos, 3687 .add_encoder = &dce_v11_0_encoder_add, 3688 .add_connector = &amdgpu_connector_add, 3689 }; 3690 3691 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev) 3692 { 3693 if (adev->mode_info.funcs == NULL) 3694 adev->mode_info.funcs = &dce_v11_0_display_funcs; 3695 } 3696 3697 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = { 3698 .set = dce_v11_0_set_crtc_irq_state, 3699 .process = dce_v11_0_crtc_irq, 3700 }; 3701 3702 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = { 3703 .set = dce_v11_0_set_pageflip_irq_state, 3704 .process = dce_v11_0_pageflip_irq, 3705 }; 3706 3707 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = { 3708 .set = dce_v11_0_set_hpd_irq_state, 3709 .process = dce_v11_0_hpd_irq, 3710 }; 3711 3712 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev) 3713 { 3714 if (adev->mode_info.num_crtc > 0) 3715 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; 3716 else 3717 adev->crtc_irq.num_types = 0; 3718 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs; 3719 3720 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; 3721 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs; 3722 3723 adev->hpd_irq.num_types = adev->mode_info.num_hpd; 3724 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs; 3725 } 3726 3727 const struct amdgpu_ip_block_version dce_v11_0_ip_block = 3728 { 3729 .type = AMD_IP_BLOCK_TYPE_DCE, 3730 .major = 11, 3731 .minor = 0, 3732 .rev = 0, 3733 .funcs = &dce_v11_0_ip_funcs, 3734 }; 3735 3736 const struct amdgpu_ip_block_version dce_v11_2_ip_block = 3737 { 3738 .type = AMD_IP_BLOCK_TYPE_DCE, 3739 .major = 11, 3740 .minor = 2, 3741 .rev = 0, 3742 .funcs = &dce_v11_0_ip_funcs, 3743 }; 3744