1*b843c749SSergey Zigachev /*
2*b843c749SSergey Zigachev * Copyright 2018 Advanced Micro Devices, Inc.
3*b843c749SSergey Zigachev *
4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a
5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"),
6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation
7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the
9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions:
10*b843c749SSergey Zigachev *
11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in
12*b843c749SSergey Zigachev * all copies or substantial portions of the Software.
13*b843c749SSergey Zigachev *
14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE.
21*b843c749SSergey Zigachev *
22*b843c749SSergey Zigachev */
23*b843c749SSergey Zigachev #include "amdgpu.h"
24*b843c749SSergey Zigachev #include "df_v1_7.h"
25*b843c749SSergey Zigachev
26*b843c749SSergey Zigachev #include "df/df_1_7_default.h"
27*b843c749SSergey Zigachev #include "df/df_1_7_offset.h"
28*b843c749SSergey Zigachev #include "df/df_1_7_sh_mask.h"
29*b843c749SSergey Zigachev
30*b843c749SSergey Zigachev static u32 df_v1_7_channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
31*b843c749SSergey Zigachev
df_v1_7_init(struct amdgpu_device * adev)32*b843c749SSergey Zigachev static void df_v1_7_init (struct amdgpu_device *adev)
33*b843c749SSergey Zigachev {
34*b843c749SSergey Zigachev }
35*b843c749SSergey Zigachev
df_v1_7_enable_broadcast_mode(struct amdgpu_device * adev,bool enable)36*b843c749SSergey Zigachev static void df_v1_7_enable_broadcast_mode(struct amdgpu_device *adev,
37*b843c749SSergey Zigachev bool enable)
38*b843c749SSergey Zigachev {
39*b843c749SSergey Zigachev u32 tmp;
40*b843c749SSergey Zigachev
41*b843c749SSergey Zigachev if (enable) {
42*b843c749SSergey Zigachev tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);
43*b843c749SSergey Zigachev tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
44*b843c749SSergey Zigachev WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);
45*b843c749SSergey Zigachev } else
46*b843c749SSergey Zigachev WREG32_SOC15(DF, 0, mmFabricConfigAccessControl,
47*b843c749SSergey Zigachev mmFabricConfigAccessControl_DEFAULT);
48*b843c749SSergey Zigachev }
49*b843c749SSergey Zigachev
df_v1_7_get_fb_channel_number(struct amdgpu_device * adev)50*b843c749SSergey Zigachev static u32 df_v1_7_get_fb_channel_number(struct amdgpu_device *adev)
51*b843c749SSergey Zigachev {
52*b843c749SSergey Zigachev u32 tmp;
53*b843c749SSergey Zigachev
54*b843c749SSergey Zigachev tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
55*b843c749SSergey Zigachev tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
56*b843c749SSergey Zigachev tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
57*b843c749SSergey Zigachev
58*b843c749SSergey Zigachev return tmp;
59*b843c749SSergey Zigachev }
60*b843c749SSergey Zigachev
df_v1_7_get_hbm_channel_number(struct amdgpu_device * adev)61*b843c749SSergey Zigachev static u32 df_v1_7_get_hbm_channel_number(struct amdgpu_device *adev)
62*b843c749SSergey Zigachev {
63*b843c749SSergey Zigachev int fb_channel_number;
64*b843c749SSergey Zigachev
65*b843c749SSergey Zigachev fb_channel_number = adev->df_funcs->get_fb_channel_number(adev);
66*b843c749SSergey Zigachev
67*b843c749SSergey Zigachev return df_v1_7_channel_number[fb_channel_number];
68*b843c749SSergey Zigachev }
69*b843c749SSergey Zigachev
df_v1_7_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)70*b843c749SSergey Zigachev static void df_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,
71*b843c749SSergey Zigachev bool enable)
72*b843c749SSergey Zigachev {
73*b843c749SSergey Zigachev u32 tmp;
74*b843c749SSergey Zigachev
75*b843c749SSergey Zigachev /* Put DF on broadcast mode */
76*b843c749SSergey Zigachev adev->df_funcs->enable_broadcast_mode(adev, true);
77*b843c749SSergey Zigachev
78*b843c749SSergey Zigachev if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
79*b843c749SSergey Zigachev tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
80*b843c749SSergey Zigachev tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
81*b843c749SSergey Zigachev tmp |= DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY;
82*b843c749SSergey Zigachev WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
83*b843c749SSergey Zigachev } else {
84*b843c749SSergey Zigachev tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
85*b843c749SSergey Zigachev tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
86*b843c749SSergey Zigachev tmp |= DF_V1_7_MGCG_DISABLE;
87*b843c749SSergey Zigachev WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
88*b843c749SSergey Zigachev }
89*b843c749SSergey Zigachev
90*b843c749SSergey Zigachev /* Exit boradcast mode */
91*b843c749SSergey Zigachev adev->df_funcs->enable_broadcast_mode(adev, false);
92*b843c749SSergey Zigachev }
93*b843c749SSergey Zigachev
df_v1_7_get_clockgating_state(struct amdgpu_device * adev,u32 * flags)94*b843c749SSergey Zigachev static void df_v1_7_get_clockgating_state(struct amdgpu_device *adev,
95*b843c749SSergey Zigachev u32 *flags)
96*b843c749SSergey Zigachev {
97*b843c749SSergey Zigachev u32 tmp;
98*b843c749SSergey Zigachev
99*b843c749SSergey Zigachev /* AMD_CG_SUPPORT_DF_MGCG */
100*b843c749SSergey Zigachev tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
101*b843c749SSergey Zigachev if (tmp & DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY)
102*b843c749SSergey Zigachev *flags |= AMD_CG_SUPPORT_DF_MGCG;
103*b843c749SSergey Zigachev }
104*b843c749SSergey Zigachev
df_v1_7_enable_ecc_force_par_wr_rmw(struct amdgpu_device * adev,bool enable)105*b843c749SSergey Zigachev static void df_v1_7_enable_ecc_force_par_wr_rmw(struct amdgpu_device *adev,
106*b843c749SSergey Zigachev bool enable)
107*b843c749SSergey Zigachev {
108*b843c749SSergey Zigachev WREG32_FIELD15(DF, 0, DF_CS_AON0_CoherentSlaveModeCtrlA0,
109*b843c749SSergey Zigachev ForceParWrRMW, enable);
110*b843c749SSergey Zigachev }
111*b843c749SSergey Zigachev
112*b843c749SSergey Zigachev const struct amdgpu_df_funcs df_v1_7_funcs = {
113*b843c749SSergey Zigachev .init = df_v1_7_init,
114*b843c749SSergey Zigachev .enable_broadcast_mode = df_v1_7_enable_broadcast_mode,
115*b843c749SSergey Zigachev .get_fb_channel_number = df_v1_7_get_fb_channel_number,
116*b843c749SSergey Zigachev .get_hbm_channel_number = df_v1_7_get_hbm_channel_number,
117*b843c749SSergey Zigachev .update_medium_grain_clock_gating = df_v1_7_update_medium_grain_clock_gating,
118*b843c749SSergey Zigachev .get_clockgating_state = df_v1_7_get_clockgating_state,
119*b843c749SSergey Zigachev .enable_ecc_force_par_wr_rmw = df_v1_7_enable_ecc_force_par_wr_rmw,
120*b843c749SSergey Zigachev };
121