1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "gfxhub_v1_0.h" 25 26 #include "gc/gc_9_0_offset.h" 27 #include "gc/gc_9_0_sh_mask.h" 28 #include "gc/gc_9_0_default.h" 29 #include "vega10_enum.h" 30 31 #include "soc15_common.h" 32 33 u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev) 34 { 35 return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24; 36 } 37 38 static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev) 39 { 40 uint64_t value; 41 42 BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL)); 43 value = adev->gart.table_addr - adev->gmc.vram_start 44 + adev->vm_manager.vram_base_offset; 45 value &= 0x0000FFFFFFFFF000ULL; 46 value |= 0x1; /*valid bit*/ 47 48 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 49 lower_32_bits(value)); 50 51 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 52 upper_32_bits(value)); 53 } 54 55 static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev) 56 { 57 gfxhub_v1_0_init_gart_pt_regs(adev); 58 59 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 60 (u32)(adev->gmc.gart_start >> 12)); 61 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 62 (u32)(adev->gmc.gart_start >> 44)); 63 64 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 65 (u32)(adev->gmc.gart_end >> 12)); 66 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 67 (u32)(adev->gmc.gart_end >> 44)); 68 } 69 70 static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 71 { 72 uint64_t value; 73 74 /* Disable AGP. */ 75 WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0); 76 WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0); 77 WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFFFF); 78 79 /* Program the system aperture low logical page number. */ 80 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 81 adev->gmc.vram_start >> 18); 82 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 83 adev->gmc.vram_end >> 18); 84 85 /* Set default page address. */ 86 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start 87 + adev->vm_manager.vram_base_offset; 88 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 89 (u32)(value >> 12)); 90 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 91 (u32)(value >> 44)); 92 93 /* Program "protection fault". */ 94 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 95 (u32)(adev->dummy_page_addr >> 12)); 96 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 97 (u32)((u64)adev->dummy_page_addr >> 44)); 98 99 WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2, 100 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 101 } 102 103 static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) 104 { 105 uint32_t tmp; 106 107 /* Setup TLB control */ 108 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); 109 110 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 111 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 112 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 113 ENABLE_ADVANCED_DRIVER_MODEL, 1); 114 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 115 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 116 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 117 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 118 MTYPE, MTYPE_UC);/* XXX for emulation. */ 119 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); 120 121 WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); 122 } 123 124 static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 125 { 126 uint32_t tmp; 127 128 /* Setup L2 cache */ 129 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL); 130 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 131 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 132 /* XXX for emulation, Refer to closed source code.*/ 133 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 134 0); 135 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1); 136 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 137 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 138 WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp); 139 140 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2); 141 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 142 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 143 WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp); 144 145 tmp = mmVM_L2_CNTL3_DEFAULT; 146 if (adev->gmc.translate_further) { 147 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); 148 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 149 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 150 } else { 151 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); 152 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 153 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 154 } 155 WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp); 156 157 tmp = mmVM_L2_CNTL4_DEFAULT; 158 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 159 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 160 WREG32_SOC15(GC, 0, mmVM_L2_CNTL4, tmp); 161 } 162 163 static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev) 164 { 165 uint32_t tmp; 166 167 tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL); 168 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 169 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 170 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp); 171 } 172 173 static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev) 174 { 175 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 176 0XFFFFFFFF); 177 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 178 0x0000000F); 179 180 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 181 0); 182 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 183 0); 184 185 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); 186 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); 187 188 } 189 190 static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) 191 { 192 unsigned num_level, block_size; 193 uint32_t tmp; 194 int i; 195 196 num_level = adev->vm_manager.num_level; 197 block_size = adev->vm_manager.block_size; 198 if (adev->gmc.translate_further) 199 num_level -= 1; 200 else 201 block_size -= 9; 202 203 for (i = 0; i <= 14; i++) { 204 tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i); 205 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 206 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 207 num_level); 208 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 209 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 210 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 211 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 212 1); 213 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 214 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 215 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 216 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 217 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 218 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 219 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 220 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 221 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 222 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 223 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 224 PAGE_TABLE_BLOCK_SIZE, 225 block_size); 226 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 227 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 228 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 229 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp); 230 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); 231 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); 232 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2, 233 lower_32_bits(adev->vm_manager.max_pfn - 1)); 234 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2, 235 upper_32_bits(adev->vm_manager.max_pfn - 1)); 236 } 237 } 238 239 static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev) 240 { 241 unsigned i; 242 243 for (i = 0 ; i < 18; ++i) { 244 WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 245 2 * i, 0xffffffff); 246 WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 247 2 * i, 0x1f); 248 } 249 } 250 251 int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) 252 { 253 if (amdgpu_sriov_vf(adev)) { 254 /* 255 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 256 * VF copy registers so vbios post doesn't program them, for 257 * SRIOV driver need to program them 258 */ 259 WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, 260 adev->gmc.vram_start >> 24); 261 WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, 262 adev->gmc.vram_end >> 24); 263 } 264 265 /* GART Enable. */ 266 gfxhub_v1_0_init_gart_aperture_regs(adev); 267 gfxhub_v1_0_init_system_aperture_regs(adev); 268 gfxhub_v1_0_init_tlb_regs(adev); 269 gfxhub_v1_0_init_cache_regs(adev); 270 271 gfxhub_v1_0_enable_system_domain(adev); 272 gfxhub_v1_0_disable_identity_aperture(adev); 273 gfxhub_v1_0_setup_vmid_config(adev); 274 gfxhub_v1_0_program_invalidation(adev); 275 276 return 0; 277 } 278 279 void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev) 280 { 281 u32 tmp; 282 u32 i; 283 284 /* Disable all tables */ 285 for (i = 0; i < 16; i++) 286 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL, i, 0); 287 288 /* Setup TLB control */ 289 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); 290 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 291 tmp = REG_SET_FIELD(tmp, 292 MC_VM_MX_L1_TLB_CNTL, 293 ENABLE_ADVANCED_DRIVER_MODEL, 294 0); 295 WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); 296 297 /* Setup L2 cache */ 298 WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 299 WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0); 300 } 301 302 /** 303 * gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling 304 * 305 * @adev: amdgpu_device pointer 306 * @value: true redirects VM faults to the default page 307 */ 308 void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, 309 bool value) 310 { 311 u32 tmp; 312 tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); 313 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 314 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 315 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 316 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 317 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 318 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 319 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 320 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 321 tmp = REG_SET_FIELD(tmp, 322 VM_L2_PROTECTION_FAULT_CNTL, 323 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 324 value); 325 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 326 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 327 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 328 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 329 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 330 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 331 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 332 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 333 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 334 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 335 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 336 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 337 if (!value) { 338 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 339 CRASH_ON_NO_RETRY_FAULT, 1); 340 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 341 CRASH_ON_RETRY_FAULT, 1); 342 } 343 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp); 344 } 345 346 void gfxhub_v1_0_init(struct amdgpu_device *adev) 347 { 348 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB]; 349 350 hub->ctx0_ptb_addr_lo32 = 351 SOC15_REG_OFFSET(GC, 0, 352 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 353 hub->ctx0_ptb_addr_hi32 = 354 SOC15_REG_OFFSET(GC, 0, 355 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 356 hub->vm_inv_eng0_req = 357 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ); 358 hub->vm_inv_eng0_ack = 359 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK); 360 hub->vm_context0_cntl = 361 SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL); 362 hub->vm_l2_pro_fault_status = 363 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS); 364 hub->vm_l2_pro_fault_cntl = 365 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); 366 } 367