1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <drm/drmP.h> 25 #include <drm/drm_cache.h> 26 #include "amdgpu.h" 27 #include "gmc_v8_0.h" 28 #include "amdgpu_ucode.h" 29 #include "amdgpu_amdkfd.h" 30 31 #include "gmc/gmc_8_1_d.h" 32 #include "gmc/gmc_8_1_sh_mask.h" 33 34 #include "bif/bif_5_0_d.h" 35 #include "bif/bif_5_0_sh_mask.h" 36 37 #include "oss/oss_3_0_d.h" 38 #include "oss/oss_3_0_sh_mask.h" 39 40 #include "dce/dce_10_0_d.h" 41 #include "dce/dce_10_0_sh_mask.h" 42 43 #include "vid.h" 44 #include "vi.h" 45 46 #include "amdgpu_atombios.h" 47 48 #include "ivsrcid/ivsrcid_vislands30.h" 49 50 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev); 51 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); 52 static int gmc_v8_0_wait_for_idle(void *handle); 53 54 MODULE_FIRMWARE("amdgpufw_tonga_mc"); 55 MODULE_FIRMWARE("amdgpufw_polaris11_mc"); 56 MODULE_FIRMWARE("amdgpufw_polaris10_mc"); 57 MODULE_FIRMWARE("amdgpufw_polaris12_mc"); 58 MODULE_FIRMWARE("amdgpufw_polaris11_k_mc"); 59 MODULE_FIRMWARE("amdgpufw_polaris10_k_mc"); 60 MODULE_FIRMWARE("amdgpufw_polaris12_k_mc"); 61 62 static const u32 golden_settings_tonga_a11[] = 63 { 64 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 65 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028, 66 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991, 67 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 68 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 69 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 70 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 71 }; 72 73 static const u32 tonga_mgcg_cgcg_init[] = 74 { 75 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 76 }; 77 78 static const u32 golden_settings_fiji_a10[] = 79 { 80 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 81 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 82 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 83 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 84 }; 85 86 static const u32 fiji_mgcg_cgcg_init[] = 87 { 88 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 89 }; 90 91 static const u32 golden_settings_polaris11_a11[] = 92 { 93 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 94 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 95 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 96 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 97 }; 98 99 static const u32 golden_settings_polaris10_a11[] = 100 { 101 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 102 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 103 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 104 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 105 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 106 }; 107 108 static const u32 cz_mgcg_cgcg_init[] = 109 { 110 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 111 }; 112 113 static const u32 stoney_mgcg_cgcg_init[] = 114 { 115 mmATC_MISC_CG, 0xffffffff, 0x000c0200, 116 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 117 }; 118 119 static const u32 golden_settings_stoney_common[] = 120 { 121 mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004, 122 mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000 123 }; 124 125 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) 126 { 127 switch (adev->asic_type) { 128 case CHIP_FIJI: 129 amdgpu_device_program_register_sequence(adev, 130 fiji_mgcg_cgcg_init, 131 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 132 amdgpu_device_program_register_sequence(adev, 133 golden_settings_fiji_a10, 134 ARRAY_SIZE(golden_settings_fiji_a10)); 135 break; 136 case CHIP_TONGA: 137 amdgpu_device_program_register_sequence(adev, 138 tonga_mgcg_cgcg_init, 139 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 140 amdgpu_device_program_register_sequence(adev, 141 golden_settings_tonga_a11, 142 ARRAY_SIZE(golden_settings_tonga_a11)); 143 break; 144 case CHIP_POLARIS11: 145 case CHIP_POLARIS12: 146 case CHIP_VEGAM: 147 amdgpu_device_program_register_sequence(adev, 148 golden_settings_polaris11_a11, 149 ARRAY_SIZE(golden_settings_polaris11_a11)); 150 break; 151 case CHIP_POLARIS10: 152 amdgpu_device_program_register_sequence(adev, 153 golden_settings_polaris10_a11, 154 ARRAY_SIZE(golden_settings_polaris10_a11)); 155 break; 156 case CHIP_CARRIZO: 157 amdgpu_device_program_register_sequence(adev, 158 cz_mgcg_cgcg_init, 159 ARRAY_SIZE(cz_mgcg_cgcg_init)); 160 break; 161 case CHIP_STONEY: 162 amdgpu_device_program_register_sequence(adev, 163 stoney_mgcg_cgcg_init, 164 ARRAY_SIZE(stoney_mgcg_cgcg_init)); 165 amdgpu_device_program_register_sequence(adev, 166 golden_settings_stoney_common, 167 ARRAY_SIZE(golden_settings_stoney_common)); 168 break; 169 default: 170 break; 171 } 172 } 173 174 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev) 175 { 176 u32 blackout; 177 178 gmc_v8_0_wait_for_idle(adev); 179 180 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 181 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 182 /* Block CPU access */ 183 WREG32(mmBIF_FB_EN, 0); 184 /* blackout the MC */ 185 blackout = REG_SET_FIELD(blackout, 186 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1); 187 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); 188 } 189 /* wait for the MC to settle */ 190 udelay(100); 191 } 192 193 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev) 194 { 195 u32 tmp; 196 197 /* unblackout the MC */ 198 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 199 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 200 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 201 /* allow CPU access */ 202 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 203 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 204 WREG32(mmBIF_FB_EN, tmp); 205 } 206 207 /** 208 * gmc_v8_0_init_microcode - load ucode images from disk 209 * 210 * @adev: amdgpu_device pointer 211 * 212 * Use the firmware interface to load the ucode images into 213 * the driver (not loaded into hw). 214 * Returns 0 on success, error on failure. 215 */ 216 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) 217 { 218 const char *chip_name; 219 char fw_name[30]; 220 int err; 221 222 DRM_DEBUG("\n"); 223 224 switch (adev->asic_type) { 225 case CHIP_TONGA: 226 chip_name = "tonga"; 227 break; 228 case CHIP_POLARIS11: 229 if (((adev->pdev->device == 0x67ef) && 230 ((adev->pdev->revision == 0xe0) || 231 (adev->pdev->revision == 0xe5))) || 232 ((adev->pdev->device == 0x67ff) && 233 ((adev->pdev->revision == 0xcf) || 234 (adev->pdev->revision == 0xef) || 235 (adev->pdev->revision == 0xff)))) 236 chip_name = "polaris11_k"; 237 else if ((adev->pdev->device == 0x67ef) && 238 (adev->pdev->revision == 0xe2)) 239 chip_name = "polaris11_k"; 240 else 241 chip_name = "polaris11"; 242 break; 243 case CHIP_POLARIS10: 244 if ((adev->pdev->device == 0x67df) && 245 ((adev->pdev->revision == 0xe1) || 246 (adev->pdev->revision == 0xf7))) 247 chip_name = "polaris10_k"; 248 else 249 chip_name = "polaris10"; 250 break; 251 case CHIP_POLARIS12: 252 if (((adev->pdev->device == 0x6987) && 253 ((adev->pdev->revision == 0xc0) || 254 (adev->pdev->revision == 0xc3))) || 255 ((adev->pdev->device == 0x6981) && 256 ((adev->pdev->revision == 0x00) || 257 (adev->pdev->revision == 0x01) || 258 (adev->pdev->revision == 0x10)))) 259 chip_name = "polaris12_k"; 260 else 261 chip_name = "polaris12"; 262 break; 263 case CHIP_FIJI: 264 case CHIP_CARRIZO: 265 case CHIP_STONEY: 266 case CHIP_VEGAM: 267 return 0; 268 default: BUG(); 269 } 270 271 snprintf(fw_name, sizeof(fw_name), "amdgpufw_%s_mc", chip_name); 272 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); 273 if (err) 274 goto out; 275 err = amdgpu_ucode_validate(adev->gmc.fw); 276 277 out: 278 if (err) { 279 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name); 280 release_firmware(adev->gmc.fw); 281 adev->gmc.fw = NULL; 282 } 283 return err; 284 } 285 286 /** 287 * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw 288 * 289 * @adev: amdgpu_device pointer 290 * 291 * Load the GDDR MC ucode into the hw (CIK). 292 * Returns 0 on success, error on failure. 293 */ 294 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev) 295 { 296 const struct mc_firmware_header_v1_0 *hdr; 297 const __le32 *fw_data = NULL; 298 const __le32 *io_mc_regs = NULL; 299 u32 running; 300 int i, ucode_size, regs_size; 301 302 /* Skip MC ucode loading on SR-IOV capable boards. 303 * vbios does this for us in asic_init in that case. 304 * Skip MC ucode loading on VF, because hypervisor will do that 305 * for this adaptor. 306 */ 307 if (amdgpu_sriov_bios(adev)) 308 return 0; 309 310 if (!adev->gmc.fw) 311 return -EINVAL; 312 313 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 314 amdgpu_ucode_print_mc_hdr(&hdr->header); 315 316 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 317 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 318 io_mc_regs = (const __le32 *) 319 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 320 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 321 fw_data = (const __le32 *) 322 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 323 324 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 325 326 if (running == 0) { 327 /* reset the engine and set to writable */ 328 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 329 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 330 331 /* load mc io regs */ 332 for (i = 0; i < regs_size; i++) { 333 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 334 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 335 } 336 /* load the MC ucode */ 337 for (i = 0; i < ucode_size; i++) 338 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 339 340 /* put the engine back into the active state */ 341 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 342 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 343 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 344 345 /* wait for training to complete */ 346 for (i = 0; i < adev->usec_timeout; i++) { 347 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 348 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 349 break; 350 udelay(1); 351 } 352 for (i = 0; i < adev->usec_timeout; i++) { 353 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 354 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 355 break; 356 udelay(1); 357 } 358 } 359 360 return 0; 361 } 362 363 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev) 364 { 365 const struct mc_firmware_header_v1_0 *hdr; 366 const __le32 *fw_data = NULL; 367 const __le32 *io_mc_regs = NULL; 368 u32 data; 369 int i, ucode_size, regs_size; 370 371 /* Skip MC ucode loading on SR-IOV capable boards. 372 * vbios does this for us in asic_init in that case. 373 * Skip MC ucode loading on VF, because hypervisor will do that 374 * for this adaptor. 375 */ 376 if (amdgpu_sriov_bios(adev)) 377 return 0; 378 379 if (!adev->gmc.fw) 380 return -EINVAL; 381 382 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 383 amdgpu_ucode_print_mc_hdr(&hdr->header); 384 385 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 386 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 387 io_mc_regs = (const __le32 *) 388 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 389 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 390 fw_data = (const __le32 *) 391 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 392 393 data = RREG32(mmMC_SEQ_MISC0); 394 data &= ~(0x40); 395 WREG32(mmMC_SEQ_MISC0, data); 396 397 /* load mc io regs */ 398 for (i = 0; i < regs_size; i++) { 399 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 400 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 401 } 402 403 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 404 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 405 406 /* load the MC ucode */ 407 for (i = 0; i < ucode_size; i++) 408 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 409 410 /* put the engine back into the active state */ 411 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 412 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 413 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 414 415 /* wait for training to complete */ 416 for (i = 0; i < adev->usec_timeout; i++) { 417 data = RREG32(mmMC_SEQ_MISC0); 418 if (data & 0x80) 419 break; 420 udelay(1); 421 } 422 423 return 0; 424 } 425 426 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, 427 struct amdgpu_gmc *mc) 428 { 429 u64 base = 0; 430 431 if (!amdgpu_sriov_vf(adev)) 432 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 433 base <<= 24; 434 435 amdgpu_device_vram_location(adev, &adev->gmc, base); 436 amdgpu_device_gart_location(adev, mc); 437 } 438 439 /** 440 * gmc_v8_0_mc_program - program the GPU memory controller 441 * 442 * @adev: amdgpu_device pointer 443 * 444 * Set the location of vram, gart, and AGP in the GPU's 445 * physical address space (CIK). 446 */ 447 static void gmc_v8_0_mc_program(struct amdgpu_device *adev) 448 { 449 u32 tmp; 450 int i, j; 451 452 /* Initialize HDP */ 453 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 454 WREG32((0xb05 + j), 0x00000000); 455 WREG32((0xb06 + j), 0x00000000); 456 WREG32((0xb07 + j), 0x00000000); 457 WREG32((0xb08 + j), 0x00000000); 458 WREG32((0xb09 + j), 0x00000000); 459 } 460 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 461 462 if (gmc_v8_0_wait_for_idle((void *)adev)) { 463 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 464 } 465 if (adev->mode_info.num_crtc) { 466 /* Lockout access through VGA aperture*/ 467 tmp = RREG32(mmVGA_HDP_CONTROL); 468 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 469 WREG32(mmVGA_HDP_CONTROL, tmp); 470 471 /* disable VGA render */ 472 tmp = RREG32(mmVGA_RENDER_CONTROL); 473 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 474 WREG32(mmVGA_RENDER_CONTROL, tmp); 475 } 476 /* Update configuration */ 477 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 478 adev->gmc.vram_start >> 12); 479 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 480 adev->gmc.vram_end >> 12); 481 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 482 adev->vram_scratch.gpu_addr >> 12); 483 484 if (amdgpu_sriov_vf(adev)) { 485 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16; 486 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF); 487 WREG32(mmMC_VM_FB_LOCATION, tmp); 488 /* XXX double check these! */ 489 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); 490 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 491 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); 492 } 493 494 WREG32(mmMC_VM_AGP_BASE, 0); 495 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 496 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 497 if (gmc_v8_0_wait_for_idle((void *)adev)) { 498 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 499 } 500 501 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 502 503 tmp = RREG32(mmHDP_MISC_CNTL); 504 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 505 WREG32(mmHDP_MISC_CNTL, tmp); 506 507 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 508 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 509 } 510 511 /** 512 * gmc_v8_0_mc_init - initialize the memory controller driver params 513 * 514 * @adev: amdgpu_device pointer 515 * 516 * Look up the amount of vram, vram width, and decide how to place 517 * vram and gart within the GPU's physical address space (CIK). 518 * Returns 0 for success. 519 */ 520 static int gmc_v8_0_mc_init(struct amdgpu_device *adev) 521 { 522 int r; 523 524 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); 525 if (!adev->gmc.vram_width) { 526 u32 tmp; 527 int chansize, numchan; 528 529 /* Get VRAM informations */ 530 tmp = RREG32(mmMC_ARB_RAMCFG); 531 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { 532 chansize = 64; 533 } else { 534 chansize = 32; 535 } 536 tmp = RREG32(mmMC_SHARED_CHMAP); 537 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 538 case 0: 539 default: 540 numchan = 1; 541 break; 542 case 1: 543 numchan = 2; 544 break; 545 case 2: 546 numchan = 4; 547 break; 548 case 3: 549 numchan = 8; 550 break; 551 case 4: 552 numchan = 3; 553 break; 554 case 5: 555 numchan = 6; 556 break; 557 case 6: 558 numchan = 10; 559 break; 560 case 7: 561 numchan = 12; 562 break; 563 case 8: 564 numchan = 16; 565 break; 566 } 567 adev->gmc.vram_width = numchan * chansize; 568 } 569 /* size in MB on si */ 570 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 571 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 572 573 if (!(adev->flags & AMD_IS_APU)) { 574 r = amdgpu_device_resize_fb_bar(adev); 575 if (r) 576 return r; 577 } 578 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 579 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 580 581 #ifdef CONFIG_X86_64 582 if (adev->flags & AMD_IS_APU) { 583 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 584 adev->gmc.aper_size = adev->gmc.real_vram_size; 585 } 586 #endif 587 588 /* In case the PCI BAR is larger than the actual amount of vram */ 589 adev->gmc.visible_vram_size = adev->gmc.aper_size; 590 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 591 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 592 593 /* set the gart size */ 594 if (amdgpu_gart_size == -1) { 595 switch (adev->asic_type) { 596 case CHIP_POLARIS10: /* all engines support GPUVM */ 597 case CHIP_POLARIS11: /* all engines support GPUVM */ 598 case CHIP_POLARIS12: /* all engines support GPUVM */ 599 case CHIP_VEGAM: /* all engines support GPUVM */ 600 default: 601 adev->gmc.gart_size = 256ULL << 20; 602 break; 603 case CHIP_TONGA: /* UVD, VCE do not support GPUVM */ 604 case CHIP_FIJI: /* UVD, VCE do not support GPUVM */ 605 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */ 606 case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */ 607 adev->gmc.gart_size = 1024ULL << 20; 608 break; 609 } 610 } else { 611 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 612 } 613 614 gmc_v8_0_vram_gtt_location(adev, &adev->gmc); 615 616 return 0; 617 } 618 619 /* 620 * GART 621 * VMID 0 is the physical GPU addresses as used by the kernel. 622 * VMIDs 1-15 are used for userspace clients and are handled 623 * by the amdgpu vm/hsa code. 624 */ 625 626 /** 627 * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback 628 * 629 * @adev: amdgpu_device pointer 630 * @vmid: vm instance to flush 631 * 632 * Flush the TLB for the requested page table (CIK). 633 */ 634 static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, 635 uint32_t vmid) 636 { 637 /* bits 0-15 are the VM contexts0-15 */ 638 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 639 } 640 641 static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 642 unsigned vmid, uint64_t pd_addr) 643 { 644 uint32_t reg; 645 646 if (vmid < 8) 647 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; 648 else 649 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; 650 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); 651 652 /* bits 0-15 are the VM contexts0-15 */ 653 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); 654 655 return pd_addr; 656 } 657 658 static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 659 unsigned pasid) 660 { 661 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); 662 } 663 664 /** 665 * gmc_v8_0_set_pte_pde - update the page tables using MMIO 666 * 667 * @adev: amdgpu_device pointer 668 * @cpu_pt_addr: cpu address of the page table 669 * @gpu_page_idx: entry in the page table to update 670 * @addr: dst addr to write into pte/pde 671 * @flags: access flags 672 * 673 * Update the page tables using the CPU. 674 */ 675 static int gmc_v8_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 676 uint32_t gpu_page_idx, uint64_t addr, 677 uint64_t flags) 678 { 679 void __iomem *ptr = (void *)cpu_pt_addr; 680 uint64_t value; 681 682 /* 683 * PTE format on VI: 684 * 63:40 reserved 685 * 39:12 4k physical page base address 686 * 11:7 fragment 687 * 6 write 688 * 5 read 689 * 4 exe 690 * 3 reserved 691 * 2 snooped 692 * 1 system 693 * 0 valid 694 * 695 * PDE format on VI: 696 * 63:59 block fragment size 697 * 58:40 reserved 698 * 39:1 physical base address of PTE 699 * bits 5:1 must be 0. 700 * 0 valid 701 */ 702 value = addr & 0x000000FFFFFFF000ULL; 703 value |= flags; 704 writeq(value, ptr + (gpu_page_idx * 8)); 705 706 return 0; 707 } 708 709 static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev, 710 uint32_t flags) 711 { 712 uint64_t pte_flag = 0; 713 714 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 715 pte_flag |= AMDGPU_PTE_EXECUTABLE; 716 if (flags & AMDGPU_VM_PAGE_READABLE) 717 pte_flag |= AMDGPU_PTE_READABLE; 718 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 719 pte_flag |= AMDGPU_PTE_WRITEABLE; 720 if (flags & AMDGPU_VM_PAGE_PRT) 721 pte_flag |= AMDGPU_PTE_PRT; 722 723 return pte_flag; 724 } 725 726 static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level, 727 uint64_t *addr, uint64_t *flags) 728 { 729 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); 730 } 731 732 /** 733 * gmc_v8_0_set_fault_enable_default - update VM fault handling 734 * 735 * @adev: amdgpu_device pointer 736 * @value: true redirects VM faults to the default page 737 */ 738 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev, 739 bool value) 740 { 741 u32 tmp; 742 743 tmp = RREG32(mmVM_CONTEXT1_CNTL); 744 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 745 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 746 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 747 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 748 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 749 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 750 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 751 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 752 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 753 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 754 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 755 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 756 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 757 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 758 WREG32(mmVM_CONTEXT1_CNTL, tmp); 759 } 760 761 /** 762 * gmc_v8_0_set_prt - set PRT VM fault 763 * 764 * @adev: amdgpu_device pointer 765 * @enable: enable/disable VM fault handling for PRT 766 */ 767 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable) 768 { 769 u32 tmp; 770 771 if (enable && !adev->gmc.prt_warning) { 772 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 773 adev->gmc.prt_warning = true; 774 } 775 776 tmp = RREG32(mmVM_PRT_CNTL); 777 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 778 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 779 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 780 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 781 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 782 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 783 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 784 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 785 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 786 L2_CACHE_STORE_INVALID_ENTRIES, enable); 787 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 788 L1_TLB_STORE_INVALID_ENTRIES, enable); 789 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 790 MASK_PDE0_FAULT, enable); 791 WREG32(mmVM_PRT_CNTL, tmp); 792 793 if (enable) { 794 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; 795 uint32_t high = adev->vm_manager.max_pfn - 796 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT); 797 798 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 799 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 800 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 801 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 802 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 803 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 804 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 805 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 806 } else { 807 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 808 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 809 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 810 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 811 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 812 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 813 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 814 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 815 } 816 } 817 818 /** 819 * gmc_v8_0_gart_enable - gart enable 820 * 821 * @adev: amdgpu_device pointer 822 * 823 * This sets up the TLBs, programs the page tables for VMID0, 824 * sets up the hw for VMIDs 1-15 which are allocated on 825 * demand, and sets up the global locations for the LDS, GDS, 826 * and GPUVM for FSA64 clients (CIK). 827 * Returns 0 for success, errors for failure. 828 */ 829 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) 830 { 831 int r, i; 832 u32 tmp, field; 833 834 if (adev->gart.robj == NULL) { 835 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 836 return -EINVAL; 837 } 838 r = amdgpu_gart_table_vram_pin(adev); 839 if (r) 840 return r; 841 /* Setup TLB control */ 842 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 843 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 844 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 845 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 846 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 847 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 848 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 849 /* Setup L2 cache */ 850 tmp = RREG32(mmVM_L2_CNTL); 851 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 852 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 853 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 854 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 855 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 856 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 857 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 858 WREG32(mmVM_L2_CNTL, tmp); 859 tmp = RREG32(mmVM_L2_CNTL2); 860 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 861 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 862 WREG32(mmVM_L2_CNTL2, tmp); 863 864 field = adev->vm_manager.fragment_size; 865 tmp = RREG32(mmVM_L2_CNTL3); 866 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 867 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); 868 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); 869 WREG32(mmVM_L2_CNTL3, tmp); 870 /* XXX: set to enable PTE/PDE in system memory */ 871 tmp = RREG32(mmVM_L2_CNTL4); 872 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0); 873 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0); 874 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0); 875 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0); 876 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0); 877 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0); 878 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0); 879 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0); 880 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0); 881 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0); 882 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0); 883 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0); 884 WREG32(mmVM_L2_CNTL4, tmp); 885 /* setup context0 */ 886 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); 887 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); 888 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); 889 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 890 (u32)(adev->dummy_page_addr >> 12)); 891 WREG32(mmVM_CONTEXT0_CNTL2, 0); 892 tmp = RREG32(mmVM_CONTEXT0_CNTL); 893 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 894 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 895 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 896 WREG32(mmVM_CONTEXT0_CNTL, tmp); 897 898 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0); 899 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0); 900 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0); 901 902 /* empty context1-15 */ 903 /* FIXME start with 4G, once using 2 level pt switch to full 904 * vm size space 905 */ 906 /* set vm size, must be a multiple of 4 */ 907 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 908 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 909 for (i = 1; i < 16; i++) { 910 if (i < 8) 911 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 912 adev->gart.table_addr >> 12); 913 else 914 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 915 adev->gart.table_addr >> 12); 916 } 917 918 /* enable context1-15 */ 919 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 920 (u32)(adev->dummy_page_addr >> 12)); 921 WREG32(mmVM_CONTEXT1_CNTL2, 4); 922 tmp = RREG32(mmVM_CONTEXT1_CNTL); 923 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 924 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 925 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 926 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 927 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 928 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 929 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 930 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 931 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 932 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 933 adev->vm_manager.block_size - 9); 934 WREG32(mmVM_CONTEXT1_CNTL, tmp); 935 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 936 gmc_v8_0_set_fault_enable_default(adev, false); 937 else 938 gmc_v8_0_set_fault_enable_default(adev, true); 939 940 gmc_v8_0_flush_gpu_tlb(adev, 0); 941 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 942 (unsigned)(adev->gmc.gart_size >> 20), 943 (unsigned long long)adev->gart.table_addr); 944 adev->gart.ready = true; 945 return 0; 946 } 947 948 static int gmc_v8_0_gart_init(struct amdgpu_device *adev) 949 { 950 int r; 951 952 if (adev->gart.robj) { 953 WARN(1, "R600 PCIE GART already initialized\n"); 954 return 0; 955 } 956 /* Initialize common gart structure */ 957 r = amdgpu_gart_init(adev); 958 if (r) 959 return r; 960 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 961 adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE; 962 return amdgpu_gart_table_vram_alloc(adev); 963 } 964 965 /** 966 * gmc_v8_0_gart_disable - gart disable 967 * 968 * @adev: amdgpu_device pointer 969 * 970 * This disables all VM page table (CIK). 971 */ 972 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev) 973 { 974 u32 tmp; 975 976 /* Disable all tables */ 977 WREG32(mmVM_CONTEXT0_CNTL, 0); 978 WREG32(mmVM_CONTEXT1_CNTL, 0); 979 /* Setup TLB control */ 980 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 981 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 982 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 983 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 984 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 985 /* Setup L2 cache */ 986 tmp = RREG32(mmVM_L2_CNTL); 987 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 988 WREG32(mmVM_L2_CNTL, tmp); 989 WREG32(mmVM_L2_CNTL2, 0); 990 amdgpu_gart_table_vram_unpin(adev); 991 } 992 993 /** 994 * gmc_v8_0_vm_decode_fault - print human readable fault info 995 * 996 * @adev: amdgpu_device pointer 997 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 998 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 999 * 1000 * Print human readable fault information (CIK). 1001 */ 1002 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, 1003 u32 addr, u32 mc_client, unsigned pasid) 1004 { 1005 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 1006 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1007 PROTECTIONS); 1008 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 1009 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 1010 u32 mc_id; 1011 1012 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1013 MEMORY_CLIENT_ID); 1014 1015 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 1016 protections, vmid, pasid, addr, 1017 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1018 MEMORY_CLIENT_RW) ? 1019 "write" : "read", block, mc_client, mc_id); 1020 } 1021 1022 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type) 1023 { 1024 switch (mc_seq_vram_type) { 1025 case MC_SEQ_MISC0__MT__GDDR1: 1026 return AMDGPU_VRAM_TYPE_GDDR1; 1027 case MC_SEQ_MISC0__MT__DDR2: 1028 return AMDGPU_VRAM_TYPE_DDR2; 1029 case MC_SEQ_MISC0__MT__GDDR3: 1030 return AMDGPU_VRAM_TYPE_GDDR3; 1031 case MC_SEQ_MISC0__MT__GDDR4: 1032 return AMDGPU_VRAM_TYPE_GDDR4; 1033 case MC_SEQ_MISC0__MT__GDDR5: 1034 return AMDGPU_VRAM_TYPE_GDDR5; 1035 case MC_SEQ_MISC0__MT__HBM: 1036 return AMDGPU_VRAM_TYPE_HBM; 1037 case MC_SEQ_MISC0__MT__DDR3: 1038 return AMDGPU_VRAM_TYPE_DDR3; 1039 default: 1040 return AMDGPU_VRAM_TYPE_UNKNOWN; 1041 } 1042 } 1043 1044 static int gmc_v8_0_early_init(void *handle) 1045 { 1046 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1047 1048 gmc_v8_0_set_gmc_funcs(adev); 1049 gmc_v8_0_set_irq_funcs(adev); 1050 1051 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1052 adev->gmc.shared_aperture_end = 1053 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1054 adev->gmc.private_aperture_start = 1055 adev->gmc.shared_aperture_end + 1; 1056 adev->gmc.private_aperture_end = 1057 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1058 1059 return 0; 1060 } 1061 1062 static int gmc_v8_0_late_init(void *handle) 1063 { 1064 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1065 1066 amdgpu_bo_late_init(adev); 1067 1068 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 1069 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1070 else 1071 return 0; 1072 } 1073 1074 static unsigned gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev) 1075 { 1076 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); 1077 unsigned size; 1078 1079 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1080 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 1081 } else { 1082 u32 viewport = RREG32(mmVIEWPORT_SIZE); 1083 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1084 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1085 4); 1086 } 1087 /* return 0 if the pre-OS buffer uses up most of vram */ 1088 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 1089 return 0; 1090 return size; 1091 } 1092 1093 #define mmMC_SEQ_MISC0_FIJI 0xA71 1094 1095 static int gmc_v8_0_sw_init(void *handle) 1096 { 1097 int r; 1098 int dma_bits; 1099 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1100 1101 if (adev->flags & AMD_IS_APU) { 1102 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 1103 } else { 1104 u32 tmp; 1105 1106 if ((adev->asic_type == CHIP_FIJI) || 1107 (adev->asic_type == CHIP_VEGAM)) 1108 tmp = RREG32(mmMC_SEQ_MISC0_FIJI); 1109 else 1110 tmp = RREG32(mmMC_SEQ_MISC0); 1111 tmp &= MC_SEQ_MISC0__MT__MASK; 1112 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp); 1113 } 1114 1115 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault); 1116 if (r) 1117 return r; 1118 1119 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault); 1120 if (r) 1121 return r; 1122 1123 /* Adjust VM size here. 1124 * Currently set to 4GB ((1 << 20) 4k pages). 1125 * Max GPUVM size for cayman and SI is 40 bits. 1126 */ 1127 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 1128 1129 /* Set the internal MC address mask 1130 * This is the max address of the GPU's 1131 * internal address space. 1132 */ 1133 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1134 1135 /* set DMA mask + need_dma32 flags. 1136 * PCIE - can handle 40-bits. 1137 * IGP - can handle 40-bits 1138 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 1139 */ 1140 adev->need_dma32 = false; 1141 dma_bits = adev->need_dma32 ? 32 : 40; 1142 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1143 if (r) { 1144 adev->need_dma32 = true; 1145 dma_bits = 32; 1146 pr_warn("amdgpu: No suitable DMA available\n"); 1147 } 1148 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1149 if (r) { 1150 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 1151 pr_warn("amdgpu: No coherent DMA available\n"); 1152 } 1153 #if 0 1154 adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits); 1155 #endif 1156 /* XXX DragonFly: FreeBSD implementation returns false 1157 * drm-kmod excerpt: 1158 * Only used in combination with CONFIG_SWIOTLB in v4.17 1159 * BSDFIXME: Let's say we can dma all physical memory... 1160 */ 1161 adev->need_swiotlb = false; 1162 1163 r = gmc_v8_0_init_microcode(adev); 1164 if (r) { 1165 DRM_ERROR("Failed to load mc firmware!\n"); 1166 return r; 1167 } 1168 1169 r = gmc_v8_0_mc_init(adev); 1170 if (r) 1171 return r; 1172 1173 adev->gmc.stolen_size = gmc_v8_0_get_vbios_fb_size(adev); 1174 1175 /* Memory manager */ 1176 r = amdgpu_bo_init(adev); 1177 if (r) 1178 return r; 1179 1180 r = gmc_v8_0_gart_init(adev); 1181 if (r) 1182 return r; 1183 1184 /* 1185 * number of VMs 1186 * VMID 0 is reserved for System 1187 * amdgpu graphics/compute will use VMIDs 1-7 1188 * amdkfd will use VMIDs 8-15 1189 */ 1190 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; 1191 amdgpu_vm_manager_init(adev); 1192 1193 /* base offset of vram pages */ 1194 if (adev->flags & AMD_IS_APU) { 1195 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 1196 1197 tmp <<= 22; 1198 adev->vm_manager.vram_base_offset = tmp; 1199 } else { 1200 adev->vm_manager.vram_base_offset = 0; 1201 } 1202 1203 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info), 1204 M_DRM, 1205 GFP_KERNEL); 1206 if (!adev->gmc.vm_fault_info) 1207 return -ENOMEM; 1208 atomic_set(&adev->gmc.vm_fault_info_updated, 0); 1209 1210 return 0; 1211 } 1212 1213 static int gmc_v8_0_sw_fini(void *handle) 1214 { 1215 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1216 1217 amdgpu_gem_force_release(adev); 1218 amdgpu_vm_manager_fini(adev); 1219 kfree(adev->gmc.vm_fault_info); 1220 amdgpu_gart_table_vram_free(adev); 1221 amdgpu_bo_fini(adev); 1222 amdgpu_gart_fini(adev); 1223 release_firmware(adev->gmc.fw); 1224 adev->gmc.fw = NULL; 1225 1226 return 0; 1227 } 1228 1229 static int gmc_v8_0_hw_init(void *handle) 1230 { 1231 int r; 1232 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1233 1234 gmc_v8_0_init_golden_registers(adev); 1235 1236 gmc_v8_0_mc_program(adev); 1237 1238 if (adev->asic_type == CHIP_TONGA) { 1239 r = gmc_v8_0_tonga_mc_load_microcode(adev); 1240 if (r) { 1241 DRM_ERROR("Failed to load MC firmware!\n"); 1242 return r; 1243 } 1244 } else if (adev->asic_type == CHIP_POLARIS11 || 1245 adev->asic_type == CHIP_POLARIS10 || 1246 adev->asic_type == CHIP_POLARIS12) { 1247 r = gmc_v8_0_polaris_mc_load_microcode(adev); 1248 if (r) { 1249 DRM_ERROR("Failed to load MC firmware!\n"); 1250 return r; 1251 } 1252 } 1253 1254 r = gmc_v8_0_gart_enable(adev); 1255 if (r) 1256 return r; 1257 1258 return r; 1259 } 1260 1261 static int gmc_v8_0_hw_fini(void *handle) 1262 { 1263 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1264 1265 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1266 gmc_v8_0_gart_disable(adev); 1267 1268 return 0; 1269 } 1270 1271 static int gmc_v8_0_suspend(void *handle) 1272 { 1273 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1274 1275 gmc_v8_0_hw_fini(adev); 1276 1277 return 0; 1278 } 1279 1280 static int gmc_v8_0_resume(void *handle) 1281 { 1282 int r; 1283 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1284 1285 r = gmc_v8_0_hw_init(adev); 1286 if (r) 1287 return r; 1288 1289 amdgpu_vmid_reset_all(adev); 1290 1291 return 0; 1292 } 1293 1294 static bool gmc_v8_0_is_idle(void *handle) 1295 { 1296 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1297 u32 tmp = RREG32(mmSRBM_STATUS); 1298 1299 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1300 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1301 return false; 1302 1303 return true; 1304 } 1305 1306 static int gmc_v8_0_wait_for_idle(void *handle) 1307 { 1308 unsigned i; 1309 u32 tmp; 1310 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1311 1312 for (i = 0; i < adev->usec_timeout; i++) { 1313 /* read MC_STATUS */ 1314 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1315 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1316 SRBM_STATUS__MCC_BUSY_MASK | 1317 SRBM_STATUS__MCD_BUSY_MASK | 1318 SRBM_STATUS__VMC_BUSY_MASK | 1319 SRBM_STATUS__VMC1_BUSY_MASK); 1320 if (!tmp) 1321 return 0; 1322 udelay(1); 1323 } 1324 return -ETIMEDOUT; 1325 1326 } 1327 1328 static bool gmc_v8_0_check_soft_reset(void *handle) 1329 { 1330 u32 srbm_soft_reset = 0; 1331 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1332 u32 tmp = RREG32(mmSRBM_STATUS); 1333 1334 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1335 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1336 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1337 1338 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1339 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1340 if (!(adev->flags & AMD_IS_APU)) 1341 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1342 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1343 } 1344 if (srbm_soft_reset) { 1345 adev->gmc.srbm_soft_reset = srbm_soft_reset; 1346 return true; 1347 } else { 1348 adev->gmc.srbm_soft_reset = 0; 1349 return false; 1350 } 1351 } 1352 1353 static int gmc_v8_0_pre_soft_reset(void *handle) 1354 { 1355 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1356 1357 if (!adev->gmc.srbm_soft_reset) 1358 return 0; 1359 1360 gmc_v8_0_mc_stop(adev); 1361 if (gmc_v8_0_wait_for_idle(adev)) { 1362 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1363 } 1364 1365 return 0; 1366 } 1367 1368 static int gmc_v8_0_soft_reset(void *handle) 1369 { 1370 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1371 u32 srbm_soft_reset; 1372 1373 if (!adev->gmc.srbm_soft_reset) 1374 return 0; 1375 srbm_soft_reset = adev->gmc.srbm_soft_reset; 1376 1377 if (srbm_soft_reset) { 1378 u32 tmp; 1379 1380 tmp = RREG32(mmSRBM_SOFT_RESET); 1381 tmp |= srbm_soft_reset; 1382 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1383 WREG32(mmSRBM_SOFT_RESET, tmp); 1384 tmp = RREG32(mmSRBM_SOFT_RESET); 1385 1386 udelay(50); 1387 1388 tmp &= ~srbm_soft_reset; 1389 WREG32(mmSRBM_SOFT_RESET, tmp); 1390 tmp = RREG32(mmSRBM_SOFT_RESET); 1391 1392 /* Wait a little for things to settle down */ 1393 udelay(50); 1394 } 1395 1396 return 0; 1397 } 1398 1399 static int gmc_v8_0_post_soft_reset(void *handle) 1400 { 1401 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1402 1403 if (!adev->gmc.srbm_soft_reset) 1404 return 0; 1405 1406 gmc_v8_0_mc_resume(adev); 1407 return 0; 1408 } 1409 1410 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1411 struct amdgpu_irq_src *src, 1412 unsigned type, 1413 enum amdgpu_interrupt_state state) 1414 { 1415 u32 tmp; 1416 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1417 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1418 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1419 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1420 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1421 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1422 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1423 1424 switch (state) { 1425 case AMDGPU_IRQ_STATE_DISABLE: 1426 /* system context */ 1427 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1428 tmp &= ~bits; 1429 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1430 /* VMs */ 1431 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1432 tmp &= ~bits; 1433 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1434 break; 1435 case AMDGPU_IRQ_STATE_ENABLE: 1436 /* system context */ 1437 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1438 tmp |= bits; 1439 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1440 /* VMs */ 1441 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1442 tmp |= bits; 1443 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1444 break; 1445 default: 1446 break; 1447 } 1448 1449 return 0; 1450 } 1451 1452 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, 1453 struct amdgpu_irq_src *source, 1454 struct amdgpu_iv_entry *entry) 1455 { 1456 u32 addr, status, mc_client, vmid; 1457 1458 if (amdgpu_sriov_vf(adev)) { 1459 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1460 entry->src_id, entry->src_data[0]); 1461 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n"); 1462 return 0; 1463 } 1464 1465 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1466 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1467 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1468 /* reset addr and status */ 1469 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1470 1471 if (!addr && !status) 1472 return 0; 1473 1474 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1475 gmc_v8_0_set_fault_enable_default(adev, false); 1476 1477 if (printk_ratelimit()) { 1478 struct amdgpu_task_info task_info = { 0 }; 1479 1480 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 1481 1482 dev_err(adev->dev, "GPU fault detected: %d 0x%08x for process %s pid %d thread %s pid %d\n", 1483 entry->src_id, entry->src_data[0], task_info.process_name, 1484 task_info.tgid, task_info.task_name, task_info.pid); 1485 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1486 addr); 1487 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1488 status); 1489 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client, 1490 entry->pasid); 1491 } 1492 1493 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1494 VMID); 1495 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) 1496 && !atomic_read(&adev->gmc.vm_fault_info_updated)) { 1497 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; 1498 u32 protections = REG_GET_FIELD(status, 1499 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1500 PROTECTIONS); 1501 1502 info->vmid = vmid; 1503 info->mc_id = REG_GET_FIELD(status, 1504 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1505 MEMORY_CLIENT_ID); 1506 info->status = status; 1507 info->page_addr = addr; 1508 info->prot_valid = protections & 0x7 ? true : false; 1509 info->prot_read = protections & 0x8 ? true : false; 1510 info->prot_write = protections & 0x10 ? true : false; 1511 info->prot_exec = protections & 0x20 ? true : false; 1512 mb(); 1513 atomic_set(&adev->gmc.vm_fault_info_updated, 1); 1514 } 1515 1516 return 0; 1517 } 1518 1519 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev, 1520 bool enable) 1521 { 1522 uint32_t data; 1523 1524 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 1525 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1526 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1527 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1528 1529 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1530 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1531 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1532 1533 data = RREG32(mmMC_HUB_MISC_VM_CG); 1534 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK; 1535 WREG32(mmMC_HUB_MISC_VM_CG, data); 1536 1537 data = RREG32(mmMC_XPB_CLK_GAT); 1538 data |= MC_XPB_CLK_GAT__ENABLE_MASK; 1539 WREG32(mmMC_XPB_CLK_GAT, data); 1540 1541 data = RREG32(mmATC_MISC_CG); 1542 data |= ATC_MISC_CG__ENABLE_MASK; 1543 WREG32(mmATC_MISC_CG, data); 1544 1545 data = RREG32(mmMC_CITF_MISC_WR_CG); 1546 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK; 1547 WREG32(mmMC_CITF_MISC_WR_CG, data); 1548 1549 data = RREG32(mmMC_CITF_MISC_RD_CG); 1550 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK; 1551 WREG32(mmMC_CITF_MISC_RD_CG, data); 1552 1553 data = RREG32(mmMC_CITF_MISC_VM_CG); 1554 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK; 1555 WREG32(mmMC_CITF_MISC_VM_CG, data); 1556 1557 data = RREG32(mmVM_L2_CG); 1558 data |= VM_L2_CG__ENABLE_MASK; 1559 WREG32(mmVM_L2_CG, data); 1560 } else { 1561 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1562 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1563 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1564 1565 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1566 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1567 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1568 1569 data = RREG32(mmMC_HUB_MISC_VM_CG); 1570 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK; 1571 WREG32(mmMC_HUB_MISC_VM_CG, data); 1572 1573 data = RREG32(mmMC_XPB_CLK_GAT); 1574 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK; 1575 WREG32(mmMC_XPB_CLK_GAT, data); 1576 1577 data = RREG32(mmATC_MISC_CG); 1578 data &= ~ATC_MISC_CG__ENABLE_MASK; 1579 WREG32(mmATC_MISC_CG, data); 1580 1581 data = RREG32(mmMC_CITF_MISC_WR_CG); 1582 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK; 1583 WREG32(mmMC_CITF_MISC_WR_CG, data); 1584 1585 data = RREG32(mmMC_CITF_MISC_RD_CG); 1586 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK; 1587 WREG32(mmMC_CITF_MISC_RD_CG, data); 1588 1589 data = RREG32(mmMC_CITF_MISC_VM_CG); 1590 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK; 1591 WREG32(mmMC_CITF_MISC_VM_CG, data); 1592 1593 data = RREG32(mmVM_L2_CG); 1594 data &= ~VM_L2_CG__ENABLE_MASK; 1595 WREG32(mmVM_L2_CG, data); 1596 } 1597 } 1598 1599 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev, 1600 bool enable) 1601 { 1602 uint32_t data; 1603 1604 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) { 1605 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1606 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1607 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1608 1609 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1610 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1611 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1612 1613 data = RREG32(mmMC_HUB_MISC_VM_CG); 1614 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1615 WREG32(mmMC_HUB_MISC_VM_CG, data); 1616 1617 data = RREG32(mmMC_XPB_CLK_GAT); 1618 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1619 WREG32(mmMC_XPB_CLK_GAT, data); 1620 1621 data = RREG32(mmATC_MISC_CG); 1622 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1623 WREG32(mmATC_MISC_CG, data); 1624 1625 data = RREG32(mmMC_CITF_MISC_WR_CG); 1626 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1627 WREG32(mmMC_CITF_MISC_WR_CG, data); 1628 1629 data = RREG32(mmMC_CITF_MISC_RD_CG); 1630 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1631 WREG32(mmMC_CITF_MISC_RD_CG, data); 1632 1633 data = RREG32(mmMC_CITF_MISC_VM_CG); 1634 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1635 WREG32(mmMC_CITF_MISC_VM_CG, data); 1636 1637 data = RREG32(mmVM_L2_CG); 1638 data |= VM_L2_CG__MEM_LS_ENABLE_MASK; 1639 WREG32(mmVM_L2_CG, data); 1640 } else { 1641 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1642 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1643 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1644 1645 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1646 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1647 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1648 1649 data = RREG32(mmMC_HUB_MISC_VM_CG); 1650 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1651 WREG32(mmMC_HUB_MISC_VM_CG, data); 1652 1653 data = RREG32(mmMC_XPB_CLK_GAT); 1654 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1655 WREG32(mmMC_XPB_CLK_GAT, data); 1656 1657 data = RREG32(mmATC_MISC_CG); 1658 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1659 WREG32(mmATC_MISC_CG, data); 1660 1661 data = RREG32(mmMC_CITF_MISC_WR_CG); 1662 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1663 WREG32(mmMC_CITF_MISC_WR_CG, data); 1664 1665 data = RREG32(mmMC_CITF_MISC_RD_CG); 1666 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1667 WREG32(mmMC_CITF_MISC_RD_CG, data); 1668 1669 data = RREG32(mmMC_CITF_MISC_VM_CG); 1670 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1671 WREG32(mmMC_CITF_MISC_VM_CG, data); 1672 1673 data = RREG32(mmVM_L2_CG); 1674 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK; 1675 WREG32(mmVM_L2_CG, data); 1676 } 1677 } 1678 1679 static int gmc_v8_0_set_clockgating_state(void *handle, 1680 enum amd_clockgating_state state) 1681 { 1682 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1683 1684 if (amdgpu_sriov_vf(adev)) 1685 return 0; 1686 1687 switch (adev->asic_type) { 1688 case CHIP_FIJI: 1689 fiji_update_mc_medium_grain_clock_gating(adev, 1690 state == AMD_CG_STATE_GATE); 1691 fiji_update_mc_light_sleep(adev, 1692 state == AMD_CG_STATE_GATE); 1693 break; 1694 default: 1695 break; 1696 } 1697 return 0; 1698 } 1699 1700 static int gmc_v8_0_set_powergating_state(void *handle, 1701 enum amd_powergating_state state) 1702 { 1703 return 0; 1704 } 1705 1706 static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags) 1707 { 1708 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1709 int data; 1710 1711 if (amdgpu_sriov_vf(adev)) 1712 *flags = 0; 1713 1714 /* AMD_CG_SUPPORT_MC_MGCG */ 1715 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1716 if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK) 1717 *flags |= AMD_CG_SUPPORT_MC_MGCG; 1718 1719 /* AMD_CG_SUPPORT_MC_LS */ 1720 if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK) 1721 *flags |= AMD_CG_SUPPORT_MC_LS; 1722 } 1723 1724 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = { 1725 .name = "gmc_v8_0", 1726 .early_init = gmc_v8_0_early_init, 1727 .late_init = gmc_v8_0_late_init, 1728 .sw_init = gmc_v8_0_sw_init, 1729 .sw_fini = gmc_v8_0_sw_fini, 1730 .hw_init = gmc_v8_0_hw_init, 1731 .hw_fini = gmc_v8_0_hw_fini, 1732 .suspend = gmc_v8_0_suspend, 1733 .resume = gmc_v8_0_resume, 1734 .is_idle = gmc_v8_0_is_idle, 1735 .wait_for_idle = gmc_v8_0_wait_for_idle, 1736 .check_soft_reset = gmc_v8_0_check_soft_reset, 1737 .pre_soft_reset = gmc_v8_0_pre_soft_reset, 1738 .soft_reset = gmc_v8_0_soft_reset, 1739 .post_soft_reset = gmc_v8_0_post_soft_reset, 1740 .set_clockgating_state = gmc_v8_0_set_clockgating_state, 1741 .set_powergating_state = gmc_v8_0_set_powergating_state, 1742 .get_clockgating_state = gmc_v8_0_get_clockgating_state, 1743 }; 1744 1745 static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = { 1746 .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb, 1747 .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb, 1748 .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping, 1749 .set_pte_pde = gmc_v8_0_set_pte_pde, 1750 .set_prt = gmc_v8_0_set_prt, 1751 .get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags, 1752 .get_vm_pde = gmc_v8_0_get_vm_pde 1753 }; 1754 1755 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = { 1756 .set = gmc_v8_0_vm_fault_interrupt_state, 1757 .process = gmc_v8_0_process_interrupt, 1758 }; 1759 1760 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev) 1761 { 1762 if (adev->gmc.gmc_funcs == NULL) 1763 adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs; 1764 } 1765 1766 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev) 1767 { 1768 adev->gmc.vm_fault.num_types = 1; 1769 adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs; 1770 } 1771 1772 const struct amdgpu_ip_block_version gmc_v8_0_ip_block = 1773 { 1774 .type = AMD_IP_BLOCK_TYPE_GMC, 1775 .major = 8, 1776 .minor = 0, 1777 .rev = 0, 1778 .funcs = &gmc_v8_0_ip_funcs, 1779 }; 1780 1781 const struct amdgpu_ip_block_version gmc_v8_1_ip_block = 1782 { 1783 .type = AMD_IP_BLOCK_TYPE_GMC, 1784 .major = 8, 1785 .minor = 1, 1786 .rev = 0, 1787 .funcs = &gmc_v8_0_ip_funcs, 1788 }; 1789 1790 const struct amdgpu_ip_block_version gmc_v8_5_ip_block = 1791 { 1792 .type = AMD_IP_BLOCK_TYPE_GMC, 1793 .major = 8, 1794 .minor = 5, 1795 .rev = 0, 1796 .funcs = &gmc_v8_0_ip_funcs, 1797 }; 1798