1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "mmhub_v1_0.h" 25 26 #include "mmhub/mmhub_1_0_offset.h" 27 #include "mmhub/mmhub_1_0_sh_mask.h" 28 #include "mmhub/mmhub_1_0_default.h" 29 #include "athub/athub_1_0_offset.h" 30 #include "athub/athub_1_0_sh_mask.h" 31 #include "vega10_enum.h" 32 33 #include "soc15_common.h" 34 35 #define mmDAGB0_CNTL_MISC2_RV 0x008f 36 #define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0 37 38 u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev) 39 { 40 u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE); 41 42 base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 43 base <<= 24; 44 45 return base; 46 } 47 48 static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev) 49 { 50 uint64_t value; 51 52 BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL)); 53 value = adev->gart.table_addr - adev->gmc.vram_start + 54 adev->vm_manager.vram_base_offset; 55 value &= 0x0000FFFFFFFFF000ULL; 56 value |= 0x1; /* valid bit */ 57 58 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 59 lower_32_bits(value)); 60 61 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 62 upper_32_bits(value)); 63 } 64 65 static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev) 66 { 67 mmhub_v1_0_init_gart_pt_regs(adev); 68 69 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 70 (u32)(adev->gmc.gart_start >> 12)); 71 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 72 (u32)(adev->gmc.gart_start >> 44)); 73 74 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 75 (u32)(adev->gmc.gart_end >> 12)); 76 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 77 (u32)(adev->gmc.gart_end >> 44)); 78 } 79 80 static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 81 { 82 uint64_t value; 83 uint32_t tmp; 84 85 /* Disable AGP. */ 86 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0); 87 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, 0); 88 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, 0x00FFFFFF); 89 90 /* Program the system aperture low logical page number. */ 91 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 92 adev->gmc.vram_start >> 18); 93 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 94 adev->gmc.vram_end >> 18); 95 96 /* Set default page address. */ 97 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + 98 adev->vm_manager.vram_base_offset; 99 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 100 (u32)(value >> 12)); 101 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 102 (u32)(value >> 44)); 103 104 /* Program "protection fault". */ 105 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 106 (u32)(adev->dummy_page_addr >> 12)); 107 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 108 (u32)((u64)adev->dummy_page_addr >> 44)); 109 110 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2); 111 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, 112 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 113 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp); 114 } 115 116 static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) 117 { 118 uint32_t tmp; 119 120 /* Setup TLB control */ 121 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); 122 123 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 124 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 125 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 126 ENABLE_ADVANCED_DRIVER_MODEL, 1); 127 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 128 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 129 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 130 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 131 MTYPE, MTYPE_UC);/* XXX for emulation. */ 132 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); 133 134 WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); 135 } 136 137 static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 138 { 139 uint32_t tmp; 140 141 /* Setup L2 cache */ 142 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); 143 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 144 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 145 /* XXX for emulation, Refer to closed source code.*/ 146 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 147 0); 148 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1); 149 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 150 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 151 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp); 152 153 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2); 154 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 155 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 156 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp); 157 158 if (adev->gmc.translate_further) { 159 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); 160 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 161 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 162 } else { 163 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); 164 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 165 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 166 } 167 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp); 168 169 tmp = mmVM_L2_CNTL4_DEFAULT; 170 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 171 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 172 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp); 173 } 174 175 static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev) 176 { 177 uint32_t tmp; 178 179 tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL); 180 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 181 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 182 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL, tmp); 183 } 184 185 static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev) 186 { 187 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 188 0XFFFFFFFF); 189 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 190 0x0000000F); 191 192 WREG32_SOC15(MMHUB, 0, 193 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 194 WREG32_SOC15(MMHUB, 0, 195 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 196 197 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 198 0); 199 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 200 0); 201 } 202 203 static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) 204 { 205 unsigned num_level, block_size; 206 uint32_t tmp; 207 int i; 208 209 num_level = adev->vm_manager.num_level; 210 block_size = adev->vm_manager.block_size; 211 if (adev->gmc.translate_further) 212 num_level -= 1; 213 else 214 block_size -= 9; 215 216 for (i = 0; i <= 14; i++) { 217 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i); 218 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 219 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 220 num_level); 221 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 222 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 223 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 224 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 225 1); 226 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 227 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 228 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 229 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 230 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 231 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 232 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 233 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 234 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 235 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 236 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 237 PAGE_TABLE_BLOCK_SIZE, 238 block_size); 239 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 240 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 241 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 242 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i, tmp); 243 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); 244 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); 245 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2, 246 lower_32_bits(adev->vm_manager.max_pfn - 1)); 247 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2, 248 upper_32_bits(adev->vm_manager.max_pfn - 1)); 249 } 250 } 251 252 static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev) 253 { 254 unsigned i; 255 256 for (i = 0; i < 18; ++i) { 257 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 258 2 * i, 0xffffffff); 259 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 260 2 * i, 0x1f); 261 } 262 } 263 264 struct pctl_data { 265 uint32_t index; 266 uint32_t data; 267 }; 268 269 static const struct pctl_data pctl0_data[] = { 270 {0x0, 0x7a640}, 271 {0x9, 0x2a64a}, 272 {0xd, 0x2a680}, 273 {0x11, 0x6a684}, 274 {0x19, 0xea68e}, 275 {0x29, 0xa69e}, 276 {0x2b, 0x0010a6c0}, 277 {0x3d, 0x83a707}, 278 {0xc2, 0x8a7a4}, 279 {0xcc, 0x1a7b8}, 280 {0xcf, 0xfa7cc}, 281 {0xe0, 0x17a7dd}, 282 {0xf9, 0xa7dc}, 283 {0xfb, 0x12a7f5}, 284 {0x10f, 0xa808}, 285 {0x111, 0x12a810}, 286 {0x125, 0x7a82c} 287 }; 288 #define PCTL0_DATA_LEN (ARRAY_SIZE(pctl0_data)) 289 290 #define PCTL0_RENG_EXEC_END_PTR 0x12d 291 #define PCTL0_STCTRL_REG_SAVE_RANGE0_BASE 0xa640 292 #define PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa833 293 294 static const struct pctl_data pctl1_data[] = { 295 {0x0, 0x39a000}, 296 {0x3b, 0x44a040}, 297 {0x81, 0x2a08d}, 298 {0x85, 0x6ba094}, 299 {0xf2, 0x18a100}, 300 {0x10c, 0x4a132}, 301 {0x112, 0xca141}, 302 {0x120, 0x2fa158}, 303 {0x151, 0x17a1d0}, 304 {0x16a, 0x1a1e9}, 305 {0x16d, 0x13a1ec}, 306 {0x182, 0x7a201}, 307 {0x18b, 0x3a20a}, 308 {0x190, 0x7a580}, 309 {0x199, 0xa590}, 310 {0x19b, 0x4a594}, 311 {0x1a1, 0x1a59c}, 312 {0x1a4, 0x7a82c}, 313 {0x1ad, 0xfa7cc}, 314 {0x1be, 0x17a7dd}, 315 {0x1d7, 0x12a810}, 316 {0x1eb, 0x4000a7e1}, 317 {0x1ec, 0x5000a7f5}, 318 {0x1ed, 0x4000a7e2}, 319 {0x1ee, 0x5000a7dc}, 320 {0x1ef, 0x4000a7e3}, 321 {0x1f0, 0x5000a7f6}, 322 {0x1f1, 0x5000a7e4} 323 }; 324 #define PCTL1_DATA_LEN (ARRAY_SIZE(pctl1_data)) 325 326 #define PCTL1_RENG_EXEC_END_PTR 0x1f1 327 #define PCTL1_STCTRL_REG_SAVE_RANGE0_BASE 0xa000 328 #define PCTL1_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa20d 329 #define PCTL1_STCTRL_REG_SAVE_RANGE1_BASE 0xa580 330 #define PCTL1_STCTRL_REG_SAVE_RANGE1_LIMIT 0xa59d 331 #define PCTL1_STCTRL_REG_SAVE_RANGE2_BASE 0xa82c 332 #define PCTL1_STCTRL_REG_SAVE_RANGE2_LIMIT 0xa833 333 334 static void mmhub_v1_0_power_gating_write_save_ranges(struct amdgpu_device *adev) 335 { 336 uint32_t tmp = 0; 337 338 /* PCTL0_STCTRL_REGISTER_SAVE_RANGE0 */ 339 tmp = REG_SET_FIELD(tmp, PCTL0_STCTRL_REGISTER_SAVE_RANGE0, 340 STCTRL_REGISTER_SAVE_BASE, 341 PCTL0_STCTRL_REG_SAVE_RANGE0_BASE); 342 tmp = REG_SET_FIELD(tmp, PCTL0_STCTRL_REGISTER_SAVE_RANGE0, 343 STCTRL_REGISTER_SAVE_LIMIT, 344 PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT); 345 WREG32_SOC15(MMHUB, 0, mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0, tmp); 346 347 /* PCTL1_STCTRL_REGISTER_SAVE_RANGE0 */ 348 tmp = 0; 349 tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE0, 350 STCTRL_REGISTER_SAVE_BASE, 351 PCTL1_STCTRL_REG_SAVE_RANGE0_BASE); 352 tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE0, 353 STCTRL_REGISTER_SAVE_LIMIT, 354 PCTL1_STCTRL_REG_SAVE_RANGE0_LIMIT); 355 WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0, tmp); 356 357 /* PCTL1_STCTRL_REGISTER_SAVE_RANGE1 */ 358 tmp = 0; 359 tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE1, 360 STCTRL_REGISTER_SAVE_BASE, 361 PCTL1_STCTRL_REG_SAVE_RANGE1_BASE); 362 tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE1, 363 STCTRL_REGISTER_SAVE_LIMIT, 364 PCTL1_STCTRL_REG_SAVE_RANGE1_LIMIT); 365 WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1, tmp); 366 367 /* PCTL1_STCTRL_REGISTER_SAVE_RANGE2 */ 368 tmp = 0; 369 tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE2, 370 STCTRL_REGISTER_SAVE_BASE, 371 PCTL1_STCTRL_REG_SAVE_RANGE2_BASE); 372 tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE2, 373 STCTRL_REGISTER_SAVE_LIMIT, 374 PCTL1_STCTRL_REG_SAVE_RANGE2_LIMIT); 375 WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2, tmp); 376 } 377 378 void mmhub_v1_0_initialize_power_gating(struct amdgpu_device *adev) 379 { 380 uint32_t pctl0_misc = 0; 381 uint32_t pctl0_reng_execute = 0; 382 uint32_t pctl1_misc = 0; 383 uint32_t pctl1_reng_execute = 0; 384 int i = 0; 385 386 if (amdgpu_sriov_vf(adev)) 387 return; 388 389 /****************** pctl0 **********************/ 390 pctl0_misc = RREG32_SOC15(MMHUB, 0, mmPCTL0_MISC); 391 pctl0_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE); 392 393 /* Light sleep must be disabled before writing to pctl0 registers */ 394 pctl0_misc &= ~PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK; 395 WREG32_SOC15(MMHUB, 0, mmPCTL0_MISC, pctl0_misc); 396 397 /* Write data used to access ram of register engine */ 398 for (i = 0; i < PCTL0_DATA_LEN; i++) { 399 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_RAM_INDEX, 400 pctl0_data[i].index); 401 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_RAM_DATA, 402 pctl0_data[i].data); 403 } 404 405 /* Re-enable light sleep */ 406 pctl0_misc |= PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK; 407 WREG32_SOC15(MMHUB, 0, mmPCTL0_MISC, pctl0_misc); 408 409 /****************** pctl1 **********************/ 410 pctl1_misc = RREG32_SOC15(MMHUB, 0, mmPCTL1_MISC); 411 pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE); 412 413 /* Light sleep must be disabled before writing to pctl1 registers */ 414 pctl1_misc &= ~PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK; 415 WREG32_SOC15(MMHUB, 0, mmPCTL1_MISC, pctl1_misc); 416 417 /* Write data used to access ram of register engine */ 418 for (i = 0; i < PCTL1_DATA_LEN; i++) { 419 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_RAM_INDEX, 420 pctl1_data[i].index); 421 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_RAM_DATA, 422 pctl1_data[i].data); 423 } 424 425 /* Re-enable light sleep */ 426 pctl1_misc |= PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK; 427 WREG32_SOC15(MMHUB, 0, mmPCTL1_MISC, pctl1_misc); 428 429 mmhub_v1_0_power_gating_write_save_ranges(adev); 430 431 /* Set the reng execute end ptr for pctl0 */ 432 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute, 433 PCTL0_RENG_EXECUTE, 434 RENG_EXECUTE_END_PTR, 435 PCTL0_RENG_EXEC_END_PTR); 436 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute); 437 438 /* Set the reng execute end ptr for pctl1 */ 439 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute, 440 PCTL1_RENG_EXECUTE, 441 RENG_EXECUTE_END_PTR, 442 PCTL1_RENG_EXEC_END_PTR); 443 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute); 444 } 445 446 void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev, 447 bool enable) 448 { 449 uint32_t pctl0_reng_execute = 0; 450 uint32_t pctl1_reng_execute = 0; 451 452 if (amdgpu_sriov_vf(adev)) 453 return; 454 455 pctl0_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE); 456 pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE); 457 458 if (enable && adev->pg_flags & AMD_PG_SUPPORT_MMHUB) { 459 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute, 460 PCTL0_RENG_EXECUTE, 461 RENG_EXECUTE_ON_PWR_UP, 1); 462 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute, 463 PCTL0_RENG_EXECUTE, 464 RENG_EXECUTE_ON_REG_UPDATE, 1); 465 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute); 466 467 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute, 468 PCTL1_RENG_EXECUTE, 469 RENG_EXECUTE_ON_PWR_UP, 1); 470 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute, 471 PCTL1_RENG_EXECUTE, 472 RENG_EXECUTE_ON_REG_UPDATE, 1); 473 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute); 474 475 if (adev->powerplay.pp_funcs->set_powergating_by_smu) 476 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GMC, true); 477 478 } else { 479 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute, 480 PCTL0_RENG_EXECUTE, 481 RENG_EXECUTE_ON_PWR_UP, 0); 482 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute, 483 PCTL0_RENG_EXECUTE, 484 RENG_EXECUTE_ON_REG_UPDATE, 0); 485 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute); 486 487 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute, 488 PCTL1_RENG_EXECUTE, 489 RENG_EXECUTE_ON_PWR_UP, 0); 490 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute, 491 PCTL1_RENG_EXECUTE, 492 RENG_EXECUTE_ON_REG_UPDATE, 0); 493 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute); 494 } 495 } 496 497 int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) 498 { 499 if (amdgpu_sriov_vf(adev)) { 500 /* 501 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 502 * VF copy registers so vbios post doesn't program them, for 503 * SRIOV driver need to program them 504 */ 505 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE, 506 adev->gmc.vram_start >> 24); 507 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP, 508 adev->gmc.vram_end >> 24); 509 } 510 511 /* GART Enable. */ 512 mmhub_v1_0_init_gart_aperture_regs(adev); 513 mmhub_v1_0_init_system_aperture_regs(adev); 514 mmhub_v1_0_init_tlb_regs(adev); 515 mmhub_v1_0_init_cache_regs(adev); 516 517 mmhub_v1_0_enable_system_domain(adev); 518 mmhub_v1_0_disable_identity_aperture(adev); 519 mmhub_v1_0_setup_vmid_config(adev); 520 mmhub_v1_0_program_invalidation(adev); 521 522 return 0; 523 } 524 525 void mmhub_v1_0_gart_disable(struct amdgpu_device *adev) 526 { 527 u32 tmp; 528 u32 i; 529 530 /* Disable all tables */ 531 for (i = 0; i < 16; i++) 532 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL, i, 0); 533 534 /* Setup TLB control */ 535 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); 536 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 537 tmp = REG_SET_FIELD(tmp, 538 MC_VM_MX_L1_TLB_CNTL, 539 ENABLE_ADVANCED_DRIVER_MODEL, 540 0); 541 WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); 542 543 /* Setup L2 cache */ 544 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); 545 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 546 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp); 547 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, 0); 548 } 549 550 /** 551 * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling 552 * 553 * @adev: amdgpu_device pointer 554 * @value: true redirects VM faults to the default page 555 */ 556 void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) 557 { 558 u32 tmp; 559 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL); 560 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 561 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 562 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 563 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 564 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 565 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 566 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 567 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 568 tmp = REG_SET_FIELD(tmp, 569 VM_L2_PROTECTION_FAULT_CNTL, 570 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 571 value); 572 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 573 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 574 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 575 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 576 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 577 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 578 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 579 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 580 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 581 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 582 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 583 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 584 if (!value) { 585 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 586 CRASH_ON_NO_RETRY_FAULT, 1); 587 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 588 CRASH_ON_RETRY_FAULT, 1); 589 } 590 591 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp); 592 } 593 594 void mmhub_v1_0_init(struct amdgpu_device *adev) 595 { 596 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB]; 597 598 hub->ctx0_ptb_addr_lo32 = 599 SOC15_REG_OFFSET(MMHUB, 0, 600 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 601 hub->ctx0_ptb_addr_hi32 = 602 SOC15_REG_OFFSET(MMHUB, 0, 603 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 604 hub->vm_inv_eng0_req = 605 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_REQ); 606 hub->vm_inv_eng0_ack = 607 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ACK); 608 hub->vm_context0_cntl = 609 SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL); 610 hub->vm_l2_pro_fault_status = 611 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_STATUS); 612 hub->vm_l2_pro_fault_cntl = 613 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL); 614 615 } 616 617 static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 618 bool enable) 619 { 620 uint32_t def, data, def1, data1, def2 = 0, data2 = 0; 621 622 def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); 623 624 if (adev->asic_type != CHIP_RAVEN) { 625 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 626 def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2); 627 } else 628 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV); 629 630 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 631 data |= ATC_L2_MISC_CG__ENABLE_MASK; 632 633 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 634 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 635 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 636 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 637 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 638 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 639 640 if (adev->asic_type != CHIP_RAVEN) 641 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 642 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 643 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 644 DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 645 DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 646 DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 647 } else { 648 data &= ~ATC_L2_MISC_CG__ENABLE_MASK; 649 650 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 651 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 652 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 653 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 654 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 655 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 656 657 if (adev->asic_type != CHIP_RAVEN) 658 data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 659 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 660 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 661 DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 662 DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 663 DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 664 } 665 666 if (def != data) 667 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data); 668 669 if (def1 != data1) { 670 if (adev->asic_type != CHIP_RAVEN) 671 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1); 672 else 673 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1); 674 } 675 676 if (adev->asic_type != CHIP_RAVEN && def2 != data2) 677 WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2); 678 } 679 680 static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev, 681 bool enable) 682 { 683 uint32_t def, data; 684 685 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); 686 687 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) 688 data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK; 689 else 690 data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK; 691 692 if (def != data) 693 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data); 694 } 695 696 static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 697 bool enable) 698 { 699 uint32_t def, data; 700 701 def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); 702 703 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 704 data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 705 else 706 data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 707 708 if (def != data) 709 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data); 710 } 711 712 static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev, 713 bool enable) 714 { 715 uint32_t def, data; 716 717 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); 718 719 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) && 720 (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 721 data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; 722 else 723 data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; 724 725 if(def != data) 726 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data); 727 } 728 729 int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev, 730 enum amd_clockgating_state state) 731 { 732 if (amdgpu_sriov_vf(adev)) 733 return 0; 734 735 switch (adev->asic_type) { 736 case CHIP_VEGA10: 737 case CHIP_VEGA12: 738 case CHIP_VEGA20: 739 case CHIP_RAVEN: 740 mmhub_v1_0_update_medium_grain_clock_gating(adev, 741 state == AMD_CG_STATE_GATE ? true : false); 742 athub_update_medium_grain_clock_gating(adev, 743 state == AMD_CG_STATE_GATE ? true : false); 744 mmhub_v1_0_update_medium_grain_light_sleep(adev, 745 state == AMD_CG_STATE_GATE ? true : false); 746 athub_update_medium_grain_light_sleep(adev, 747 state == AMD_CG_STATE_GATE ? true : false); 748 break; 749 default: 750 break; 751 } 752 753 return 0; 754 } 755 756 void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) 757 { 758 int data; 759 760 if (amdgpu_sriov_vf(adev)) 761 *flags = 0; 762 763 /* AMD_CG_SUPPORT_MC_MGCG */ 764 data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); 765 if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK) 766 *flags |= AMD_CG_SUPPORT_MC_MGCG; 767 768 /* AMD_CG_SUPPORT_MC_LS */ 769 data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); 770 if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 771 *flags |= AMD_CG_SUPPORT_MC_LS; 772 } 773