1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2017 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev */ 23*b843c749SSergey Zigachev 24*b843c749SSergey Zigachev #ifndef _PSP_TEE_GFX_IF_H_ 25*b843c749SSergey Zigachev #define _PSP_TEE_GFX_IF_H_ 26*b843c749SSergey Zigachev 27*b843c749SSergey Zigachev #define PSP_GFX_CMD_BUF_VERSION 0x00000001 28*b843c749SSergey Zigachev 29*b843c749SSergey Zigachev #define GFX_CMD_STATUS_MASK 0x0000FFFF 30*b843c749SSergey Zigachev #define GFX_CMD_ID_MASK 0x000F0000 31*b843c749SSergey Zigachev #define GFX_CMD_RESERVED_MASK 0x7FF00000 32*b843c749SSergey Zigachev #define GFX_CMD_RESPONSE_MASK 0x80000000 33*b843c749SSergey Zigachev 34*b843c749SSergey Zigachev /* TEE Gfx Command IDs for the register interface. 35*b843c749SSergey Zigachev * Command ID must be between 0x00010000 and 0x000F0000. 36*b843c749SSergey Zigachev */ 37*b843c749SSergey Zigachev enum psp_gfx_crtl_cmd_id 38*b843c749SSergey Zigachev { 39*b843c749SSergey Zigachev GFX_CTRL_CMD_ID_INIT_RBI_RING = 0x00010000, /* initialize RBI ring */ 40*b843c749SSergey Zigachev GFX_CTRL_CMD_ID_INIT_GPCOM_RING = 0x00020000, /* initialize GPCOM ring */ 41*b843c749SSergey Zigachev GFX_CTRL_CMD_ID_DESTROY_RINGS = 0x00030000, /* destroy rings */ 42*b843c749SSergey Zigachev GFX_CTRL_CMD_ID_CAN_INIT_RINGS = 0x00040000, /* is it allowed to initialized the rings */ 43*b843c749SSergey Zigachev GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */ 44*b843c749SSergey Zigachev GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */ 45*b843c749SSergey Zigachev GFX_CTRL_CMD_ID_MODE1_RST = 0x00070000, /* trigger the Mode 1 reset */ 46*b843c749SSergey Zigachev 47*b843c749SSergey Zigachev GFX_CTRL_CMD_ID_MAX = 0x000F0000, /* max command ID */ 48*b843c749SSergey Zigachev }; 49*b843c749SSergey Zigachev 50*b843c749SSergey Zigachev 51*b843c749SSergey Zigachev /*----------------------------------------------------------------------------- 52*b843c749SSergey Zigachev NOTE: All physical addresses used in this interface are actually 53*b843c749SSergey Zigachev GPU Virtual Addresses. 54*b843c749SSergey Zigachev */ 55*b843c749SSergey Zigachev 56*b843c749SSergey Zigachev 57*b843c749SSergey Zigachev /* Control registers of the TEE Gfx interface. These are located in 58*b843c749SSergey Zigachev * SRBM-to-PSP mailbox registers (total 8 registers). 59*b843c749SSergey Zigachev */ 60*b843c749SSergey Zigachev struct psp_gfx_ctrl 61*b843c749SSergey Zigachev { 62*b843c749SSergey Zigachev volatile uint32_t cmd_resp; /* +0 Command/Response register for Gfx commands */ 63*b843c749SSergey Zigachev volatile uint32_t rbi_wptr; /* +4 Write pointer (index) of RBI ring */ 64*b843c749SSergey Zigachev volatile uint32_t rbi_rptr; /* +8 Read pointer (index) of RBI ring */ 65*b843c749SSergey Zigachev volatile uint32_t gpcom_wptr; /* +12 Write pointer (index) of GPCOM ring */ 66*b843c749SSergey Zigachev volatile uint32_t gpcom_rptr; /* +16 Read pointer (index) of GPCOM ring */ 67*b843c749SSergey Zigachev volatile uint32_t ring_addr_lo; /* +20 bits [31:0] of GPU Virtual of ring buffer (VMID=0)*/ 68*b843c749SSergey Zigachev volatile uint32_t ring_addr_hi; /* +24 bits [63:32] of GPU Virtual of ring buffer (VMID=0) */ 69*b843c749SSergey Zigachev volatile uint32_t ring_buf_size; /* +28 Ring buffer size (in bytes) */ 70*b843c749SSergey Zigachev 71*b843c749SSergey Zigachev }; 72*b843c749SSergey Zigachev 73*b843c749SSergey Zigachev 74*b843c749SSergey Zigachev /* Response flag is set in the command when command is completed by PSP. 75*b843c749SSergey Zigachev * Used in the GFX_CTRL.CmdResp. 76*b843c749SSergey Zigachev * When PSP GFX I/F is initialized, the flag is set. 77*b843c749SSergey Zigachev */ 78*b843c749SSergey Zigachev #define GFX_FLAG_RESPONSE 0x80000000 79*b843c749SSergey Zigachev 80*b843c749SSergey Zigachev 81*b843c749SSergey Zigachev /* TEE Gfx Command IDs for the ring buffer interface. */ 82*b843c749SSergey Zigachev enum psp_gfx_cmd_id 83*b843c749SSergey Zigachev { 84*b843c749SSergey Zigachev GFX_CMD_ID_LOAD_TA = 0x00000001, /* load TA */ 85*b843c749SSergey Zigachev GFX_CMD_ID_UNLOAD_TA = 0x00000002, /* unload TA */ 86*b843c749SSergey Zigachev GFX_CMD_ID_INVOKE_CMD = 0x00000003, /* send command to TA */ 87*b843c749SSergey Zigachev GFX_CMD_ID_LOAD_ASD = 0x00000004, /* load ASD Driver */ 88*b843c749SSergey Zigachev GFX_CMD_ID_SETUP_TMR = 0x00000005, /* setup TMR region */ 89*b843c749SSergey Zigachev GFX_CMD_ID_LOAD_IP_FW = 0x00000006, /* load HW IP FW */ 90*b843c749SSergey Zigachev GFX_CMD_ID_DESTROY_TMR = 0x00000007, /* destroy TMR region */ 91*b843c749SSergey Zigachev GFX_CMD_ID_SAVE_RESTORE = 0x00000008, /* save/restore HW IP FW */ 92*b843c749SSergey Zigachev 93*b843c749SSergey Zigachev }; 94*b843c749SSergey Zigachev 95*b843c749SSergey Zigachev 96*b843c749SSergey Zigachev /* Command to load Trusted Application binary into PSP OS. */ 97*b843c749SSergey Zigachev struct psp_gfx_cmd_load_ta 98*b843c749SSergey Zigachev { 99*b843c749SSergey Zigachev uint32_t app_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of the TA binary (must be 4 KB aligned) */ 100*b843c749SSergey Zigachev uint32_t app_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of the TA binary */ 101*b843c749SSergey Zigachev uint32_t app_len; /* length of the TA binary in bytes */ 102*b843c749SSergey Zigachev uint32_t cmd_buf_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of CMD buffer (must be 4 KB aligned) */ 103*b843c749SSergey Zigachev uint32_t cmd_buf_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of CMD buffer */ 104*b843c749SSergey Zigachev uint32_t cmd_buf_len; /* length of the CMD buffer in bytes; must be multiple of 4 KB */ 105*b843c749SSergey Zigachev 106*b843c749SSergey Zigachev /* Note: CmdBufLen can be set to 0. In this case no persistent CMD buffer is provided 107*b843c749SSergey Zigachev * for the TA. Each InvokeCommand can have dinamically mapped CMD buffer instead 108*b843c749SSergey Zigachev * of using global persistent buffer. 109*b843c749SSergey Zigachev */ 110*b843c749SSergey Zigachev }; 111*b843c749SSergey Zigachev 112*b843c749SSergey Zigachev 113*b843c749SSergey Zigachev /* Command to Unload Trusted Application binary from PSP OS. */ 114*b843c749SSergey Zigachev struct psp_gfx_cmd_unload_ta 115*b843c749SSergey Zigachev { 116*b843c749SSergey Zigachev uint32_t session_id; /* Session ID of the loaded TA to be unloaded */ 117*b843c749SSergey Zigachev 118*b843c749SSergey Zigachev }; 119*b843c749SSergey Zigachev 120*b843c749SSergey Zigachev 121*b843c749SSergey Zigachev /* Shared buffers for InvokeCommand. 122*b843c749SSergey Zigachev */ 123*b843c749SSergey Zigachev struct psp_gfx_buf_desc 124*b843c749SSergey Zigachev { 125*b843c749SSergey Zigachev uint32_t buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of the buffer (must be 4 KB aligned) */ 126*b843c749SSergey Zigachev uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of the buffer */ 127*b843c749SSergey Zigachev uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB and no bigger than 64 MB) */ 128*b843c749SSergey Zigachev 129*b843c749SSergey Zigachev }; 130*b843c749SSergey Zigachev 131*b843c749SSergey Zigachev /* Max number of descriptors for one shared buffer (in how many different 132*b843c749SSergey Zigachev * physical locations one shared buffer can be stored). If buffer is too much 133*b843c749SSergey Zigachev * fragmented, error will be returned. 134*b843c749SSergey Zigachev */ 135*b843c749SSergey Zigachev #define GFX_BUF_MAX_DESC 64 136*b843c749SSergey Zigachev 137*b843c749SSergey Zigachev struct psp_gfx_buf_list 138*b843c749SSergey Zigachev { 139*b843c749SSergey Zigachev uint32_t num_desc; /* number of buffer descriptors in the list */ 140*b843c749SSergey Zigachev uint32_t total_size; /* total size of all buffers in the list in bytes (must be multiple of 4 KB) */ 141*b843c749SSergey Zigachev struct psp_gfx_buf_desc buf_desc[GFX_BUF_MAX_DESC]; /* list of buffer descriptors */ 142*b843c749SSergey Zigachev 143*b843c749SSergey Zigachev /* total 776 bytes */ 144*b843c749SSergey Zigachev }; 145*b843c749SSergey Zigachev 146*b843c749SSergey Zigachev /* Command to execute InvokeCommand entry point of the TA. */ 147*b843c749SSergey Zigachev struct psp_gfx_cmd_invoke_cmd 148*b843c749SSergey Zigachev { 149*b843c749SSergey Zigachev uint32_t session_id; /* Session ID of the TA to be executed */ 150*b843c749SSergey Zigachev uint32_t ta_cmd_id; /* Command ID to be sent to TA */ 151*b843c749SSergey Zigachev struct psp_gfx_buf_list buf; /* one indirect buffer (scatter/gather list) */ 152*b843c749SSergey Zigachev 153*b843c749SSergey Zigachev }; 154*b843c749SSergey Zigachev 155*b843c749SSergey Zigachev 156*b843c749SSergey Zigachev /* Command to setup TMR region. */ 157*b843c749SSergey Zigachev struct psp_gfx_cmd_setup_tmr 158*b843c749SSergey Zigachev { 159*b843c749SSergey Zigachev uint32_t buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of TMR buffer (must be 4 KB aligned) */ 160*b843c749SSergey Zigachev uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of TMR buffer */ 161*b843c749SSergey Zigachev uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB) */ 162*b843c749SSergey Zigachev 163*b843c749SSergey Zigachev }; 164*b843c749SSergey Zigachev 165*b843c749SSergey Zigachev 166*b843c749SSergey Zigachev /* FW types for GFX_CMD_ID_LOAD_IP_FW command. Limit 31. */ 167*b843c749SSergey Zigachev enum psp_gfx_fw_type 168*b843c749SSergey Zigachev { 169*b843c749SSergey Zigachev GFX_FW_TYPE_NONE = 0, 170*b843c749SSergey Zigachev GFX_FW_TYPE_CP_ME = 1, 171*b843c749SSergey Zigachev GFX_FW_TYPE_CP_PFP = 2, 172*b843c749SSergey Zigachev GFX_FW_TYPE_CP_CE = 3, 173*b843c749SSergey Zigachev GFX_FW_TYPE_CP_MEC = 4, 174*b843c749SSergey Zigachev GFX_FW_TYPE_CP_MEC_ME1 = 5, 175*b843c749SSergey Zigachev GFX_FW_TYPE_CP_MEC_ME2 = 6, 176*b843c749SSergey Zigachev GFX_FW_TYPE_RLC_V = 7, 177*b843c749SSergey Zigachev GFX_FW_TYPE_RLC_G = 8, 178*b843c749SSergey Zigachev GFX_FW_TYPE_SDMA0 = 9, 179*b843c749SSergey Zigachev GFX_FW_TYPE_SDMA1 = 10, 180*b843c749SSergey Zigachev GFX_FW_TYPE_DMCU_ERAM = 11, 181*b843c749SSergey Zigachev GFX_FW_TYPE_DMCU_ISR = 12, 182*b843c749SSergey Zigachev GFX_FW_TYPE_VCN = 13, 183*b843c749SSergey Zigachev GFX_FW_TYPE_UVD = 14, 184*b843c749SSergey Zigachev GFX_FW_TYPE_VCE = 15, 185*b843c749SSergey Zigachev GFX_FW_TYPE_ISP = 16, 186*b843c749SSergey Zigachev GFX_FW_TYPE_ACP = 17, 187*b843c749SSergey Zigachev GFX_FW_TYPE_SMU = 18, 188*b843c749SSergey Zigachev GFX_FW_TYPE_MMSCH = 19, 189*b843c749SSergey Zigachev GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM = 20, 190*b843c749SSergey Zigachev GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM = 21, 191*b843c749SSergey Zigachev GFX_FW_TYPE_RLC_RESTORE_LIST_CNTL = 22, 192*b843c749SSergey Zigachev GFX_FW_TYPE_MAX = 23 193*b843c749SSergey Zigachev }; 194*b843c749SSergey Zigachev 195*b843c749SSergey Zigachev /* Command to load HW IP FW. */ 196*b843c749SSergey Zigachev struct psp_gfx_cmd_load_ip_fw 197*b843c749SSergey Zigachev { 198*b843c749SSergey Zigachev uint32_t fw_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */ 199*b843c749SSergey Zigachev uint32_t fw_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */ 200*b843c749SSergey Zigachev uint32_t fw_size; /* FW buffer size in bytes */ 201*b843c749SSergey Zigachev enum psp_gfx_fw_type fw_type; /* FW type */ 202*b843c749SSergey Zigachev 203*b843c749SSergey Zigachev }; 204*b843c749SSergey Zigachev 205*b843c749SSergey Zigachev /* Command to save/restore HW IP FW. */ 206*b843c749SSergey Zigachev struct psp_gfx_cmd_save_restore_ip_fw 207*b843c749SSergey Zigachev { 208*b843c749SSergey Zigachev uint32_t save_fw; /* if set, command is used for saving fw otherwise for resetoring*/ 209*b843c749SSergey Zigachev uint32_t save_restore_addr_lo; /* bits [31:0] of FB address of GART memory used as save/restore buffer (must be 4 KB aligned) */ 210*b843c749SSergey Zigachev uint32_t save_restore_addr_hi; /* bits [63:32] of FB address of GART memory used as save/restore buffer */ 211*b843c749SSergey Zigachev uint32_t buf_size; /* Size of the save/restore buffer in bytes */ 212*b843c749SSergey Zigachev enum psp_gfx_fw_type fw_type; /* FW type */ 213*b843c749SSergey Zigachev }; 214*b843c749SSergey Zigachev 215*b843c749SSergey Zigachev /* All GFX ring buffer commands. */ 216*b843c749SSergey Zigachev union psp_gfx_commands 217*b843c749SSergey Zigachev { 218*b843c749SSergey Zigachev struct psp_gfx_cmd_load_ta cmd_load_ta; 219*b843c749SSergey Zigachev struct psp_gfx_cmd_unload_ta cmd_unload_ta; 220*b843c749SSergey Zigachev struct psp_gfx_cmd_invoke_cmd cmd_invoke_cmd; 221*b843c749SSergey Zigachev struct psp_gfx_cmd_setup_tmr cmd_setup_tmr; 222*b843c749SSergey Zigachev struct psp_gfx_cmd_load_ip_fw cmd_load_ip_fw; 223*b843c749SSergey Zigachev struct psp_gfx_cmd_save_restore_ip_fw cmd_save_restore_ip_fw; 224*b843c749SSergey Zigachev }; 225*b843c749SSergey Zigachev 226*b843c749SSergey Zigachev 227*b843c749SSergey Zigachev /* Structure of GFX Response buffer. 228*b843c749SSergey Zigachev * For GPCOM I/F it is part of GFX_CMD_RESP buffer, for RBI 229*b843c749SSergey Zigachev * it is separate buffer. 230*b843c749SSergey Zigachev */ 231*b843c749SSergey Zigachev struct psp_gfx_resp 232*b843c749SSergey Zigachev { 233*b843c749SSergey Zigachev uint32_t status; /* +0 status of command execution */ 234*b843c749SSergey Zigachev uint32_t session_id; /* +4 session ID in response to LoadTa command */ 235*b843c749SSergey Zigachev uint32_t fw_addr_lo; /* +8 bits [31:0] of FW address within TMR (in response to cmd_load_ip_fw command) */ 236*b843c749SSergey Zigachev uint32_t fw_addr_hi; /* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw command) */ 237*b843c749SSergey Zigachev 238*b843c749SSergey Zigachev uint32_t reserved[4]; 239*b843c749SSergey Zigachev 240*b843c749SSergey Zigachev /* total 32 bytes */ 241*b843c749SSergey Zigachev }; 242*b843c749SSergey Zigachev 243*b843c749SSergey Zigachev /* Structure of Command buffer pointed by psp_gfx_rb_frame.cmd_buf_addr_hi 244*b843c749SSergey Zigachev * and psp_gfx_rb_frame.cmd_buf_addr_lo. 245*b843c749SSergey Zigachev */ 246*b843c749SSergey Zigachev struct psp_gfx_cmd_resp 247*b843c749SSergey Zigachev { 248*b843c749SSergey Zigachev uint32_t buf_size; /* +0 total size of the buffer in bytes */ 249*b843c749SSergey Zigachev uint32_t buf_version; /* +4 version of the buffer strusture; must be PSP_GFX_CMD_BUF_VERSION */ 250*b843c749SSergey Zigachev uint32_t cmd_id; /* +8 command ID */ 251*b843c749SSergey Zigachev 252*b843c749SSergey Zigachev /* These fields are used for RBI only. They are all 0 in GPCOM commands 253*b843c749SSergey Zigachev */ 254*b843c749SSergey Zigachev uint32_t resp_buf_addr_lo; /* +12 bits [31:0] of GPU Virtual address of response buffer (must be 4 KB aligned) */ 255*b843c749SSergey Zigachev uint32_t resp_buf_addr_hi; /* +16 bits [63:32] of GPU Virtual address of response buffer */ 256*b843c749SSergey Zigachev uint32_t resp_offset; /* +20 offset within response buffer */ 257*b843c749SSergey Zigachev uint32_t resp_buf_size; /* +24 total size of the response buffer in bytes */ 258*b843c749SSergey Zigachev 259*b843c749SSergey Zigachev union psp_gfx_commands cmd; /* +28 command specific structures */ 260*b843c749SSergey Zigachev 261*b843c749SSergey Zigachev uint8_t reserved_1[864 - sizeof(union psp_gfx_commands) - 28]; 262*b843c749SSergey Zigachev 263*b843c749SSergey Zigachev /* Note: Resp is part of this buffer for GPCOM ring. For RBI ring the response 264*b843c749SSergey Zigachev * is separate buffer pointed by resp_buf_addr_hi and resp_buf_addr_lo. 265*b843c749SSergey Zigachev */ 266*b843c749SSergey Zigachev struct psp_gfx_resp resp; /* +864 response */ 267*b843c749SSergey Zigachev 268*b843c749SSergey Zigachev uint8_t reserved_2[1024 - 864 - sizeof(struct psp_gfx_resp)]; 269*b843c749SSergey Zigachev 270*b843c749SSergey Zigachev /* total size 1024 bytes */ 271*b843c749SSergey Zigachev }; 272*b843c749SSergey Zigachev 273*b843c749SSergey Zigachev 274*b843c749SSergey Zigachev #define FRAME_TYPE_DESTROY 1 /* frame sent by KMD driver when UMD Scheduler context is destroyed*/ 275*b843c749SSergey Zigachev 276*b843c749SSergey Zigachev /* Structure of the Ring Buffer Frame */ 277*b843c749SSergey Zigachev struct psp_gfx_rb_frame 278*b843c749SSergey Zigachev { 279*b843c749SSergey Zigachev uint32_t cmd_buf_addr_lo; /* +0 bits [31:0] of GPU Virtual address of command buffer (must be 4 KB aligned) */ 280*b843c749SSergey Zigachev uint32_t cmd_buf_addr_hi; /* +4 bits [63:32] of GPU Virtual address of command buffer */ 281*b843c749SSergey Zigachev uint32_t cmd_buf_size; /* +8 command buffer size in bytes */ 282*b843c749SSergey Zigachev uint32_t fence_addr_lo; /* +12 bits [31:0] of GPU Virtual address of Fence for this frame */ 283*b843c749SSergey Zigachev uint32_t fence_addr_hi; /* +16 bits [63:32] of GPU Virtual address of Fence for this frame */ 284*b843c749SSergey Zigachev uint32_t fence_value; /* +20 Fence value */ 285*b843c749SSergey Zigachev uint32_t sid_lo; /* +24 bits [31:0] of SID value (used only for RBI frames) */ 286*b843c749SSergey Zigachev uint32_t sid_hi; /* +28 bits [63:32] of SID value (used only for RBI frames) */ 287*b843c749SSergey Zigachev uint8_t vmid; /* +32 VMID value used for mapping of all addresses for this frame */ 288*b843c749SSergey Zigachev uint8_t frame_type; /* +33 1: destory context frame, 0: all other frames; used only for RBI frames */ 289*b843c749SSergey Zigachev uint8_t reserved1[2]; /* +34 reserved, must be 0 */ 290*b843c749SSergey Zigachev uint32_t reserved2[7]; /* +36 reserved, must be 0 */ 291*b843c749SSergey Zigachev /* total 64 bytes */ 292*b843c749SSergey Zigachev }; 293*b843c749SSergey Zigachev 294*b843c749SSergey Zigachev #endif /* _PSP_TEE_GFX_IF_H_ */ 295