1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 #include "vi.h" 30 #include "vid.h" 31 32 #include "oss/oss_2_4_d.h" 33 #include "oss/oss_2_4_sh_mask.h" 34 35 #include "gmc/gmc_7_1_d.h" 36 #include "gmc/gmc_7_1_sh_mask.h" 37 38 #include "gca/gfx_8_0_d.h" 39 #include "gca/gfx_8_0_enum.h" 40 #include "gca/gfx_8_0_sh_mask.h" 41 42 #include "bif/bif_5_0_d.h" 43 #include "bif/bif_5_0_sh_mask.h" 44 45 #include "iceland_sdma_pkt_open.h" 46 47 #include "ivsrcid/ivsrcid_vislands30.h" 48 49 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev); 50 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev); 51 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev); 52 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev); 53 54 MODULE_FIRMWARE("amdgpufw_topaz_sdma"); 55 MODULE_FIRMWARE("amdgpufw_topaz_sdma1"); 56 57 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 58 { 59 SDMA0_REGISTER_OFFSET, 60 SDMA1_REGISTER_OFFSET 61 }; 62 63 static const u32 golden_settings_iceland_a11[] = 64 { 65 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 66 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 67 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 68 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 69 }; 70 71 static const u32 iceland_mgcg_cgcg_init[] = 72 { 73 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 74 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 75 }; 76 77 /* 78 * sDMA - System DMA 79 * Starting with CIK, the GPU has new asynchronous 80 * DMA engines. These engines are used for compute 81 * and gfx. There are two DMA engines (SDMA0, SDMA1) 82 * and each one supports 1 ring buffer used for gfx 83 * and 2 queues used for compute. 84 * 85 * The programming model is very similar to the CP 86 * (ring buffer, IBs, etc.), but sDMA has it's own 87 * packet format that is different from the PM4 format 88 * used by the CP. sDMA supports copying data, writing 89 * embedded data, solid fills, and a number of other 90 * things. It also has support for tiling/detiling of 91 * buffers. 92 */ 93 94 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev) 95 { 96 switch (adev->asic_type) { 97 case CHIP_TOPAZ: 98 amdgpu_device_program_register_sequence(adev, 99 iceland_mgcg_cgcg_init, 100 ARRAY_SIZE(iceland_mgcg_cgcg_init)); 101 amdgpu_device_program_register_sequence(adev, 102 golden_settings_iceland_a11, 103 ARRAY_SIZE(golden_settings_iceland_a11)); 104 break; 105 default: 106 break; 107 } 108 } 109 110 static void sdma_v2_4_free_microcode(struct amdgpu_device *adev) 111 { 112 int i; 113 for (i = 0; i < adev->sdma.num_instances; i++) { 114 release_firmware(adev->sdma.instance[i].fw); 115 adev->sdma.instance[i].fw = NULL; 116 } 117 } 118 119 /** 120 * sdma_v2_4_init_microcode - load ucode images from disk 121 * 122 * @adev: amdgpu_device pointer 123 * 124 * Use the firmware interface to load the ucode images into 125 * the driver (not loaded into hw). 126 * Returns 0 on success, error on failure. 127 */ 128 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev) 129 { 130 const char *chip_name; 131 char fw_name[30]; 132 int err = 0, i; 133 struct amdgpu_firmware_info *info = NULL; 134 const struct common_firmware_header *header = NULL; 135 const struct sdma_firmware_header_v1_0 *hdr; 136 137 DRM_DEBUG("\n"); 138 139 switch (adev->asic_type) { 140 case CHIP_TOPAZ: 141 chip_name = "topaz"; 142 break; 143 default: BUG(); 144 } 145 146 for (i = 0; i < adev->sdma.num_instances; i++) { 147 if (i == 0) 148 snprintf(fw_name, sizeof(fw_name), "amdgpufw_%s_sdma", chip_name); 149 else 150 snprintf(fw_name, sizeof(fw_name), "amdgpufw_%s_sdma1", chip_name); 151 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 152 if (err) 153 goto out; 154 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 155 if (err) 156 goto out; 157 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 158 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 159 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 160 if (adev->sdma.instance[i].feature_version >= 20) 161 adev->sdma.instance[i].burst_nop = true; 162 163 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) { 164 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 165 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 166 info->fw = adev->sdma.instance[i].fw; 167 header = (const struct common_firmware_header *)info->fw->data; 168 adev->firmware.fw_size += 169 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 170 } 171 } 172 173 out: 174 if (err) { 175 pr_err("sdma_v2_4: Failed to load firmware \"%s\"\n", fw_name); 176 for (i = 0; i < adev->sdma.num_instances; i++) { 177 release_firmware(adev->sdma.instance[i].fw); 178 adev->sdma.instance[i].fw = NULL; 179 } 180 } 181 return err; 182 } 183 184 /** 185 * sdma_v2_4_ring_get_rptr - get the current read pointer 186 * 187 * @ring: amdgpu ring pointer 188 * 189 * Get the current rptr from the hardware (VI+). 190 */ 191 static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring) 192 { 193 /* XXX check if swapping is necessary on BE */ 194 return ring->adev->wb.wb[ring->rptr_offs] >> 2; 195 } 196 197 /** 198 * sdma_v2_4_ring_get_wptr - get the current write pointer 199 * 200 * @ring: amdgpu ring pointer 201 * 202 * Get the current wptr from the hardware (VI+). 203 */ 204 static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring) 205 { 206 struct amdgpu_device *adev = ring->adev; 207 u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; 208 209 return wptr; 210 } 211 212 /** 213 * sdma_v2_4_ring_set_wptr - commit the write pointer 214 * 215 * @ring: amdgpu ring pointer 216 * 217 * Write the wptr back to the hardware (VI+). 218 */ 219 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring) 220 { 221 struct amdgpu_device *adev = ring->adev; 222 223 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2); 224 } 225 226 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 227 { 228 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 229 int i; 230 231 for (i = 0; i < count; i++) 232 if (sdma && sdma->burst_nop && (i == 0)) 233 amdgpu_ring_write(ring, ring->funcs->nop | 234 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 235 else 236 amdgpu_ring_write(ring, ring->funcs->nop); 237 } 238 239 /** 240 * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine 241 * 242 * @ring: amdgpu ring pointer 243 * @ib: IB object to schedule 244 * 245 * Schedule an IB in the DMA ring (VI). 246 */ 247 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring, 248 struct amdgpu_ib *ib, 249 unsigned vmid, bool ctx_switch) 250 { 251 /* IB packet must end on a 8 DW boundary */ 252 sdma_v2_4_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 253 254 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 255 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 256 /* base must be 32 byte aligned */ 257 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 258 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 259 amdgpu_ring_write(ring, ib->length_dw); 260 amdgpu_ring_write(ring, 0); 261 amdgpu_ring_write(ring, 0); 262 263 } 264 265 /** 266 * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring 267 * 268 * @ring: amdgpu ring pointer 269 * 270 * Emit an hdp flush packet on the requested DMA ring. 271 */ 272 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring) 273 { 274 u32 ref_and_mask = 0; 275 276 if (ring->me == 0) 277 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 278 else 279 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 280 281 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 282 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 283 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 284 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 285 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 286 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 287 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 288 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 289 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 290 } 291 292 /** 293 * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring 294 * 295 * @ring: amdgpu ring pointer 296 * @fence: amdgpu fence object 297 * 298 * Add a DMA fence packet to the ring to write 299 * the fence seq number and DMA trap packet to generate 300 * an interrupt if needed (VI). 301 */ 302 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, uint64_t addr, uint64_t seq, 303 unsigned flags) 304 { 305 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 306 /* write the fence */ 307 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 308 amdgpu_ring_write(ring, lower_32_bits(addr)); 309 amdgpu_ring_write(ring, upper_32_bits(addr)); 310 amdgpu_ring_write(ring, lower_32_bits(seq)); 311 312 /* optionally write high bits as well */ 313 if (write64bit) { 314 addr += 4; 315 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 316 amdgpu_ring_write(ring, lower_32_bits(addr)); 317 amdgpu_ring_write(ring, upper_32_bits(addr)); 318 amdgpu_ring_write(ring, upper_32_bits(seq)); 319 } 320 321 /* generate an interrupt */ 322 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 323 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 324 } 325 326 /** 327 * sdma_v2_4_gfx_stop - stop the gfx async dma engines 328 * 329 * @adev: amdgpu_device pointer 330 * 331 * Stop the gfx async dma ring buffers (VI). 332 */ 333 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev) 334 { 335 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 336 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 337 u32 rb_cntl, ib_cntl; 338 int i; 339 340 if ((adev->mman.buffer_funcs_ring == sdma0) || 341 (adev->mman.buffer_funcs_ring == sdma1)) 342 amdgpu_ttm_set_buffer_funcs_status(adev, false); 343 344 for (i = 0; i < adev->sdma.num_instances; i++) { 345 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 346 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 347 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 348 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 349 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 350 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 351 } 352 sdma0->ready = false; 353 sdma1->ready = false; 354 } 355 356 /** 357 * sdma_v2_4_rlc_stop - stop the compute async dma engines 358 * 359 * @adev: amdgpu_device pointer 360 * 361 * Stop the compute async dma queues (VI). 362 */ 363 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev) 364 { 365 /* XXX todo */ 366 } 367 368 /** 369 * sdma_v2_4_enable - stop the async dma engines 370 * 371 * @adev: amdgpu_device pointer 372 * @enable: enable/disable the DMA MEs. 373 * 374 * Halt or unhalt the async dma engines (VI). 375 */ 376 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable) 377 { 378 u32 f32_cntl; 379 int i; 380 381 if (!enable) { 382 sdma_v2_4_gfx_stop(adev); 383 sdma_v2_4_rlc_stop(adev); 384 } 385 386 for (i = 0; i < adev->sdma.num_instances; i++) { 387 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 388 if (enable) 389 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 390 else 391 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 392 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); 393 } 394 } 395 396 /** 397 * sdma_v2_4_gfx_resume - setup and start the async dma engines 398 * 399 * @adev: amdgpu_device pointer 400 * 401 * Set up the gfx DMA ring buffers and enable them (VI). 402 * Returns 0 for success, error for failure. 403 */ 404 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev) 405 { 406 struct amdgpu_ring *ring; 407 u32 rb_cntl, ib_cntl; 408 u32 rb_bufsz; 409 u32 wb_offset; 410 int i, j, r; 411 412 for (i = 0; i < adev->sdma.num_instances; i++) { 413 ring = &adev->sdma.instance[i].ring; 414 wb_offset = (ring->rptr_offs * 4); 415 416 mutex_lock(&adev->srbm_mutex); 417 for (j = 0; j < 16; j++) { 418 vi_srbm_select(adev, 0, 0, 0, j); 419 /* SDMA GFX */ 420 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 421 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 422 } 423 vi_srbm_select(adev, 0, 0, 0, 0); 424 mutex_unlock(&adev->srbm_mutex); 425 426 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], 427 adev->gfx.config.gb_addr_config & 0x70); 428 429 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 430 431 /* Set ring buffer size in dwords */ 432 rb_bufsz = order_base_2(ring->ring_size / 4); 433 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 434 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 435 #ifdef __BIG_ENDIAN 436 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 437 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 438 RPTR_WRITEBACK_SWAP_ENABLE, 1); 439 #endif 440 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 441 442 /* Initialize the ring buffer's read and write pointers */ 443 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 444 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 445 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); 446 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); 447 448 /* set the wb address whether it's enabled or not */ 449 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 450 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 451 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 452 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 453 454 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 455 456 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 457 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 458 459 ring->wptr = 0; 460 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); 461 462 /* enable DMA RB */ 463 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 464 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 465 466 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 467 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 468 #ifdef __BIG_ENDIAN 469 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 470 #endif 471 /* enable DMA IBs */ 472 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 473 474 ring->ready = true; 475 } 476 477 sdma_v2_4_enable(adev, true); 478 for (i = 0; i < adev->sdma.num_instances; i++) { 479 ring = &adev->sdma.instance[i].ring; 480 r = amdgpu_ring_test_ring(ring); 481 if (r) { 482 ring->ready = false; 483 return r; 484 } 485 486 if (adev->mman.buffer_funcs_ring == ring) 487 amdgpu_ttm_set_buffer_funcs_status(adev, true); 488 } 489 490 return 0; 491 } 492 493 /** 494 * sdma_v2_4_rlc_resume - setup and start the async dma engines 495 * 496 * @adev: amdgpu_device pointer 497 * 498 * Set up the compute DMA queues and enable them (VI). 499 * Returns 0 for success, error for failure. 500 */ 501 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev) 502 { 503 /* XXX todo */ 504 return 0; 505 } 506 507 /** 508 * sdma_v2_4_load_microcode - load the sDMA ME ucode 509 * 510 * @adev: amdgpu_device pointer 511 * 512 * Loads the sDMA0/1 ucode. 513 * Returns 0 for success, -EINVAL if the ucode is not available. 514 */ 515 static int sdma_v2_4_load_microcode(struct amdgpu_device *adev) 516 { 517 const struct sdma_firmware_header_v1_0 *hdr; 518 const __le32 *fw_data; 519 u32 fw_size; 520 int i, j; 521 522 /* halt the MEs */ 523 sdma_v2_4_enable(adev, false); 524 525 for (i = 0; i < adev->sdma.num_instances; i++) { 526 if (!adev->sdma.instance[i].fw) 527 return -EINVAL; 528 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 529 amdgpu_ucode_print_sdma_hdr(&hdr->header); 530 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 531 fw_data = (const __le32 *) 532 (adev->sdma.instance[i].fw->data + 533 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 534 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); 535 for (j = 0; j < fw_size; j++) 536 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); 537 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); 538 } 539 540 return 0; 541 } 542 543 /** 544 * sdma_v2_4_start - setup and start the async dma engines 545 * 546 * @adev: amdgpu_device pointer 547 * 548 * Set up the DMA engines and enable them (VI). 549 * Returns 0 for success, error for failure. 550 */ 551 static int sdma_v2_4_start(struct amdgpu_device *adev) 552 { 553 int r; 554 555 556 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 557 r = sdma_v2_4_load_microcode(adev); 558 if (r) 559 return r; 560 } 561 562 /* halt the engine before programing */ 563 sdma_v2_4_enable(adev, false); 564 565 /* start the gfx rings and rlc compute queues */ 566 r = sdma_v2_4_gfx_resume(adev); 567 if (r) 568 return r; 569 r = sdma_v2_4_rlc_resume(adev); 570 if (r) 571 return r; 572 573 return 0; 574 } 575 576 /** 577 * sdma_v2_4_ring_test_ring - simple async dma engine test 578 * 579 * @ring: amdgpu_ring structure holding ring information 580 * 581 * Test the DMA engine by writing using it to write an 582 * value to memory. (VI). 583 * Returns 0 for success, error for failure. 584 */ 585 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring) 586 { 587 struct amdgpu_device *adev = ring->adev; 588 unsigned i; 589 unsigned index; 590 int r; 591 u32 tmp; 592 u64 gpu_addr; 593 594 r = amdgpu_device_wb_get(adev, &index); 595 if (r) { 596 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 597 return r; 598 } 599 600 gpu_addr = adev->wb.gpu_addr + (index * 4); 601 tmp = 0xCAFEDEAD; 602 adev->wb.wb[index] = cpu_to_le32(tmp); 603 604 r = amdgpu_ring_alloc(ring, 5); 605 if (r) { 606 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 607 amdgpu_device_wb_free(adev, index); 608 return r; 609 } 610 611 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 612 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 613 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 614 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 615 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 616 amdgpu_ring_write(ring, 0xDEADBEEF); 617 amdgpu_ring_commit(ring); 618 619 for (i = 0; i < adev->usec_timeout; i++) { 620 tmp = le32_to_cpu(adev->wb.wb[index]); 621 if (tmp == 0xDEADBEEF) 622 break; 623 DRM_UDELAY(1); 624 } 625 626 if (i < adev->usec_timeout) { 627 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); 628 } else { 629 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 630 ring->idx, tmp); 631 r = -EINVAL; 632 } 633 amdgpu_device_wb_free(adev, index); 634 635 return r; 636 } 637 638 /** 639 * sdma_v2_4_ring_test_ib - test an IB on the DMA engine 640 * 641 * @ring: amdgpu_ring structure holding ring information 642 * 643 * Test a simple IB in the DMA ring (VI). 644 * Returns 0 on success, error on failure. 645 */ 646 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout) 647 { 648 struct amdgpu_device *adev = ring->adev; 649 struct amdgpu_ib ib; 650 struct dma_fence *f = NULL; 651 unsigned index; 652 u32 tmp = 0; 653 u64 gpu_addr; 654 long r; 655 656 r = amdgpu_device_wb_get(adev, &index); 657 if (r) { 658 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 659 return r; 660 } 661 662 gpu_addr = adev->wb.gpu_addr + (index * 4); 663 tmp = 0xCAFEDEAD; 664 adev->wb.wb[index] = cpu_to_le32(tmp); 665 memset(&ib, 0, sizeof(ib)); 666 r = amdgpu_ib_get(adev, NULL, 256, &ib); 667 if (r) { 668 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 669 goto err0; 670 } 671 672 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 673 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 674 ib.ptr[1] = lower_32_bits(gpu_addr); 675 ib.ptr[2] = upper_32_bits(gpu_addr); 676 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); 677 ib.ptr[4] = 0xDEADBEEF; 678 ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 679 ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 680 ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 681 ib.length_dw = 8; 682 683 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 684 if (r) 685 goto err1; 686 687 r = dma_fence_wait_timeout(f, false, timeout); 688 if (r == 0) { 689 DRM_ERROR("amdgpu: IB test timed out\n"); 690 r = -ETIMEDOUT; 691 goto err1; 692 } else if (r < 0) { 693 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 694 goto err1; 695 } 696 tmp = le32_to_cpu(adev->wb.wb[index]); 697 if (tmp == 0xDEADBEEF) { 698 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); 699 r = 0; 700 } else { 701 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 702 r = -EINVAL; 703 } 704 705 err1: 706 amdgpu_ib_free(adev, &ib, NULL); 707 dma_fence_put(f); 708 err0: 709 amdgpu_device_wb_free(adev, index); 710 return r; 711 } 712 713 /** 714 * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART 715 * 716 * @ib: indirect buffer to fill with commands 717 * @pe: addr of the page entry 718 * @src: src addr to copy from 719 * @count: number of page entries to update 720 * 721 * Update PTEs by copying them from the GART using sDMA (CIK). 722 */ 723 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib, 724 uint64_t pe, uint64_t src, 725 unsigned count) 726 { 727 unsigned bytes = count * 8; 728 729 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 730 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 731 ib->ptr[ib->length_dw++] = bytes; 732 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 733 ib->ptr[ib->length_dw++] = lower_32_bits(src); 734 ib->ptr[ib->length_dw++] = upper_32_bits(src); 735 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 736 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 737 } 738 739 /** 740 * sdma_v2_4_vm_write_pte - update PTEs by writing them manually 741 * 742 * @ib: indirect buffer to fill with commands 743 * @pe: addr of the page entry 744 * @value: dst addr to write into pe 745 * @count: number of page entries to update 746 * @incr: increase next addr by incr bytes 747 * 748 * Update PTEs by writing them manually using sDMA (CIK). 749 */ 750 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 751 uint64_t value, unsigned count, 752 uint32_t incr) 753 { 754 unsigned ndw = count * 2; 755 756 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 757 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 758 ib->ptr[ib->length_dw++] = pe; 759 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 760 ib->ptr[ib->length_dw++] = ndw; 761 for (; ndw > 0; ndw -= 2) { 762 ib->ptr[ib->length_dw++] = lower_32_bits(value); 763 ib->ptr[ib->length_dw++] = upper_32_bits(value); 764 value += incr; 765 } 766 } 767 768 /** 769 * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA 770 * 771 * @ib: indirect buffer to fill with commands 772 * @pe: addr of the page entry 773 * @addr: dst addr to write into pe 774 * @count: number of page entries to update 775 * @incr: increase next addr by incr bytes 776 * @flags: access flags 777 * 778 * Update the page tables using sDMA (CIK). 779 */ 780 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, 781 uint64_t addr, unsigned count, 782 uint32_t incr, uint64_t flags) 783 { 784 /* for physically contiguous pages (vram) */ 785 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); 786 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 787 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 788 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 789 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 790 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 791 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 792 ib->ptr[ib->length_dw++] = incr; /* increment size */ 793 ib->ptr[ib->length_dw++] = 0; 794 ib->ptr[ib->length_dw++] = count; /* number of entries */ 795 } 796 797 /** 798 * sdma_v2_4_ring_pad_ib - pad the IB to the required number of dw 799 * 800 * @ib: indirect buffer to fill with padding 801 * 802 */ 803 static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 804 { 805 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 806 u32 pad_count; 807 int i; 808 809 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 810 for (i = 0; i < pad_count; i++) 811 if (sdma && sdma->burst_nop && (i == 0)) 812 ib->ptr[ib->length_dw++] = 813 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 814 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 815 else 816 ib->ptr[ib->length_dw++] = 817 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 818 } 819 820 /** 821 * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline 822 * 823 * @ring: amdgpu_ring pointer 824 * 825 * Make sure all previous operations are completed (CIK). 826 */ 827 static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 828 { 829 uint32_t seq = ring->fence_drv.sync_seq; 830 uint64_t addr = ring->fence_drv.gpu_addr; 831 832 /* wait for idle */ 833 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 834 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 835 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 836 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 837 amdgpu_ring_write(ring, addr & 0xfffffffc); 838 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 839 amdgpu_ring_write(ring, seq); /* reference */ 840 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 841 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 842 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 843 } 844 845 /** 846 * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA 847 * 848 * @ring: amdgpu_ring pointer 849 * @vm: amdgpu_vm pointer 850 * 851 * Update the page table base and flush the VM TLB 852 * using sDMA (VI). 853 */ 854 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring, 855 unsigned vmid, uint64_t pd_addr) 856 { 857 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 858 859 /* wait for flush */ 860 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 861 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 862 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ 863 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 864 amdgpu_ring_write(ring, 0); 865 amdgpu_ring_write(ring, 0); /* reference */ 866 amdgpu_ring_write(ring, 0); /* mask */ 867 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 868 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 869 } 870 871 static void sdma_v2_4_ring_emit_wreg(struct amdgpu_ring *ring, 872 uint32_t reg, uint32_t val) 873 { 874 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 875 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 876 amdgpu_ring_write(ring, reg); 877 amdgpu_ring_write(ring, val); 878 } 879 880 static int sdma_v2_4_early_init(void *handle) 881 { 882 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 883 884 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 885 886 sdma_v2_4_set_ring_funcs(adev); 887 sdma_v2_4_set_buffer_funcs(adev); 888 sdma_v2_4_set_vm_pte_funcs(adev); 889 sdma_v2_4_set_irq_funcs(adev); 890 891 return 0; 892 } 893 894 static int sdma_v2_4_sw_init(void *handle) 895 { 896 struct amdgpu_ring *ring; 897 int r, i; 898 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 899 900 /* SDMA trap event */ 901 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP, 902 &adev->sdma.trap_irq); 903 if (r) 904 return r; 905 906 /* SDMA Privileged inst */ 907 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241, 908 &adev->sdma.illegal_inst_irq); 909 if (r) 910 return r; 911 912 /* SDMA Privileged inst */ 913 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE, 914 &adev->sdma.illegal_inst_irq); 915 if (r) 916 return r; 917 918 r = sdma_v2_4_init_microcode(adev); 919 if (r) { 920 DRM_ERROR("Failed to load sdma firmware!\n"); 921 return r; 922 } 923 924 for (i = 0; i < adev->sdma.num_instances; i++) { 925 ring = &adev->sdma.instance[i].ring; 926 ring->ring_obj = NULL; 927 ring->use_doorbell = false; 928 ksprintf(ring->name, "sdma%d", i); 929 r = amdgpu_ring_init(adev, ring, 1024, 930 &adev->sdma.trap_irq, 931 (i == 0) ? 932 AMDGPU_SDMA_IRQ_TRAP0 : 933 AMDGPU_SDMA_IRQ_TRAP1); 934 if (r) 935 return r; 936 } 937 938 return r; 939 } 940 941 static int sdma_v2_4_sw_fini(void *handle) 942 { 943 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 944 int i; 945 946 for (i = 0; i < adev->sdma.num_instances; i++) 947 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 948 949 sdma_v2_4_free_microcode(adev); 950 return 0; 951 } 952 953 static int sdma_v2_4_hw_init(void *handle) 954 { 955 int r; 956 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 957 958 sdma_v2_4_init_golden_registers(adev); 959 960 r = sdma_v2_4_start(adev); 961 if (r) 962 return r; 963 964 return r; 965 } 966 967 static int sdma_v2_4_hw_fini(void *handle) 968 { 969 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 970 971 sdma_v2_4_enable(adev, false); 972 973 return 0; 974 } 975 976 static int sdma_v2_4_suspend(void *handle) 977 { 978 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 979 980 return sdma_v2_4_hw_fini(adev); 981 } 982 983 static int sdma_v2_4_resume(void *handle) 984 { 985 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 986 987 return sdma_v2_4_hw_init(adev); 988 } 989 990 static bool sdma_v2_4_is_idle(void *handle) 991 { 992 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 993 u32 tmp = RREG32(mmSRBM_STATUS2); 994 995 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 996 SRBM_STATUS2__SDMA1_BUSY_MASK)) 997 return false; 998 999 return true; 1000 } 1001 1002 static int sdma_v2_4_wait_for_idle(void *handle) 1003 { 1004 unsigned i; 1005 u32 tmp; 1006 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1007 1008 for (i = 0; i < adev->usec_timeout; i++) { 1009 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1010 SRBM_STATUS2__SDMA1_BUSY_MASK); 1011 1012 if (!tmp) 1013 return 0; 1014 udelay(1); 1015 } 1016 return -ETIMEDOUT; 1017 } 1018 1019 static int sdma_v2_4_soft_reset(void *handle) 1020 { 1021 u32 srbm_soft_reset = 0; 1022 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1023 u32 tmp = RREG32(mmSRBM_STATUS2); 1024 1025 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { 1026 /* sdma0 */ 1027 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); 1028 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); 1029 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); 1030 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1031 } 1032 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { 1033 /* sdma1 */ 1034 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); 1035 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); 1036 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); 1037 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1038 } 1039 1040 if (srbm_soft_reset) { 1041 tmp = RREG32(mmSRBM_SOFT_RESET); 1042 tmp |= srbm_soft_reset; 1043 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1044 WREG32(mmSRBM_SOFT_RESET, tmp); 1045 tmp = RREG32(mmSRBM_SOFT_RESET); 1046 1047 udelay(50); 1048 1049 tmp &= ~srbm_soft_reset; 1050 WREG32(mmSRBM_SOFT_RESET, tmp); 1051 tmp = RREG32(mmSRBM_SOFT_RESET); 1052 1053 /* Wait a little for things to settle down */ 1054 udelay(50); 1055 } 1056 1057 return 0; 1058 } 1059 1060 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev, 1061 struct amdgpu_irq_src *src, 1062 unsigned type, 1063 enum amdgpu_interrupt_state state) 1064 { 1065 u32 sdma_cntl; 1066 1067 switch (type) { 1068 case AMDGPU_SDMA_IRQ_TRAP0: 1069 switch (state) { 1070 case AMDGPU_IRQ_STATE_DISABLE: 1071 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1072 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1073 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1074 break; 1075 case AMDGPU_IRQ_STATE_ENABLE: 1076 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1077 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1078 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1079 break; 1080 default: 1081 break; 1082 } 1083 break; 1084 case AMDGPU_SDMA_IRQ_TRAP1: 1085 switch (state) { 1086 case AMDGPU_IRQ_STATE_DISABLE: 1087 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1088 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1089 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1090 break; 1091 case AMDGPU_IRQ_STATE_ENABLE: 1092 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1093 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1094 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1095 break; 1096 default: 1097 break; 1098 } 1099 break; 1100 default: 1101 break; 1102 } 1103 return 0; 1104 } 1105 1106 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev, 1107 struct amdgpu_irq_src *source, 1108 struct amdgpu_iv_entry *entry) 1109 { 1110 u8 instance_id, queue_id; 1111 1112 instance_id = (entry->ring_id & 0x3) >> 0; 1113 queue_id = (entry->ring_id & 0xc) >> 2; 1114 DRM_DEBUG("IH: SDMA trap\n"); 1115 switch (instance_id) { 1116 case 0: 1117 switch (queue_id) { 1118 case 0: 1119 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1120 break; 1121 case 1: 1122 /* XXX compute */ 1123 break; 1124 case 2: 1125 /* XXX compute */ 1126 break; 1127 } 1128 break; 1129 case 1: 1130 switch (queue_id) { 1131 case 0: 1132 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1133 break; 1134 case 1: 1135 /* XXX compute */ 1136 break; 1137 case 2: 1138 /* XXX compute */ 1139 break; 1140 } 1141 break; 1142 } 1143 return 0; 1144 } 1145 1146 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev, 1147 struct amdgpu_irq_src *source, 1148 struct amdgpu_iv_entry *entry) 1149 { 1150 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1151 schedule_work(&adev->reset_work); 1152 return 0; 1153 } 1154 1155 static int sdma_v2_4_set_clockgating_state(void *handle, 1156 enum amd_clockgating_state state) 1157 { 1158 /* XXX handled via the smc on VI */ 1159 return 0; 1160 } 1161 1162 static int sdma_v2_4_set_powergating_state(void *handle, 1163 enum amd_powergating_state state) 1164 { 1165 return 0; 1166 } 1167 1168 static const struct amd_ip_funcs sdma_v2_4_ip_funcs = { 1169 .name = "sdma_v2_4", 1170 .early_init = sdma_v2_4_early_init, 1171 .late_init = NULL, 1172 .sw_init = sdma_v2_4_sw_init, 1173 .sw_fini = sdma_v2_4_sw_fini, 1174 .hw_init = sdma_v2_4_hw_init, 1175 .hw_fini = sdma_v2_4_hw_fini, 1176 .suspend = sdma_v2_4_suspend, 1177 .resume = sdma_v2_4_resume, 1178 .is_idle = sdma_v2_4_is_idle, 1179 .wait_for_idle = sdma_v2_4_wait_for_idle, 1180 .soft_reset = sdma_v2_4_soft_reset, 1181 .set_clockgating_state = sdma_v2_4_set_clockgating_state, 1182 .set_powergating_state = sdma_v2_4_set_powergating_state, 1183 }; 1184 1185 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { 1186 .type = AMDGPU_RING_TYPE_SDMA, 1187 .align_mask = 0xf, 1188 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1189 .support_64bit_ptrs = false, 1190 .get_rptr = sdma_v2_4_ring_get_rptr, 1191 .get_wptr = sdma_v2_4_ring_get_wptr, 1192 .set_wptr = sdma_v2_4_ring_set_wptr, 1193 .emit_frame_size = 1194 6 + /* sdma_v2_4_ring_emit_hdp_flush */ 1195 3 + /* hdp invalidate */ 1196 6 + /* sdma_v2_4_ring_emit_pipeline_sync */ 1197 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v2_4_ring_emit_vm_flush */ 1198 10 + 10 + 10, /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */ 1199 .emit_ib_size = 7 + 6, /* sdma_v2_4_ring_emit_ib */ 1200 .emit_ib = sdma_v2_4_ring_emit_ib, 1201 .emit_fence = sdma_v2_4_ring_emit_fence, 1202 .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync, 1203 .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush, 1204 .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush, 1205 .test_ring = sdma_v2_4_ring_test_ring, 1206 .test_ib = sdma_v2_4_ring_test_ib, 1207 .insert_nop = sdma_v2_4_ring_insert_nop, 1208 .pad_ib = sdma_v2_4_ring_pad_ib, 1209 .emit_wreg = sdma_v2_4_ring_emit_wreg, 1210 }; 1211 1212 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev) 1213 { 1214 int i; 1215 1216 for (i = 0; i < adev->sdma.num_instances; i++) { 1217 adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs; 1218 adev->sdma.instance[i].ring.me = i; 1219 } 1220 } 1221 1222 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = { 1223 .set = sdma_v2_4_set_trap_irq_state, 1224 .process = sdma_v2_4_process_trap_irq, 1225 }; 1226 1227 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = { 1228 .process = sdma_v2_4_process_illegal_inst_irq, 1229 }; 1230 1231 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev) 1232 { 1233 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1234 adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs; 1235 adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs; 1236 } 1237 1238 /** 1239 * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine 1240 * 1241 * @ring: amdgpu_ring structure holding ring information 1242 * @src_offset: src GPU address 1243 * @dst_offset: dst GPU address 1244 * @byte_count: number of bytes to xfer 1245 * 1246 * Copy GPU buffers using the DMA engine (VI). 1247 * Used by the amdgpu ttm implementation to move pages if 1248 * registered as the asic copy callback. 1249 */ 1250 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib, 1251 uint64_t src_offset, 1252 uint64_t dst_offset, 1253 uint32_t byte_count) 1254 { 1255 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1256 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1257 ib->ptr[ib->length_dw++] = byte_count; 1258 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1259 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1260 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1261 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1262 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1263 } 1264 1265 /** 1266 * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine 1267 * 1268 * @ring: amdgpu_ring structure holding ring information 1269 * @src_data: value to write to buffer 1270 * @dst_offset: dst GPU address 1271 * @byte_count: number of bytes to xfer 1272 * 1273 * Fill GPU buffers using the DMA engine (VI). 1274 */ 1275 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib, 1276 uint32_t src_data, 1277 uint64_t dst_offset, 1278 uint32_t byte_count) 1279 { 1280 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1281 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1282 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1283 ib->ptr[ib->length_dw++] = src_data; 1284 ib->ptr[ib->length_dw++] = byte_count; 1285 } 1286 1287 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = { 1288 .copy_max_bytes = 0x1fffff, 1289 .copy_num_dw = 7, 1290 .emit_copy_buffer = sdma_v2_4_emit_copy_buffer, 1291 1292 .fill_max_bytes = 0x1fffff, 1293 .fill_num_dw = 7, 1294 .emit_fill_buffer = sdma_v2_4_emit_fill_buffer, 1295 }; 1296 1297 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev) 1298 { 1299 if (adev->mman.buffer_funcs == NULL) { 1300 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs; 1301 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1302 } 1303 } 1304 1305 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = { 1306 .copy_pte_num_dw = 7, 1307 .copy_pte = sdma_v2_4_vm_copy_pte, 1308 1309 .write_pte = sdma_v2_4_vm_write_pte, 1310 .set_pte_pde = sdma_v2_4_vm_set_pte_pde, 1311 }; 1312 1313 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev) 1314 { 1315 unsigned i; 1316 1317 if (adev->vm_manager.vm_pte_funcs == NULL) { 1318 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs; 1319 for (i = 0; i < adev->sdma.num_instances; i++) 1320 adev->vm_manager.vm_pte_rings[i] = 1321 &adev->sdma.instance[i].ring; 1322 1323 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; 1324 } 1325 } 1326 1327 const struct amdgpu_ip_block_version sdma_v2_4_ip_block = 1328 { 1329 .type = AMD_IP_BLOCK_TYPE_SDMA, 1330 .major = 2, 1331 .minor = 4, 1332 .rev = 0, 1333 .funcs = &sdma_v2_4_ip_funcs, 1334 }; 1335