1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 30 #include "sdma0/sdma0_4_0_offset.h" 31 #include "sdma0/sdma0_4_0_sh_mask.h" 32 #include "sdma1/sdma1_4_0_offset.h" 33 #include "sdma1/sdma1_4_0_sh_mask.h" 34 #include "hdp/hdp_4_0_offset.h" 35 #include "sdma0/sdma0_4_1_default.h" 36 37 #include "soc15_common.h" 38 #include "soc15.h" 39 #include "vega10_sdma_pkt_open.h" 40 41 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 42 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 43 44 MODULE_FIRMWARE("amdgpufw_vega10_sdma"); 45 MODULE_FIRMWARE("amdgpufw_vega10_sdma1"); 46 MODULE_FIRMWARE("amdgpufw_vega12_sdma"); 47 MODULE_FIRMWARE("amdgpufw_vega12_sdma1"); 48 MODULE_FIRMWARE("amdgpufw_vega20_sdma"); 49 MODULE_FIRMWARE("amdgpufw_vega20_sdma1"); 50 MODULE_FIRMWARE("amdgpufw_raven_sdma"); 51 52 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 53 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 54 55 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 56 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 57 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 58 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 59 60 static const struct soc15_reg_golden golden_settings_sdma_4[] = { 61 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 62 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), 63 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), 64 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 65 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 66 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 67 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), 68 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 69 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 70 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 71 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 72 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 73 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000), 74 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 75 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), 76 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 77 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 78 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 79 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000), 80 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 81 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 82 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 83 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 84 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 85 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000) 86 }; 87 88 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { 89 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 91 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 92 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 93 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002) 94 }; 95 96 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = { 97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 99 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 100 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 101 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001) 102 }; 103 104 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = 105 { 106 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 107 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 108 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100), 109 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 110 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051), 111 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100), 112 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 113 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100), 114 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 115 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 116 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000) 117 }; 118 119 static const struct soc15_reg_golden golden_settings_sdma_4_2[] = 120 { 121 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 122 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 123 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 124 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 125 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 126 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 127 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 128 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 129 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 130 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 131 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 132 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 133 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 134 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 135 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 136 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 137 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 138 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0) 139 }; 140 141 static const struct soc15_reg_golden golden_settings_sdma_rv1[] = 142 { 143 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 144 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002) 145 }; 146 147 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, 148 u32 instance, u32 offset) 149 { 150 return ( 0 == instance ? (adev->reg_offset[SDMA0_HWIP][0][0] + offset) : 151 (adev->reg_offset[SDMA1_HWIP][0][0] + offset)); 152 } 153 154 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 155 { 156 switch (adev->asic_type) { 157 case CHIP_VEGA10: 158 soc15_program_register_sequence(adev, 159 golden_settings_sdma_4, 160 ARRAY_SIZE(golden_settings_sdma_4)); 161 soc15_program_register_sequence(adev, 162 golden_settings_sdma_vg10, 163 ARRAY_SIZE(golden_settings_sdma_vg10)); 164 break; 165 case CHIP_VEGA12: 166 soc15_program_register_sequence(adev, 167 golden_settings_sdma_4, 168 ARRAY_SIZE(golden_settings_sdma_4)); 169 soc15_program_register_sequence(adev, 170 golden_settings_sdma_vg12, 171 ARRAY_SIZE(golden_settings_sdma_vg12)); 172 break; 173 case CHIP_VEGA20: 174 soc15_program_register_sequence(adev, 175 golden_settings_sdma_4_2, 176 ARRAY_SIZE(golden_settings_sdma_4_2)); 177 break; 178 case CHIP_RAVEN: 179 soc15_program_register_sequence(adev, 180 golden_settings_sdma_4_1, 181 ARRAY_SIZE(golden_settings_sdma_4_1)); 182 soc15_program_register_sequence(adev, 183 golden_settings_sdma_rv1, 184 ARRAY_SIZE(golden_settings_sdma_rv1)); 185 break; 186 default: 187 break; 188 } 189 } 190 191 /** 192 * sdma_v4_0_init_microcode - load ucode images from disk 193 * 194 * @adev: amdgpu_device pointer 195 * 196 * Use the firmware interface to load the ucode images into 197 * the driver (not loaded into hw). 198 * Returns 0 on success, error on failure. 199 */ 200 201 // emulation only, won't work on real chip 202 // vega10 real chip need to use PSP to load firmware 203 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 204 { 205 const char *chip_name; 206 char fw_name[30]; 207 int err = 0, i; 208 struct amdgpu_firmware_info *info = NULL; 209 const struct common_firmware_header *header = NULL; 210 const struct sdma_firmware_header_v1_0 *hdr; 211 212 DRM_DEBUG("\n"); 213 214 switch (adev->asic_type) { 215 case CHIP_VEGA10: 216 chip_name = "vega10"; 217 break; 218 case CHIP_VEGA12: 219 chip_name = "vega12"; 220 break; 221 case CHIP_VEGA20: 222 chip_name = "vega20"; 223 break; 224 case CHIP_RAVEN: 225 chip_name = "raven"; 226 break; 227 default: 228 BUG(); 229 } 230 231 for (i = 0; i < adev->sdma.num_instances; i++) { 232 if (i == 0) 233 snprintf(fw_name, sizeof(fw_name), "amdgpufw_%s_sdma", chip_name); 234 else 235 snprintf(fw_name, sizeof(fw_name), "amdgpufw_%s_sdma1", chip_name); 236 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 237 if (err) 238 goto out; 239 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 240 if (err) 241 goto out; 242 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 243 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 244 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 245 if (adev->sdma.instance[i].feature_version >= 20) 246 adev->sdma.instance[i].burst_nop = true; 247 DRM_DEBUG("psp_load == '%s'\n", 248 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 249 250 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 251 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 252 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 253 info->fw = adev->sdma.instance[i].fw; 254 header = (const struct common_firmware_header *)info->fw->data; 255 adev->firmware.fw_size += 256 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 257 } 258 } 259 out: 260 if (err) { 261 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name); 262 for (i = 0; i < adev->sdma.num_instances; i++) { 263 release_firmware(adev->sdma.instance[i].fw); 264 adev->sdma.instance[i].fw = NULL; 265 } 266 } 267 return err; 268 } 269 270 /** 271 * sdma_v4_0_ring_get_rptr - get the current read pointer 272 * 273 * @ring: amdgpu ring pointer 274 * 275 * Get the current rptr from the hardware (VEGA10+). 276 */ 277 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 278 { 279 u64 *rptr; 280 281 /* XXX check if swapping is necessary on BE */ 282 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 283 284 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 285 return ((*rptr) >> 2); 286 } 287 288 /** 289 * sdma_v4_0_ring_get_wptr - get the current write pointer 290 * 291 * @ring: amdgpu ring pointer 292 * 293 * Get the current wptr from the hardware (VEGA10+). 294 */ 295 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 296 { 297 struct amdgpu_device *adev = ring->adev; 298 u64 wptr; 299 300 if (ring->use_doorbell) { 301 /* XXX check if swapping is necessary on BE */ 302 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 303 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 304 } else { 305 u32 lowbit, highbit; 306 307 lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2; 308 highbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2; 309 310 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n", 311 ring->me, highbit, lowbit); 312 wptr = highbit; 313 wptr = wptr << 32; 314 wptr |= lowbit; 315 } 316 317 return wptr >> 2; 318 } 319 320 /** 321 * sdma_v4_0_ring_set_wptr - commit the write pointer 322 * 323 * @ring: amdgpu ring pointer 324 * 325 * Write the wptr back to the hardware (VEGA10+). 326 */ 327 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 328 { 329 struct amdgpu_device *adev = ring->adev; 330 331 DRM_DEBUG("Setting write pointer\n"); 332 if (ring->use_doorbell) { 333 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 334 335 DRM_DEBUG("Using doorbell -- " 336 "wptr_offs == 0x%08x " 337 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 338 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 339 ring->wptr_offs, 340 lower_32_bits(ring->wptr << 2), 341 upper_32_bits(ring->wptr << 2)); 342 /* XXX check if swapping is necessary on BE */ 343 WRITE_ONCE(*wb, (ring->wptr << 2)); 344 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 345 ring->doorbell_index, ring->wptr << 2); 346 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 347 } else { 348 DRM_DEBUG("Not using doorbell -- " 349 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 350 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 351 ring->me, 352 lower_32_bits(ring->wptr << 2), 353 ring->me, 354 upper_32_bits(ring->wptr << 2)); 355 WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); 356 WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); 357 } 358 } 359 360 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 361 { 362 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 363 int i; 364 365 for (i = 0; i < count; i++) 366 if (sdma && sdma->burst_nop && (i == 0)) 367 amdgpu_ring_write(ring, ring->funcs->nop | 368 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 369 else 370 amdgpu_ring_write(ring, ring->funcs->nop); 371 } 372 373 /** 374 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine 375 * 376 * @ring: amdgpu ring pointer 377 * @ib: IB object to schedule 378 * 379 * Schedule an IB in the DMA ring (VEGA10). 380 */ 381 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 382 struct amdgpu_ib *ib, 383 unsigned vmid, bool ctx_switch) 384 { 385 /* IB packet must end on a 8 DW boundary */ 386 sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 387 388 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 389 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 390 /* base must be 32 byte aligned */ 391 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 392 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 393 amdgpu_ring_write(ring, ib->length_dw); 394 amdgpu_ring_write(ring, 0); 395 amdgpu_ring_write(ring, 0); 396 397 } 398 399 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring, 400 int mem_space, int hdp, 401 uint32_t addr0, uint32_t addr1, 402 uint32_t ref, uint32_t mask, 403 uint32_t inv) 404 { 405 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 406 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 407 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 408 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 409 if (mem_space) { 410 /* memory */ 411 amdgpu_ring_write(ring, addr0); 412 amdgpu_ring_write(ring, addr1); 413 } else { 414 /* registers */ 415 amdgpu_ring_write(ring, addr0 << 2); 416 amdgpu_ring_write(ring, addr1 << 2); 417 } 418 amdgpu_ring_write(ring, ref); /* reference */ 419 amdgpu_ring_write(ring, mask); /* mask */ 420 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 421 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 422 } 423 424 /** 425 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 426 * 427 * @ring: amdgpu ring pointer 428 * 429 * Emit an hdp flush packet on the requested DMA ring. 430 */ 431 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 432 { 433 struct amdgpu_device *adev = ring->adev; 434 u32 ref_and_mask = 0; 435 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; 436 437 if (ring->me == 0) 438 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; 439 else 440 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; 441 442 sdma_v4_0_wait_reg_mem(ring, 0, 1, 443 adev->nbio_funcs->get_hdp_flush_done_offset(adev), 444 adev->nbio_funcs->get_hdp_flush_req_offset(adev), 445 ref_and_mask, ref_and_mask, 10); 446 } 447 448 /** 449 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring 450 * 451 * @ring: amdgpu ring pointer 452 * @fence: amdgpu fence object 453 * 454 * Add a DMA fence packet to the ring to write 455 * the fence seq number and DMA trap packet to generate 456 * an interrupt if needed (VEGA10). 457 */ 458 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, uint64_t addr, uint64_t seq, 459 unsigned flags) 460 { 461 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 462 /* write the fence */ 463 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 464 /* zero in first two bits */ 465 BUG_ON(addr & 0x3); 466 amdgpu_ring_write(ring, lower_32_bits(addr)); 467 amdgpu_ring_write(ring, upper_32_bits(addr)); 468 amdgpu_ring_write(ring, lower_32_bits(seq)); 469 470 /* optionally write high bits as well */ 471 if (write64bit) { 472 addr += 4; 473 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 474 /* zero in first two bits */ 475 BUG_ON(addr & 0x3); 476 amdgpu_ring_write(ring, lower_32_bits(addr)); 477 amdgpu_ring_write(ring, upper_32_bits(addr)); 478 amdgpu_ring_write(ring, upper_32_bits(seq)); 479 } 480 481 /* generate an interrupt */ 482 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 483 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 484 } 485 486 487 /** 488 * sdma_v4_0_gfx_stop - stop the gfx async dma engines 489 * 490 * @adev: amdgpu_device pointer 491 * 492 * Stop the gfx async dma ring buffers (VEGA10). 493 */ 494 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) 495 { 496 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 497 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 498 u32 rb_cntl, ib_cntl; 499 int i; 500 501 if ((adev->mman.buffer_funcs_ring == sdma0) || 502 (adev->mman.buffer_funcs_ring == sdma1)) 503 amdgpu_ttm_set_buffer_funcs_status(adev, false); 504 505 for (i = 0; i < adev->sdma.num_instances; i++) { 506 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 507 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 508 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 509 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 510 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 511 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 512 } 513 514 sdma0->ready = false; 515 sdma1->ready = false; 516 } 517 518 /** 519 * sdma_v4_0_rlc_stop - stop the compute async dma engines 520 * 521 * @adev: amdgpu_device pointer 522 * 523 * Stop the compute async dma queues (VEGA10). 524 */ 525 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) 526 { 527 /* XXX todo */ 528 } 529 530 /** 531 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch 532 * 533 * @adev: amdgpu_device pointer 534 * @enable: enable/disable the DMA MEs context switch. 535 * 536 * Halt or unhalt the async dma engines context switch (VEGA10). 537 */ 538 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 539 { 540 u32 f32_cntl, phase_quantum = 0; 541 int i; 542 543 if (amdgpu_sdma_phase_quantum) { 544 unsigned value = amdgpu_sdma_phase_quantum; 545 unsigned unit = 0; 546 547 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 548 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 549 value = (value + 1) >> 1; 550 unit++; 551 } 552 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 553 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 554 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 555 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 556 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 557 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 558 WARN_ONCE(1, 559 "clamping sdma_phase_quantum to %uK clock cycles\n", 560 value << unit); 561 } 562 phase_quantum = 563 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 564 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 565 } 566 567 for (i = 0; i < adev->sdma.num_instances; i++) { 568 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 569 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 570 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 571 if (enable && amdgpu_sdma_phase_quantum) { 572 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 573 phase_quantum); 574 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 575 phase_quantum); 576 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 577 phase_quantum); 578 } 579 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 580 } 581 582 } 583 584 /** 585 * sdma_v4_0_enable - stop the async dma engines 586 * 587 * @adev: amdgpu_device pointer 588 * @enable: enable/disable the DMA MEs. 589 * 590 * Halt or unhalt the async dma engines (VEGA10). 591 */ 592 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 593 { 594 u32 f32_cntl; 595 int i; 596 597 if (enable == false) { 598 sdma_v4_0_gfx_stop(adev); 599 sdma_v4_0_rlc_stop(adev); 600 } 601 602 for (i = 0; i < adev->sdma.num_instances; i++) { 603 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 604 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 605 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 606 } 607 } 608 609 /** 610 * sdma_v4_0_gfx_resume - setup and start the async dma engines 611 * 612 * @adev: amdgpu_device pointer 613 * 614 * Set up the gfx DMA ring buffers and enable them (VEGA10). 615 * Returns 0 for success, error for failure. 616 */ 617 static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev) 618 { 619 struct amdgpu_ring *ring; 620 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 621 u32 rb_bufsz; 622 u32 wb_offset; 623 u32 doorbell; 624 u32 doorbell_offset; 625 u32 temp; 626 u64 wptr_gpu_addr; 627 int i, r; 628 629 for (i = 0; i < adev->sdma.num_instances; i++) { 630 ring = &adev->sdma.instance[i].ring; 631 wb_offset = (ring->rptr_offs * 4); 632 633 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 634 635 /* Set ring buffer size in dwords */ 636 rb_bufsz = order_base_2(ring->ring_size / 4); 637 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 638 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 639 #ifdef __BIG_ENDIAN 640 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 641 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 642 RPTR_WRITEBACK_SWAP_ENABLE, 1); 643 #endif 644 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 645 646 /* Initialize the ring buffer's read and write pointers */ 647 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 648 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 649 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 650 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 651 652 /* set the wb address whether it's enabled or not */ 653 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 654 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 655 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 656 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 657 658 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 659 660 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 661 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 662 663 ring->wptr = 0; 664 665 /* before programing wptr to a less value, need set minor_ptr_update first */ 666 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 667 668 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 669 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); 670 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 671 } 672 673 doorbell = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 674 doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 675 676 if (ring->use_doorbell) { 677 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 678 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 679 OFFSET, ring->doorbell_index); 680 } else { 681 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 682 } 683 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 684 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 685 adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 686 ring->doorbell_index); 687 688 if (amdgpu_sriov_vf(adev)) 689 sdma_v4_0_ring_set_wptr(ring); 690 691 /* set minor_ptr_update to 0 after wptr programed */ 692 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 693 694 /* set utc l1 enable flag always to 1 */ 695 temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 696 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 697 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 698 699 if (!amdgpu_sriov_vf(adev)) { 700 /* unhalt engine */ 701 temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 702 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 703 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 704 } 705 706 /* setup the wptr shadow polling */ 707 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 708 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 709 lower_32_bits(wptr_gpu_addr)); 710 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 711 upper_32_bits(wptr_gpu_addr)); 712 wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 713 if (amdgpu_sriov_vf(adev)) 714 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1); 715 else 716 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0); 717 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl); 718 719 /* enable DMA RB */ 720 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 721 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 722 723 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 724 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 725 #ifdef __BIG_ENDIAN 726 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 727 #endif 728 /* enable DMA IBs */ 729 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 730 731 ring->ready = true; 732 733 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 734 sdma_v4_0_ctx_switch_enable(adev, true); 735 sdma_v4_0_enable(adev, true); 736 } 737 738 r = amdgpu_ring_test_ring(ring); 739 if (r) { 740 ring->ready = false; 741 return r; 742 } 743 744 if (adev->mman.buffer_funcs_ring == ring) 745 amdgpu_ttm_set_buffer_funcs_status(adev, true); 746 747 } 748 749 return 0; 750 } 751 752 static void 753 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable) 754 { 755 uint32_t def, data; 756 757 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) { 758 /* disable idle interrupt */ 759 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 760 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 761 762 if (data != def) 763 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 764 } else { 765 /* disable idle interrupt */ 766 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 767 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 768 if (data != def) 769 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 770 } 771 } 772 773 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev) 774 { 775 uint32_t def, data; 776 777 /* Enable HW based PG. */ 778 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 779 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK; 780 if (data != def) 781 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 782 783 /* enable interrupt */ 784 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 785 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 786 if (data != def) 787 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 788 789 /* Configure hold time to filter in-valid power on/off request. Use default right now */ 790 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 791 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK; 792 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK); 793 /* Configure switch time for hysteresis purpose. Use default right now */ 794 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; 795 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK); 796 if(data != def) 797 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 798 } 799 800 static void sdma_v4_0_init_pg(struct amdgpu_device *adev) 801 { 802 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA)) 803 return; 804 805 switch (adev->asic_type) { 806 case CHIP_RAVEN: 807 sdma_v4_1_init_power_gating(adev); 808 sdma_v4_1_update_power_gating(adev, true); 809 break; 810 default: 811 break; 812 } 813 } 814 815 /** 816 * sdma_v4_0_rlc_resume - setup and start the async dma engines 817 * 818 * @adev: amdgpu_device pointer 819 * 820 * Set up the compute DMA queues and enable them (VEGA10). 821 * Returns 0 for success, error for failure. 822 */ 823 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) 824 { 825 sdma_v4_0_init_pg(adev); 826 827 return 0; 828 } 829 830 /** 831 * sdma_v4_0_load_microcode - load the sDMA ME ucode 832 * 833 * @adev: amdgpu_device pointer 834 * 835 * Loads the sDMA0/1 ucode. 836 * Returns 0 for success, -EINVAL if the ucode is not available. 837 */ 838 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 839 { 840 const struct sdma_firmware_header_v1_0 *hdr; 841 const __le32 *fw_data; 842 u32 fw_size; 843 int i, j; 844 845 /* halt the MEs */ 846 sdma_v4_0_enable(adev, false); 847 848 for (i = 0; i < adev->sdma.num_instances; i++) { 849 if (!adev->sdma.instance[i].fw) 850 return -EINVAL; 851 852 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 853 amdgpu_ucode_print_sdma_hdr(&hdr->header); 854 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 855 856 fw_data = (const __le32 *) 857 (adev->sdma.instance[i].fw->data + 858 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 859 860 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 861 862 for (j = 0; j < fw_size; j++) 863 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 864 865 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 866 } 867 868 return 0; 869 } 870 871 /** 872 * sdma_v4_0_start - setup and start the async dma engines 873 * 874 * @adev: amdgpu_device pointer 875 * 876 * Set up the DMA engines and enable them (VEGA10). 877 * Returns 0 for success, error for failure. 878 */ 879 static int sdma_v4_0_start(struct amdgpu_device *adev) 880 { 881 int r = 0; 882 883 if (amdgpu_sriov_vf(adev)) { 884 sdma_v4_0_ctx_switch_enable(adev, false); 885 sdma_v4_0_enable(adev, false); 886 887 /* set RB registers */ 888 r = sdma_v4_0_gfx_resume(adev); 889 return r; 890 } 891 892 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 893 r = sdma_v4_0_load_microcode(adev); 894 if (r) 895 return r; 896 } 897 898 /* unhalt the MEs */ 899 sdma_v4_0_enable(adev, true); 900 /* enable sdma ring preemption */ 901 sdma_v4_0_ctx_switch_enable(adev, true); 902 903 /* start the gfx rings and rlc compute queues */ 904 r = sdma_v4_0_gfx_resume(adev); 905 if (r) 906 return r; 907 r = sdma_v4_0_rlc_resume(adev); 908 909 return r; 910 } 911 912 /** 913 * sdma_v4_0_ring_test_ring - simple async dma engine test 914 * 915 * @ring: amdgpu_ring structure holding ring information 916 * 917 * Test the DMA engine by writing using it to write an 918 * value to memory. (VEGA10). 919 * Returns 0 for success, error for failure. 920 */ 921 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 922 { 923 struct amdgpu_device *adev = ring->adev; 924 unsigned i; 925 unsigned index; 926 int r; 927 u32 tmp; 928 u64 gpu_addr; 929 930 r = amdgpu_device_wb_get(adev, &index); 931 if (r) { 932 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 933 return r; 934 } 935 936 gpu_addr = adev->wb.gpu_addr + (index * 4); 937 tmp = 0xCAFEDEAD; 938 adev->wb.wb[index] = cpu_to_le32(tmp); 939 940 r = amdgpu_ring_alloc(ring, 5); 941 if (r) { 942 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 943 amdgpu_device_wb_free(adev, index); 944 return r; 945 } 946 947 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 948 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 949 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 950 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 951 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 952 amdgpu_ring_write(ring, 0xDEADBEEF); 953 amdgpu_ring_commit(ring); 954 955 for (i = 0; i < adev->usec_timeout; i++) { 956 tmp = le32_to_cpu(adev->wb.wb[index]); 957 if (tmp == 0xDEADBEEF) 958 break; 959 DRM_UDELAY(1); 960 } 961 962 if (i < adev->usec_timeout) { 963 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); 964 } else { 965 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 966 ring->idx, tmp); 967 r = -EINVAL; 968 } 969 amdgpu_device_wb_free(adev, index); 970 971 return r; 972 } 973 974 /** 975 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine 976 * 977 * @ring: amdgpu_ring structure holding ring information 978 * 979 * Test a simple IB in the DMA ring (VEGA10). 980 * Returns 0 on success, error on failure. 981 */ 982 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 983 { 984 struct amdgpu_device *adev = ring->adev; 985 struct amdgpu_ib ib; 986 struct dma_fence *f = NULL; 987 unsigned index; 988 long r; 989 u32 tmp = 0; 990 u64 gpu_addr; 991 992 r = amdgpu_device_wb_get(adev, &index); 993 if (r) { 994 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 995 return r; 996 } 997 998 gpu_addr = adev->wb.gpu_addr + (index * 4); 999 tmp = 0xCAFEDEAD; 1000 adev->wb.wb[index] = cpu_to_le32(tmp); 1001 memset(&ib, 0, sizeof(ib)); 1002 r = amdgpu_ib_get(adev, NULL, 256, &ib); 1003 if (r) { 1004 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 1005 goto err0; 1006 } 1007 1008 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1009 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1010 ib.ptr[1] = lower_32_bits(gpu_addr); 1011 ib.ptr[2] = upper_32_bits(gpu_addr); 1012 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1013 ib.ptr[4] = 0xDEADBEEF; 1014 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1015 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1016 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1017 ib.length_dw = 8; 1018 1019 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1020 if (r) 1021 goto err1; 1022 1023 r = dma_fence_wait_timeout(f, false, timeout); 1024 if (r == 0) { 1025 DRM_ERROR("amdgpu: IB test timed out\n"); 1026 r = -ETIMEDOUT; 1027 goto err1; 1028 } else if (r < 0) { 1029 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1030 goto err1; 1031 } 1032 tmp = le32_to_cpu(adev->wb.wb[index]); 1033 if (tmp == 0xDEADBEEF) { 1034 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); 1035 r = 0; 1036 } else { 1037 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 1038 r = -EINVAL; 1039 } 1040 err1: 1041 amdgpu_ib_free(adev, &ib, NULL); 1042 dma_fence_put(f); 1043 err0: 1044 amdgpu_device_wb_free(adev, index); 1045 return r; 1046 } 1047 1048 1049 /** 1050 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART 1051 * 1052 * @ib: indirect buffer to fill with commands 1053 * @pe: addr of the page entry 1054 * @src: src addr to copy from 1055 * @count: number of page entries to update 1056 * 1057 * Update PTEs by copying them from the GART using sDMA (VEGA10). 1058 */ 1059 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, 1060 uint64_t pe, uint64_t src, 1061 unsigned count) 1062 { 1063 unsigned bytes = count * 8; 1064 1065 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1066 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1067 ib->ptr[ib->length_dw++] = bytes - 1; 1068 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1069 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1070 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1071 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1072 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1073 1074 } 1075 1076 /** 1077 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually 1078 * 1079 * @ib: indirect buffer to fill with commands 1080 * @pe: addr of the page entry 1081 * @addr: dst addr to write into pe 1082 * @count: number of page entries to update 1083 * @incr: increase next addr by incr bytes 1084 * @flags: access flags 1085 * 1086 * Update PTEs by writing them manually using sDMA (VEGA10). 1087 */ 1088 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1089 uint64_t value, unsigned count, 1090 uint32_t incr) 1091 { 1092 unsigned ndw = count * 2; 1093 1094 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1095 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1096 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1097 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1098 ib->ptr[ib->length_dw++] = ndw - 1; 1099 for (; ndw > 0; ndw -= 2) { 1100 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1101 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1102 value += incr; 1103 } 1104 } 1105 1106 /** 1107 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA 1108 * 1109 * @ib: indirect buffer to fill with commands 1110 * @pe: addr of the page entry 1111 * @addr: dst addr to write into pe 1112 * @count: number of page entries to update 1113 * @incr: increase next addr by incr bytes 1114 * @flags: access flags 1115 * 1116 * Update the page tables using sDMA (VEGA10). 1117 */ 1118 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1119 uint64_t pe, 1120 uint64_t addr, unsigned count, 1121 uint32_t incr, uint64_t flags) 1122 { 1123 /* for physically contiguous pages (vram) */ 1124 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1125 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1126 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1127 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1128 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1129 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1130 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1131 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1132 ib->ptr[ib->length_dw++] = 0; 1133 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1134 } 1135 1136 /** 1137 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw 1138 * 1139 * @ib: indirect buffer to fill with padding 1140 * 1141 */ 1142 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1143 { 1144 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 1145 u32 pad_count; 1146 int i; 1147 1148 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1149 for (i = 0; i < pad_count; i++) 1150 if (sdma && sdma->burst_nop && (i == 0)) 1151 ib->ptr[ib->length_dw++] = 1152 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1153 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1154 else 1155 ib->ptr[ib->length_dw++] = 1156 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1157 } 1158 1159 1160 /** 1161 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline 1162 * 1163 * @ring: amdgpu_ring pointer 1164 * 1165 * Make sure all previous operations are completed (CIK). 1166 */ 1167 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1168 { 1169 uint32_t seq = ring->fence_drv.sync_seq; 1170 uint64_t addr = ring->fence_drv.gpu_addr; 1171 1172 /* wait for idle */ 1173 sdma_v4_0_wait_reg_mem(ring, 1, 0, 1174 addr & 0xfffffffc, 1175 upper_32_bits(addr) & 0xffffffff, 1176 seq, 0xffffffff, 4); 1177 } 1178 1179 1180 /** 1181 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA 1182 * 1183 * @ring: amdgpu_ring pointer 1184 * @vm: amdgpu_vm pointer 1185 * 1186 * Update the page table base and flush the VM TLB 1187 * using sDMA (VEGA10). 1188 */ 1189 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1190 unsigned vmid, uint64_t pd_addr) 1191 { 1192 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1193 } 1194 1195 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring, 1196 uint32_t reg, uint32_t val) 1197 { 1198 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1199 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1200 amdgpu_ring_write(ring, reg); 1201 amdgpu_ring_write(ring, val); 1202 } 1203 1204 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1205 uint32_t val, uint32_t mask) 1206 { 1207 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1208 } 1209 1210 static int sdma_v4_0_early_init(void *handle) 1211 { 1212 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1213 1214 if (adev->asic_type == CHIP_RAVEN) 1215 adev->sdma.num_instances = 1; 1216 else 1217 adev->sdma.num_instances = 2; 1218 1219 sdma_v4_0_set_ring_funcs(adev); 1220 sdma_v4_0_set_buffer_funcs(adev); 1221 sdma_v4_0_set_vm_pte_funcs(adev); 1222 sdma_v4_0_set_irq_funcs(adev); 1223 1224 return 0; 1225 } 1226 1227 1228 static int sdma_v4_0_sw_init(void *handle) 1229 { 1230 struct amdgpu_ring *ring; 1231 int r, i; 1232 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1233 1234 /* SDMA trap event */ 1235 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, SDMA0_4_0__SRCID__SDMA_TRAP, 1236 &adev->sdma.trap_irq); 1237 if (r) 1238 return r; 1239 1240 /* SDMA trap event */ 1241 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, SDMA1_4_0__SRCID__SDMA_TRAP, 1242 &adev->sdma.trap_irq); 1243 if (r) 1244 return r; 1245 1246 r = sdma_v4_0_init_microcode(adev); 1247 if (r) { 1248 DRM_ERROR("Failed to load sdma firmware!\n"); 1249 return r; 1250 } 1251 1252 for (i = 0; i < adev->sdma.num_instances; i++) { 1253 ring = &adev->sdma.instance[i].ring; 1254 ring->ring_obj = NULL; 1255 ring->use_doorbell = true; 1256 1257 DRM_INFO("use_doorbell being set to: [%s]\n", 1258 ring->use_doorbell?"true":"false"); 1259 1260 ring->doorbell_index = (i == 0) ? 1261 (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset 1262 : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset 1263 1264 ksprintf(ring->name, "sdma%d", i); 1265 r = amdgpu_ring_init(adev, ring, 1024, 1266 &adev->sdma.trap_irq, 1267 (i == 0) ? 1268 AMDGPU_SDMA_IRQ_TRAP0 : 1269 AMDGPU_SDMA_IRQ_TRAP1); 1270 if (r) 1271 return r; 1272 } 1273 1274 return r; 1275 } 1276 1277 static int sdma_v4_0_sw_fini(void *handle) 1278 { 1279 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1280 int i; 1281 1282 for (i = 0; i < adev->sdma.num_instances; i++) 1283 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1284 1285 for (i = 0; i < adev->sdma.num_instances; i++) { 1286 release_firmware(adev->sdma.instance[i].fw); 1287 adev->sdma.instance[i].fw = NULL; 1288 } 1289 1290 return 0; 1291 } 1292 1293 static int sdma_v4_0_hw_init(void *handle) 1294 { 1295 int r; 1296 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1297 1298 sdma_v4_0_init_golden_registers(adev); 1299 1300 r = sdma_v4_0_start(adev); 1301 1302 return r; 1303 } 1304 1305 static int sdma_v4_0_hw_fini(void *handle) 1306 { 1307 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1308 1309 if (amdgpu_sriov_vf(adev)) 1310 return 0; 1311 1312 sdma_v4_0_ctx_switch_enable(adev, false); 1313 sdma_v4_0_enable(adev, false); 1314 1315 return 0; 1316 } 1317 1318 static int sdma_v4_0_suspend(void *handle) 1319 { 1320 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1321 1322 return sdma_v4_0_hw_fini(adev); 1323 } 1324 1325 static int sdma_v4_0_resume(void *handle) 1326 { 1327 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1328 1329 return sdma_v4_0_hw_init(adev); 1330 } 1331 1332 static bool sdma_v4_0_is_idle(void *handle) 1333 { 1334 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1335 u32 i; 1336 1337 for (i = 0; i < adev->sdma.num_instances; i++) { 1338 u32 tmp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1339 1340 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1341 return false; 1342 } 1343 1344 return true; 1345 } 1346 1347 static int sdma_v4_0_wait_for_idle(void *handle) 1348 { 1349 unsigned i; 1350 u32 sdma0, sdma1; 1351 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1352 1353 for (i = 0; i < adev->usec_timeout; i++) { 1354 sdma0 = RREG32(sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1355 sdma1 = RREG32(sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1356 1357 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1358 return 0; 1359 udelay(1); 1360 } 1361 return -ETIMEDOUT; 1362 } 1363 1364 static int sdma_v4_0_soft_reset(void *handle) 1365 { 1366 /* todo */ 1367 1368 return 0; 1369 } 1370 1371 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 1372 struct amdgpu_irq_src *source, 1373 unsigned type, 1374 enum amdgpu_interrupt_state state) 1375 { 1376 u32 sdma_cntl; 1377 1378 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ? 1379 sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) : 1380 sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_CNTL); 1381 1382 sdma_cntl = RREG32(reg_offset); 1383 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1384 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1385 WREG32(reg_offset, sdma_cntl); 1386 1387 return 0; 1388 } 1389 1390 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 1391 struct amdgpu_irq_src *source, 1392 struct amdgpu_iv_entry *entry) 1393 { 1394 DRM_DEBUG("IH: SDMA trap\n"); 1395 switch (entry->client_id) { 1396 case SOC15_IH_CLIENTID_SDMA0: 1397 switch (entry->ring_id) { 1398 case 0: 1399 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1400 break; 1401 case 1: 1402 /* XXX compute */ 1403 break; 1404 case 2: 1405 /* XXX compute */ 1406 break; 1407 case 3: 1408 /* XXX page queue*/ 1409 break; 1410 } 1411 break; 1412 case SOC15_IH_CLIENTID_SDMA1: 1413 switch (entry->ring_id) { 1414 case 0: 1415 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1416 break; 1417 case 1: 1418 /* XXX compute */ 1419 break; 1420 case 2: 1421 /* XXX compute */ 1422 break; 1423 case 3: 1424 /* XXX page queue*/ 1425 break; 1426 } 1427 break; 1428 } 1429 return 0; 1430 } 1431 1432 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1433 struct amdgpu_irq_src *source, 1434 struct amdgpu_iv_entry *entry) 1435 { 1436 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1437 schedule_work(&adev->reset_work); 1438 return 0; 1439 } 1440 1441 1442 static void sdma_v4_0_update_medium_grain_clock_gating( 1443 struct amdgpu_device *adev, 1444 bool enable) 1445 { 1446 uint32_t data, def; 1447 1448 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1449 /* enable sdma0 clock gating */ 1450 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1451 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1452 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1453 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1454 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1455 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1456 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1457 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1458 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1459 if (def != data) 1460 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 1461 1462 if (adev->sdma.num_instances > 1) { 1463 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 1464 data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1465 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1466 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1467 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1468 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1469 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1470 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1471 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1472 if (def != data) 1473 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 1474 } 1475 } else { 1476 /* disable sdma0 clock gating */ 1477 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1478 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1479 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1480 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1481 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1482 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1483 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1484 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1485 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1486 1487 if (def != data) 1488 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 1489 1490 if (adev->sdma.num_instances > 1) { 1491 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 1492 data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1493 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1494 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1495 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1496 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1497 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1498 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1499 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1500 if (def != data) 1501 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 1502 } 1503 } 1504 } 1505 1506 1507 static void sdma_v4_0_update_medium_grain_light_sleep( 1508 struct amdgpu_device *adev, 1509 bool enable) 1510 { 1511 uint32_t data, def; 1512 1513 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1514 /* 1-not override: enable sdma0 mem light sleep */ 1515 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1516 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1517 if (def != data) 1518 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1519 1520 /* 1-not override: enable sdma1 mem light sleep */ 1521 if (adev->sdma.num_instances > 1) { 1522 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 1523 data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1524 if (def != data) 1525 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 1526 } 1527 } else { 1528 /* 0-override:disable sdma0 mem light sleep */ 1529 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1530 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1531 if (def != data) 1532 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1533 1534 /* 0-override:disable sdma1 mem light sleep */ 1535 if (adev->sdma.num_instances > 1) { 1536 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 1537 data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1538 if (def != data) 1539 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 1540 } 1541 } 1542 } 1543 1544 static int sdma_v4_0_set_clockgating_state(void *handle, 1545 enum amd_clockgating_state state) 1546 { 1547 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1548 1549 if (amdgpu_sriov_vf(adev)) 1550 return 0; 1551 1552 switch (adev->asic_type) { 1553 case CHIP_VEGA10: 1554 case CHIP_VEGA12: 1555 case CHIP_VEGA20: 1556 case CHIP_RAVEN: 1557 sdma_v4_0_update_medium_grain_clock_gating(adev, 1558 state == AMD_CG_STATE_GATE ? true : false); 1559 sdma_v4_0_update_medium_grain_light_sleep(adev, 1560 state == AMD_CG_STATE_GATE ? true : false); 1561 break; 1562 default: 1563 break; 1564 } 1565 return 0; 1566 } 1567 1568 static int sdma_v4_0_set_powergating_state(void *handle, 1569 enum amd_powergating_state state) 1570 { 1571 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1572 1573 switch (adev->asic_type) { 1574 case CHIP_RAVEN: 1575 sdma_v4_1_update_power_gating(adev, 1576 state == AMD_PG_STATE_GATE ? true : false); 1577 break; 1578 default: 1579 break; 1580 } 1581 1582 return 0; 1583 } 1584 1585 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags) 1586 { 1587 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1588 int data; 1589 1590 if (amdgpu_sriov_vf(adev)) 1591 *flags = 0; 1592 1593 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1594 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1595 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 1596 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1597 1598 /* AMD_CG_SUPPORT_SDMA_LS */ 1599 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1600 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1601 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1602 } 1603 1604 const struct amd_ip_funcs sdma_v4_0_ip_funcs = { 1605 .name = "sdma_v4_0", 1606 .early_init = sdma_v4_0_early_init, 1607 .late_init = NULL, 1608 .sw_init = sdma_v4_0_sw_init, 1609 .sw_fini = sdma_v4_0_sw_fini, 1610 .hw_init = sdma_v4_0_hw_init, 1611 .hw_fini = sdma_v4_0_hw_fini, 1612 .suspend = sdma_v4_0_suspend, 1613 .resume = sdma_v4_0_resume, 1614 .is_idle = sdma_v4_0_is_idle, 1615 .wait_for_idle = sdma_v4_0_wait_for_idle, 1616 .soft_reset = sdma_v4_0_soft_reset, 1617 .set_clockgating_state = sdma_v4_0_set_clockgating_state, 1618 .set_powergating_state = sdma_v4_0_set_powergating_state, 1619 .get_clockgating_state = sdma_v4_0_get_clockgating_state, 1620 }; 1621 1622 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { 1623 .type = AMDGPU_RING_TYPE_SDMA, 1624 .align_mask = 0xf, 1625 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1626 .support_64bit_ptrs = true, 1627 .vmhub = AMDGPU_MMHUB, 1628 .get_rptr = sdma_v4_0_ring_get_rptr, 1629 .get_wptr = sdma_v4_0_ring_get_wptr, 1630 .set_wptr = sdma_v4_0_ring_set_wptr, 1631 .emit_frame_size = 1632 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 1633 3 + /* hdp invalidate */ 1634 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 1635 /* sdma_v4_0_ring_emit_vm_flush */ 1636 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1637 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1638 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 1639 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 1640 .emit_ib = sdma_v4_0_ring_emit_ib, 1641 .emit_fence = sdma_v4_0_ring_emit_fence, 1642 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 1643 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 1644 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 1645 .test_ring = sdma_v4_0_ring_test_ring, 1646 .test_ib = sdma_v4_0_ring_test_ib, 1647 .insert_nop = sdma_v4_0_ring_insert_nop, 1648 .pad_ib = sdma_v4_0_ring_pad_ib, 1649 .emit_wreg = sdma_v4_0_ring_emit_wreg, 1650 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 1651 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1652 }; 1653 1654 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) 1655 { 1656 int i; 1657 1658 for (i = 0; i < adev->sdma.num_instances; i++) { 1659 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs; 1660 adev->sdma.instance[i].ring.me = i; 1661 } 1662 } 1663 1664 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { 1665 .set = sdma_v4_0_set_trap_irq_state, 1666 .process = sdma_v4_0_process_trap_irq, 1667 }; 1668 1669 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { 1670 .process = sdma_v4_0_process_illegal_inst_irq, 1671 }; 1672 1673 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 1674 { 1675 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1676 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; 1677 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; 1678 } 1679 1680 /** 1681 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine 1682 * 1683 * @ring: amdgpu_ring structure holding ring information 1684 * @src_offset: src GPU address 1685 * @dst_offset: dst GPU address 1686 * @byte_count: number of bytes to xfer 1687 * 1688 * Copy GPU buffers using the DMA engine (VEGA10/12). 1689 * Used by the amdgpu ttm implementation to move pages if 1690 * registered as the asic copy callback. 1691 */ 1692 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 1693 uint64_t src_offset, 1694 uint64_t dst_offset, 1695 uint32_t byte_count) 1696 { 1697 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1698 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1699 ib->ptr[ib->length_dw++] = byte_count - 1; 1700 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1701 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1702 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1703 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1704 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1705 } 1706 1707 /** 1708 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine 1709 * 1710 * @ring: amdgpu_ring structure holding ring information 1711 * @src_data: value to write to buffer 1712 * @dst_offset: dst GPU address 1713 * @byte_count: number of bytes to xfer 1714 * 1715 * Fill GPU buffers using the DMA engine (VEGA10/12). 1716 */ 1717 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, 1718 uint32_t src_data, 1719 uint64_t dst_offset, 1720 uint32_t byte_count) 1721 { 1722 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1723 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1724 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1725 ib->ptr[ib->length_dw++] = src_data; 1726 ib->ptr[ib->length_dw++] = byte_count - 1; 1727 } 1728 1729 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { 1730 .copy_max_bytes = 0x400000, 1731 .copy_num_dw = 7, 1732 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 1733 1734 .fill_max_bytes = 0x400000, 1735 .fill_num_dw = 5, 1736 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 1737 }; 1738 1739 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) 1740 { 1741 if (adev->mman.buffer_funcs == NULL) { 1742 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; 1743 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1744 } 1745 } 1746 1747 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 1748 .copy_pte_num_dw = 7, 1749 .copy_pte = sdma_v4_0_vm_copy_pte, 1750 1751 .write_pte = sdma_v4_0_vm_write_pte, 1752 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 1753 }; 1754 1755 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1756 { 1757 unsigned i; 1758 1759 if (adev->vm_manager.vm_pte_funcs == NULL) { 1760 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; 1761 for (i = 0; i < adev->sdma.num_instances; i++) 1762 adev->vm_manager.vm_pte_rings[i] = 1763 &adev->sdma.instance[i].ring; 1764 1765 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; 1766 } 1767 } 1768 1769 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { 1770 .type = AMD_IP_BLOCK_TYPE_SDMA, 1771 .major = 4, 1772 .minor = 0, 1773 .rev = 0, 1774 .funcs = &sdma_v4_0_ip_funcs, 1775 }; 1776