1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2012 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev */ 23*b843c749SSergey Zigachev #ifndef __SI_DPM_H__ 24*b843c749SSergey Zigachev #define __SI_DPM_H__ 25*b843c749SSergey Zigachev 26*b843c749SSergey Zigachev #include "amdgpu_atombios.h" 27*b843c749SSergey Zigachev #include "sislands_smc.h" 28*b843c749SSergey Zigachev 29*b843c749SSergey Zigachev #define MC_CG_CONFIG 0x96f 30*b843c749SSergey Zigachev #define MC_ARB_CG 0x9fa 31*b843c749SSergey Zigachev #define CG_ARB_REQ(x) ((x) << 0) 32*b843c749SSergey Zigachev #define CG_ARB_REQ_MASK (0xff << 0) 33*b843c749SSergey Zigachev 34*b843c749SSergey Zigachev #define MC_ARB_DRAM_TIMING_1 0x9fc 35*b843c749SSergey Zigachev #define MC_ARB_DRAM_TIMING_2 0x9fd 36*b843c749SSergey Zigachev #define MC_ARB_DRAM_TIMING_3 0x9fe 37*b843c749SSergey Zigachev #define MC_ARB_DRAM_TIMING2_1 0x9ff 38*b843c749SSergey Zigachev #define MC_ARB_DRAM_TIMING2_2 0xa00 39*b843c749SSergey Zigachev #define MC_ARB_DRAM_TIMING2_3 0xa01 40*b843c749SSergey Zigachev 41*b843c749SSergey Zigachev #define MAX_NO_OF_MVDD_VALUES 2 42*b843c749SSergey Zigachev #define MAX_NO_VREG_STEPS 32 43*b843c749SSergey Zigachev #define NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16 44*b843c749SSergey Zigachev #define SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE 32 45*b843c749SSergey Zigachev #define SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20 46*b843c749SSergey Zigachev #define RV770_ASI_DFLT 1000 47*b843c749SSergey Zigachev #define CYPRESS_HASI_DFLT 400000 48*b843c749SSergey Zigachev #define PCIE_PERF_REQ_PECI_GEN1 2 49*b843c749SSergey Zigachev #define PCIE_PERF_REQ_PECI_GEN2 3 50*b843c749SSergey Zigachev #define PCIE_PERF_REQ_PECI_GEN3 4 51*b843c749SSergey Zigachev #define RV770_DEFAULT_VCLK_FREQ 53300 /* 10 khz */ 52*b843c749SSergey Zigachev #define RV770_DEFAULT_DCLK_FREQ 40000 /* 10 khz */ 53*b843c749SSergey Zigachev 54*b843c749SSergey Zigachev #define SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE 16 55*b843c749SSergey Zigachev 56*b843c749SSergey Zigachev #define RV770_SMC_TABLE_ADDRESS 0xB000 57*b843c749SSergey Zigachev #define RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 3 58*b843c749SSergey Zigachev 59*b843c749SSergey Zigachev #define SMC_STROBE_RATIO 0x0F 60*b843c749SSergey Zigachev #define SMC_STROBE_ENABLE 0x10 61*b843c749SSergey Zigachev 62*b843c749SSergey Zigachev #define SMC_MC_EDC_RD_FLAG 0x01 63*b843c749SSergey Zigachev #define SMC_MC_EDC_WR_FLAG 0x02 64*b843c749SSergey Zigachev #define SMC_MC_RTT_ENABLE 0x04 65*b843c749SSergey Zigachev #define SMC_MC_STUTTER_EN 0x08 66*b843c749SSergey Zigachev 67*b843c749SSergey Zigachev #define RV770_SMC_VOLTAGEMASK_VDDC 0 68*b843c749SSergey Zigachev #define RV770_SMC_VOLTAGEMASK_MVDD 1 69*b843c749SSergey Zigachev #define RV770_SMC_VOLTAGEMASK_VDDCI 2 70*b843c749SSergey Zigachev #define RV770_SMC_VOLTAGEMASK_MAX 4 71*b843c749SSergey Zigachev 72*b843c749SSergey Zigachev #define NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16 73*b843c749SSergey Zigachev #define NISLANDS_SMC_STROBE_RATIO 0x0F 74*b843c749SSergey Zigachev #define NISLANDS_SMC_STROBE_ENABLE 0x10 75*b843c749SSergey Zigachev 76*b843c749SSergey Zigachev #define NISLANDS_SMC_MC_EDC_RD_FLAG 0x01 77*b843c749SSergey Zigachev #define NISLANDS_SMC_MC_EDC_WR_FLAG 0x02 78*b843c749SSergey Zigachev #define NISLANDS_SMC_MC_RTT_ENABLE 0x04 79*b843c749SSergey Zigachev #define NISLANDS_SMC_MC_STUTTER_EN 0x08 80*b843c749SSergey Zigachev 81*b843c749SSergey Zigachev #define MAX_NO_VREG_STEPS 32 82*b843c749SSergey Zigachev 83*b843c749SSergey Zigachev #define NISLANDS_SMC_VOLTAGEMASK_VDDC 0 84*b843c749SSergey Zigachev #define NISLANDS_SMC_VOLTAGEMASK_MVDD 1 85*b843c749SSergey Zigachev #define NISLANDS_SMC_VOLTAGEMASK_VDDCI 2 86*b843c749SSergey Zigachev #define NISLANDS_SMC_VOLTAGEMASK_MAX 4 87*b843c749SSergey Zigachev 88*b843c749SSergey Zigachev #define SISLANDS_MCREGISTERTABLE_INITIAL_SLOT 0 89*b843c749SSergey Zigachev #define SISLANDS_MCREGISTERTABLE_ACPI_SLOT 1 90*b843c749SSergey Zigachev #define SISLANDS_MCREGISTERTABLE_ULV_SLOT 2 91*b843c749SSergey Zigachev #define SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT 3 92*b843c749SSergey Zigachev 93*b843c749SSergey Zigachev #define SISLANDS_LEAKAGE_INDEX0 0xff01 94*b843c749SSergey Zigachev #define SISLANDS_MAX_LEAKAGE_COUNT 4 95*b843c749SSergey Zigachev 96*b843c749SSergey Zigachev #define SISLANDS_MAX_HARDWARE_POWERLEVELS 5 97*b843c749SSergey Zigachev #define SISLANDS_INITIAL_STATE_ARB_INDEX 0 98*b843c749SSergey Zigachev #define SISLANDS_ACPI_STATE_ARB_INDEX 1 99*b843c749SSergey Zigachev #define SISLANDS_ULV_STATE_ARB_INDEX 2 100*b843c749SSergey Zigachev #define SISLANDS_DRIVER_STATE_ARB_INDEX 3 101*b843c749SSergey Zigachev 102*b843c749SSergey Zigachev #define SISLANDS_DPM2_MAX_PULSE_SKIP 256 103*b843c749SSergey Zigachev 104*b843c749SSergey Zigachev #define SISLANDS_DPM2_NEAR_TDP_DEC 10 105*b843c749SSergey Zigachev #define SISLANDS_DPM2_ABOVE_SAFE_INC 5 106*b843c749SSergey Zigachev #define SISLANDS_DPM2_BELOW_SAFE_INC 20 107*b843c749SSergey Zigachev 108*b843c749SSergey Zigachev #define SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT 80 109*b843c749SSergey Zigachev 110*b843c749SSergey Zigachev #define SISLANDS_DPM2_MAXPS_PERCENT_H 99 111*b843c749SSergey Zigachev #define SISLANDS_DPM2_MAXPS_PERCENT_M 99 112*b843c749SSergey Zigachev 113*b843c749SSergey Zigachev #define SISLANDS_DPM2_SQ_RAMP_MAX_POWER 0x3FFF 114*b843c749SSergey Zigachev #define SISLANDS_DPM2_SQ_RAMP_MIN_POWER 0x12 115*b843c749SSergey Zigachev #define SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15 116*b843c749SSergey Zigachev #define SISLANDS_DPM2_SQ_RAMP_STI_SIZE 0x1E 117*b843c749SSergey Zigachev #define SISLANDS_DPM2_SQ_RAMP_LTI_RATIO 0xF 118*b843c749SSergey Zigachev 119*b843c749SSergey Zigachev #define SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN 10 120*b843c749SSergey Zigachev 121*b843c749SSergey Zigachev #define SISLANDS_VRC_DFLT 0xC000B3 122*b843c749SSergey Zigachev #define SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT 1687 123*b843c749SSergey Zigachev #define SISLANDS_CGULVPARAMETER_DFLT 0x00040035 124*b843c749SSergey Zigachev #define SISLANDS_CGULVCONTROL_DFLT 0x1f007550 125*b843c749SSergey Zigachev 126*b843c749SSergey Zigachev #define SI_ASI_DFLT 10000 127*b843c749SSergey Zigachev #define SI_BSP_DFLT 0x41EB 128*b843c749SSergey Zigachev #define SI_BSU_DFLT 0x2 129*b843c749SSergey Zigachev #define SI_AH_DFLT 5 130*b843c749SSergey Zigachev #define SI_RLP_DFLT 25 131*b843c749SSergey Zigachev #define SI_RMP_DFLT 65 132*b843c749SSergey Zigachev #define SI_LHP_DFLT 40 133*b843c749SSergey Zigachev #define SI_LMP_DFLT 15 134*b843c749SSergey Zigachev #define SI_TD_DFLT 0 135*b843c749SSergey Zigachev #define SI_UTC_DFLT_00 0x24 136*b843c749SSergey Zigachev #define SI_UTC_DFLT_01 0x22 137*b843c749SSergey Zigachev #define SI_UTC_DFLT_02 0x22 138*b843c749SSergey Zigachev #define SI_UTC_DFLT_03 0x22 139*b843c749SSergey Zigachev #define SI_UTC_DFLT_04 0x22 140*b843c749SSergey Zigachev #define SI_UTC_DFLT_05 0x22 141*b843c749SSergey Zigachev #define SI_UTC_DFLT_06 0x22 142*b843c749SSergey Zigachev #define SI_UTC_DFLT_07 0x22 143*b843c749SSergey Zigachev #define SI_UTC_DFLT_08 0x22 144*b843c749SSergey Zigachev #define SI_UTC_DFLT_09 0x22 145*b843c749SSergey Zigachev #define SI_UTC_DFLT_10 0x22 146*b843c749SSergey Zigachev #define SI_UTC_DFLT_11 0x22 147*b843c749SSergey Zigachev #define SI_UTC_DFLT_12 0x22 148*b843c749SSergey Zigachev #define SI_UTC_DFLT_13 0x22 149*b843c749SSergey Zigachev #define SI_UTC_DFLT_14 0x22 150*b843c749SSergey Zigachev #define SI_DTC_DFLT_00 0x24 151*b843c749SSergey Zigachev #define SI_DTC_DFLT_01 0x22 152*b843c749SSergey Zigachev #define SI_DTC_DFLT_02 0x22 153*b843c749SSergey Zigachev #define SI_DTC_DFLT_03 0x22 154*b843c749SSergey Zigachev #define SI_DTC_DFLT_04 0x22 155*b843c749SSergey Zigachev #define SI_DTC_DFLT_05 0x22 156*b843c749SSergey Zigachev #define SI_DTC_DFLT_06 0x22 157*b843c749SSergey Zigachev #define SI_DTC_DFLT_07 0x22 158*b843c749SSergey Zigachev #define SI_DTC_DFLT_08 0x22 159*b843c749SSergey Zigachev #define SI_DTC_DFLT_09 0x22 160*b843c749SSergey Zigachev #define SI_DTC_DFLT_10 0x22 161*b843c749SSergey Zigachev #define SI_DTC_DFLT_11 0x22 162*b843c749SSergey Zigachev #define SI_DTC_DFLT_12 0x22 163*b843c749SSergey Zigachev #define SI_DTC_DFLT_13 0x22 164*b843c749SSergey Zigachev #define SI_DTC_DFLT_14 0x22 165*b843c749SSergey Zigachev #define SI_VRC_DFLT 0x0000C003 166*b843c749SSergey Zigachev #define SI_VOLTAGERESPONSETIME_DFLT 1000 167*b843c749SSergey Zigachev #define SI_BACKBIASRESPONSETIME_DFLT 1000 168*b843c749SSergey Zigachev #define SI_VRU_DFLT 0x3 169*b843c749SSergey Zigachev #define SI_SPLLSTEPTIME_DFLT 0x1000 170*b843c749SSergey Zigachev #define SI_SPLLSTEPUNIT_DFLT 0x3 171*b843c749SSergey Zigachev #define SI_TPU_DFLT 0 172*b843c749SSergey Zigachev #define SI_TPC_DFLT 0x200 173*b843c749SSergey Zigachev #define SI_SSTU_DFLT 0 174*b843c749SSergey Zigachev #define SI_SST_DFLT 0x00C8 175*b843c749SSergey Zigachev #define SI_GICST_DFLT 0x200 176*b843c749SSergey Zigachev #define SI_FCT_DFLT 0x0400 177*b843c749SSergey Zigachev #define SI_FCTU_DFLT 0 178*b843c749SSergey Zigachev #define SI_CTXCGTT3DRPHC_DFLT 0x20 179*b843c749SSergey Zigachev #define SI_CTXCGTT3DRSDC_DFLT 0x40 180*b843c749SSergey Zigachev #define SI_VDDC3DOORPHC_DFLT 0x100 181*b843c749SSergey Zigachev #define SI_VDDC3DOORSDC_DFLT 0x7 182*b843c749SSergey Zigachev #define SI_VDDC3DOORSU_DFLT 0 183*b843c749SSergey Zigachev #define SI_MPLLLOCKTIME_DFLT 100 184*b843c749SSergey Zigachev #define SI_MPLLRESETTIME_DFLT 150 185*b843c749SSergey Zigachev #define SI_VCOSTEPPCT_DFLT 20 186*b843c749SSergey Zigachev #define SI_ENDINGVCOSTEPPCT_DFLT 5 187*b843c749SSergey Zigachev #define SI_REFERENCEDIVIDER_DFLT 4 188*b843c749SSergey Zigachev 189*b843c749SSergey Zigachev #define SI_PM_NUMBER_OF_TC 15 190*b843c749SSergey Zigachev #define SI_PM_NUMBER_OF_SCLKS 20 191*b843c749SSergey Zigachev #define SI_PM_NUMBER_OF_MCLKS 4 192*b843c749SSergey Zigachev #define SI_PM_NUMBER_OF_VOLTAGE_LEVELS 4 193*b843c749SSergey Zigachev #define SI_PM_NUMBER_OF_ACTIVITY_LEVELS 3 194*b843c749SSergey Zigachev 195*b843c749SSergey Zigachev /* XXX are these ok? */ 196*b843c749SSergey Zigachev #define SI_TEMP_RANGE_MIN (90 * 1000) 197*b843c749SSergey Zigachev #define SI_TEMP_RANGE_MAX (120 * 1000) 198*b843c749SSergey Zigachev 199*b843c749SSergey Zigachev #define FDO_PWM_MODE_STATIC 1 200*b843c749SSergey Zigachev #define FDO_PWM_MODE_STATIC_RPM 5 201*b843c749SSergey Zigachev 202*b843c749SSergey Zigachev enum ni_dc_cac_level 203*b843c749SSergey Zigachev { 204*b843c749SSergey Zigachev NISLANDS_DCCAC_LEVEL_0 = 0, 205*b843c749SSergey Zigachev NISLANDS_DCCAC_LEVEL_1, 206*b843c749SSergey Zigachev NISLANDS_DCCAC_LEVEL_2, 207*b843c749SSergey Zigachev NISLANDS_DCCAC_LEVEL_3, 208*b843c749SSergey Zigachev NISLANDS_DCCAC_LEVEL_4, 209*b843c749SSergey Zigachev NISLANDS_DCCAC_LEVEL_5, 210*b843c749SSergey Zigachev NISLANDS_DCCAC_LEVEL_6, 211*b843c749SSergey Zigachev NISLANDS_DCCAC_LEVEL_7, 212*b843c749SSergey Zigachev NISLANDS_DCCAC_MAX_LEVELS 213*b843c749SSergey Zigachev }; 214*b843c749SSergey Zigachev 215*b843c749SSergey Zigachev enum si_cac_config_reg_type 216*b843c749SSergey Zigachev { 217*b843c749SSergey Zigachev SISLANDS_CACCONFIG_MMR = 0, 218*b843c749SSergey Zigachev SISLANDS_CACCONFIG_CGIND, 219*b843c749SSergey Zigachev SISLANDS_CACCONFIG_MAX 220*b843c749SSergey Zigachev }; 221*b843c749SSergey Zigachev 222*b843c749SSergey Zigachev enum si_power_level { 223*b843c749SSergey Zigachev SI_POWER_LEVEL_LOW = 0, 224*b843c749SSergey Zigachev SI_POWER_LEVEL_MEDIUM = 1, 225*b843c749SSergey Zigachev SI_POWER_LEVEL_HIGH = 2, 226*b843c749SSergey Zigachev SI_POWER_LEVEL_CTXSW = 3, 227*b843c749SSergey Zigachev }; 228*b843c749SSergey Zigachev 229*b843c749SSergey Zigachev enum si_td { 230*b843c749SSergey Zigachev SI_TD_AUTO, 231*b843c749SSergey Zigachev SI_TD_UP, 232*b843c749SSergey Zigachev SI_TD_DOWN, 233*b843c749SSergey Zigachev }; 234*b843c749SSergey Zigachev 235*b843c749SSergey Zigachev enum si_display_watermark { 236*b843c749SSergey Zigachev SI_DISPLAY_WATERMARK_LOW = 0, 237*b843c749SSergey Zigachev SI_DISPLAY_WATERMARK_HIGH = 1, 238*b843c749SSergey Zigachev }; 239*b843c749SSergey Zigachev 240*b843c749SSergey Zigachev enum si_display_gap 241*b843c749SSergey Zigachev { 242*b843c749SSergey Zigachev SI_PM_DISPLAY_GAP_VBLANK_OR_WM = 0, 243*b843c749SSergey Zigachev SI_PM_DISPLAY_GAP_VBLANK = 1, 244*b843c749SSergey Zigachev SI_PM_DISPLAY_GAP_WATERMARK = 2, 245*b843c749SSergey Zigachev SI_PM_DISPLAY_GAP_IGNORE = 3, 246*b843c749SSergey Zigachev }; 247*b843c749SSergey Zigachev 248*b843c749SSergey Zigachev extern const struct amdgpu_ip_block_version si_smu_ip_block; 249*b843c749SSergey Zigachev 250*b843c749SSergey Zigachev struct ni_leakage_coeffients 251*b843c749SSergey Zigachev { 252*b843c749SSergey Zigachev u32 at; 253*b843c749SSergey Zigachev u32 bt; 254*b843c749SSergey Zigachev u32 av; 255*b843c749SSergey Zigachev u32 bv; 256*b843c749SSergey Zigachev s32 t_slope; 257*b843c749SSergey Zigachev s32 t_intercept; 258*b843c749SSergey Zigachev u32 t_ref; 259*b843c749SSergey Zigachev }; 260*b843c749SSergey Zigachev 261*b843c749SSergey Zigachev struct SMC_Evergreen_MCRegisterAddress 262*b843c749SSergey Zigachev { 263*b843c749SSergey Zigachev uint16_t s0; 264*b843c749SSergey Zigachev uint16_t s1; 265*b843c749SSergey Zigachev }; 266*b843c749SSergey Zigachev 267*b843c749SSergey Zigachev typedef struct SMC_Evergreen_MCRegisterAddress SMC_Evergreen_MCRegisterAddress; 268*b843c749SSergey Zigachev 269*b843c749SSergey Zigachev struct evergreen_mc_reg_entry { 270*b843c749SSergey Zigachev u32 mclk_max; 271*b843c749SSergey Zigachev u32 mc_data[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; 272*b843c749SSergey Zigachev }; 273*b843c749SSergey Zigachev 274*b843c749SSergey Zigachev struct evergreen_mc_reg_table { 275*b843c749SSergey Zigachev u8 last; 276*b843c749SSergey Zigachev u8 num_entries; 277*b843c749SSergey Zigachev u16 valid_flag; 278*b843c749SSergey Zigachev struct evergreen_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; 279*b843c749SSergey Zigachev SMC_Evergreen_MCRegisterAddress mc_reg_address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; 280*b843c749SSergey Zigachev }; 281*b843c749SSergey Zigachev 282*b843c749SSergey Zigachev struct SMC_Evergreen_MCRegisterSet 283*b843c749SSergey Zigachev { 284*b843c749SSergey Zigachev uint32_t value[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; 285*b843c749SSergey Zigachev }; 286*b843c749SSergey Zigachev 287*b843c749SSergey Zigachev typedef struct SMC_Evergreen_MCRegisterSet SMC_Evergreen_MCRegisterSet; 288*b843c749SSergey Zigachev 289*b843c749SSergey Zigachev struct SMC_Evergreen_MCRegisters 290*b843c749SSergey Zigachev { 291*b843c749SSergey Zigachev uint8_t last; 292*b843c749SSergey Zigachev uint8_t reserved[3]; 293*b843c749SSergey Zigachev SMC_Evergreen_MCRegisterAddress address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; 294*b843c749SSergey Zigachev SMC_Evergreen_MCRegisterSet data[5]; 295*b843c749SSergey Zigachev }; 296*b843c749SSergey Zigachev 297*b843c749SSergey Zigachev typedef struct SMC_Evergreen_MCRegisters SMC_Evergreen_MCRegisters; 298*b843c749SSergey Zigachev 299*b843c749SSergey Zigachev struct SMC_NIslands_MCRegisterSet 300*b843c749SSergey Zigachev { 301*b843c749SSergey Zigachev uint32_t value[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; 302*b843c749SSergey Zigachev }; 303*b843c749SSergey Zigachev 304*b843c749SSergey Zigachev typedef struct SMC_NIslands_MCRegisterSet SMC_NIslands_MCRegisterSet; 305*b843c749SSergey Zigachev 306*b843c749SSergey Zigachev struct ni_mc_reg_entry { 307*b843c749SSergey Zigachev u32 mclk_max; 308*b843c749SSergey Zigachev u32 mc_data[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; 309*b843c749SSergey Zigachev }; 310*b843c749SSergey Zigachev 311*b843c749SSergey Zigachev struct SMC_NIslands_MCRegisterAddress 312*b843c749SSergey Zigachev { 313*b843c749SSergey Zigachev uint16_t s0; 314*b843c749SSergey Zigachev uint16_t s1; 315*b843c749SSergey Zigachev }; 316*b843c749SSergey Zigachev 317*b843c749SSergey Zigachev typedef struct SMC_NIslands_MCRegisterAddress SMC_NIslands_MCRegisterAddress; 318*b843c749SSergey Zigachev 319*b843c749SSergey Zigachev struct SMC_NIslands_MCRegisters 320*b843c749SSergey Zigachev { 321*b843c749SSergey Zigachev uint8_t last; 322*b843c749SSergey Zigachev uint8_t reserved[3]; 323*b843c749SSergey Zigachev SMC_NIslands_MCRegisterAddress address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; 324*b843c749SSergey Zigachev SMC_NIslands_MCRegisterSet data[SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT]; 325*b843c749SSergey Zigachev }; 326*b843c749SSergey Zigachev 327*b843c749SSergey Zigachev typedef struct SMC_NIslands_MCRegisters SMC_NIslands_MCRegisters; 328*b843c749SSergey Zigachev 329*b843c749SSergey Zigachev struct evergreen_ulv_param { 330*b843c749SSergey Zigachev bool supported; 331*b843c749SSergey Zigachev struct rv7xx_pl *pl; 332*b843c749SSergey Zigachev }; 333*b843c749SSergey Zigachev 334*b843c749SSergey Zigachev struct evergreen_arb_registers { 335*b843c749SSergey Zigachev u32 mc_arb_dram_timing; 336*b843c749SSergey Zigachev u32 mc_arb_dram_timing2; 337*b843c749SSergey Zigachev u32 mc_arb_rfsh_rate; 338*b843c749SSergey Zigachev u32 mc_arb_burst_time; 339*b843c749SSergey Zigachev }; 340*b843c749SSergey Zigachev 341*b843c749SSergey Zigachev struct at { 342*b843c749SSergey Zigachev u32 rlp; 343*b843c749SSergey Zigachev u32 rmp; 344*b843c749SSergey Zigachev u32 lhp; 345*b843c749SSergey Zigachev u32 lmp; 346*b843c749SSergey Zigachev }; 347*b843c749SSergey Zigachev 348*b843c749SSergey Zigachev struct ni_clock_registers { 349*b843c749SSergey Zigachev u32 cg_spll_func_cntl; 350*b843c749SSergey Zigachev u32 cg_spll_func_cntl_2; 351*b843c749SSergey Zigachev u32 cg_spll_func_cntl_3; 352*b843c749SSergey Zigachev u32 cg_spll_func_cntl_4; 353*b843c749SSergey Zigachev u32 cg_spll_spread_spectrum; 354*b843c749SSergey Zigachev u32 cg_spll_spread_spectrum_2; 355*b843c749SSergey Zigachev u32 mclk_pwrmgt_cntl; 356*b843c749SSergey Zigachev u32 dll_cntl; 357*b843c749SSergey Zigachev u32 mpll_ad_func_cntl; 358*b843c749SSergey Zigachev u32 mpll_ad_func_cntl_2; 359*b843c749SSergey Zigachev u32 mpll_dq_func_cntl; 360*b843c749SSergey Zigachev u32 mpll_dq_func_cntl_2; 361*b843c749SSergey Zigachev u32 mpll_ss1; 362*b843c749SSergey Zigachev u32 mpll_ss2; 363*b843c749SSergey Zigachev }; 364*b843c749SSergey Zigachev 365*b843c749SSergey Zigachev struct RV770_SMC_SCLK_VALUE 366*b843c749SSergey Zigachev { 367*b843c749SSergey Zigachev uint32_t vCG_SPLL_FUNC_CNTL; 368*b843c749SSergey Zigachev uint32_t vCG_SPLL_FUNC_CNTL_2; 369*b843c749SSergey Zigachev uint32_t vCG_SPLL_FUNC_CNTL_3; 370*b843c749SSergey Zigachev uint32_t vCG_SPLL_SPREAD_SPECTRUM; 371*b843c749SSergey Zigachev uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; 372*b843c749SSergey Zigachev uint32_t sclk_value; 373*b843c749SSergey Zigachev }; 374*b843c749SSergey Zigachev 375*b843c749SSergey Zigachev typedef struct RV770_SMC_SCLK_VALUE RV770_SMC_SCLK_VALUE; 376*b843c749SSergey Zigachev 377*b843c749SSergey Zigachev struct RV770_SMC_MCLK_VALUE 378*b843c749SSergey Zigachev { 379*b843c749SSergey Zigachev uint32_t vMPLL_AD_FUNC_CNTL; 380*b843c749SSergey Zigachev uint32_t vMPLL_AD_FUNC_CNTL_2; 381*b843c749SSergey Zigachev uint32_t vMPLL_DQ_FUNC_CNTL; 382*b843c749SSergey Zigachev uint32_t vMPLL_DQ_FUNC_CNTL_2; 383*b843c749SSergey Zigachev uint32_t vMCLK_PWRMGT_CNTL; 384*b843c749SSergey Zigachev uint32_t vDLL_CNTL; 385*b843c749SSergey Zigachev uint32_t vMPLL_SS; 386*b843c749SSergey Zigachev uint32_t vMPLL_SS2; 387*b843c749SSergey Zigachev uint32_t mclk_value; 388*b843c749SSergey Zigachev }; 389*b843c749SSergey Zigachev 390*b843c749SSergey Zigachev typedef struct RV770_SMC_MCLK_VALUE RV770_SMC_MCLK_VALUE; 391*b843c749SSergey Zigachev 392*b843c749SSergey Zigachev 393*b843c749SSergey Zigachev struct RV730_SMC_MCLK_VALUE 394*b843c749SSergey Zigachev { 395*b843c749SSergey Zigachev uint32_t vMCLK_PWRMGT_CNTL; 396*b843c749SSergey Zigachev uint32_t vDLL_CNTL; 397*b843c749SSergey Zigachev uint32_t vMPLL_FUNC_CNTL; 398*b843c749SSergey Zigachev uint32_t vMPLL_FUNC_CNTL2; 399*b843c749SSergey Zigachev uint32_t vMPLL_FUNC_CNTL3; 400*b843c749SSergey Zigachev uint32_t vMPLL_SS; 401*b843c749SSergey Zigachev uint32_t vMPLL_SS2; 402*b843c749SSergey Zigachev uint32_t mclk_value; 403*b843c749SSergey Zigachev }; 404*b843c749SSergey Zigachev 405*b843c749SSergey Zigachev typedef struct RV730_SMC_MCLK_VALUE RV730_SMC_MCLK_VALUE; 406*b843c749SSergey Zigachev 407*b843c749SSergey Zigachev struct RV770_SMC_VOLTAGE_VALUE 408*b843c749SSergey Zigachev { 409*b843c749SSergey Zigachev uint16_t value; 410*b843c749SSergey Zigachev uint8_t index; 411*b843c749SSergey Zigachev uint8_t padding; 412*b843c749SSergey Zigachev }; 413*b843c749SSergey Zigachev 414*b843c749SSergey Zigachev typedef struct RV770_SMC_VOLTAGE_VALUE RV770_SMC_VOLTAGE_VALUE; 415*b843c749SSergey Zigachev 416*b843c749SSergey Zigachev union RV7XX_SMC_MCLK_VALUE 417*b843c749SSergey Zigachev { 418*b843c749SSergey Zigachev RV770_SMC_MCLK_VALUE mclk770; 419*b843c749SSergey Zigachev RV730_SMC_MCLK_VALUE mclk730; 420*b843c749SSergey Zigachev }; 421*b843c749SSergey Zigachev 422*b843c749SSergey Zigachev typedef union RV7XX_SMC_MCLK_VALUE RV7XX_SMC_MCLK_VALUE, *LPRV7XX_SMC_MCLK_VALUE; 423*b843c749SSergey Zigachev 424*b843c749SSergey Zigachev struct RV770_SMC_HW_PERFORMANCE_LEVEL 425*b843c749SSergey Zigachev { 426*b843c749SSergey Zigachev uint8_t arbValue; 427*b843c749SSergey Zigachev union{ 428*b843c749SSergey Zigachev uint8_t seqValue; 429*b843c749SSergey Zigachev uint8_t ACIndex; 430*b843c749SSergey Zigachev }; 431*b843c749SSergey Zigachev uint8_t displayWatermark; 432*b843c749SSergey Zigachev uint8_t gen2PCIE; 433*b843c749SSergey Zigachev uint8_t gen2XSP; 434*b843c749SSergey Zigachev uint8_t backbias; 435*b843c749SSergey Zigachev uint8_t strobeMode; 436*b843c749SSergey Zigachev uint8_t mcFlags; 437*b843c749SSergey Zigachev uint32_t aT; 438*b843c749SSergey Zigachev uint32_t bSP; 439*b843c749SSergey Zigachev RV770_SMC_SCLK_VALUE sclk; 440*b843c749SSergey Zigachev RV7XX_SMC_MCLK_VALUE mclk; 441*b843c749SSergey Zigachev RV770_SMC_VOLTAGE_VALUE vddc; 442*b843c749SSergey Zigachev RV770_SMC_VOLTAGE_VALUE mvdd; 443*b843c749SSergey Zigachev RV770_SMC_VOLTAGE_VALUE vddci; 444*b843c749SSergey Zigachev uint8_t reserved1; 445*b843c749SSergey Zigachev uint8_t reserved2; 446*b843c749SSergey Zigachev uint8_t stateFlags; 447*b843c749SSergey Zigachev uint8_t padding; 448*b843c749SSergey Zigachev }; 449*b843c749SSergey Zigachev 450*b843c749SSergey Zigachev typedef struct RV770_SMC_HW_PERFORMANCE_LEVEL RV770_SMC_HW_PERFORMANCE_LEVEL; 451*b843c749SSergey Zigachev 452*b843c749SSergey Zigachev struct RV770_SMC_SWSTATE 453*b843c749SSergey Zigachev { 454*b843c749SSergey Zigachev uint8_t flags; 455*b843c749SSergey Zigachev uint8_t padding1; 456*b843c749SSergey Zigachev uint8_t padding2; 457*b843c749SSergey Zigachev uint8_t padding3; 458*b843c749SSergey Zigachev RV770_SMC_HW_PERFORMANCE_LEVEL levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE]; 459*b843c749SSergey Zigachev }; 460*b843c749SSergey Zigachev 461*b843c749SSergey Zigachev typedef struct RV770_SMC_SWSTATE RV770_SMC_SWSTATE; 462*b843c749SSergey Zigachev 463*b843c749SSergey Zigachev struct RV770_SMC_VOLTAGEMASKTABLE 464*b843c749SSergey Zigachev { 465*b843c749SSergey Zigachev uint8_t highMask[RV770_SMC_VOLTAGEMASK_MAX]; 466*b843c749SSergey Zigachev uint32_t lowMask[RV770_SMC_VOLTAGEMASK_MAX]; 467*b843c749SSergey Zigachev }; 468*b843c749SSergey Zigachev 469*b843c749SSergey Zigachev typedef struct RV770_SMC_VOLTAGEMASKTABLE RV770_SMC_VOLTAGEMASKTABLE; 470*b843c749SSergey Zigachev 471*b843c749SSergey Zigachev struct RV770_SMC_STATETABLE 472*b843c749SSergey Zigachev { 473*b843c749SSergey Zigachev uint8_t thermalProtectType; 474*b843c749SSergey Zigachev uint8_t systemFlags; 475*b843c749SSergey Zigachev uint8_t maxVDDCIndexInPPTable; 476*b843c749SSergey Zigachev uint8_t extraFlags; 477*b843c749SSergey Zigachev uint8_t highSMIO[MAX_NO_VREG_STEPS]; 478*b843c749SSergey Zigachev uint32_t lowSMIO[MAX_NO_VREG_STEPS]; 479*b843c749SSergey Zigachev RV770_SMC_VOLTAGEMASKTABLE voltageMaskTable; 480*b843c749SSergey Zigachev RV770_SMC_SWSTATE initialState; 481*b843c749SSergey Zigachev RV770_SMC_SWSTATE ACPIState; 482*b843c749SSergey Zigachev RV770_SMC_SWSTATE driverState; 483*b843c749SSergey Zigachev RV770_SMC_SWSTATE ULVState; 484*b843c749SSergey Zigachev }; 485*b843c749SSergey Zigachev 486*b843c749SSergey Zigachev typedef struct RV770_SMC_STATETABLE RV770_SMC_STATETABLE; 487*b843c749SSergey Zigachev 488*b843c749SSergey Zigachev struct vddc_table_entry { 489*b843c749SSergey Zigachev u16 vddc; 490*b843c749SSergey Zigachev u8 vddc_index; 491*b843c749SSergey Zigachev u8 high_smio; 492*b843c749SSergey Zigachev u32 low_smio; 493*b843c749SSergey Zigachev }; 494*b843c749SSergey Zigachev 495*b843c749SSergey Zigachev struct rv770_clock_registers { 496*b843c749SSergey Zigachev u32 cg_spll_func_cntl; 497*b843c749SSergey Zigachev u32 cg_spll_func_cntl_2; 498*b843c749SSergey Zigachev u32 cg_spll_func_cntl_3; 499*b843c749SSergey Zigachev u32 cg_spll_spread_spectrum; 500*b843c749SSergey Zigachev u32 cg_spll_spread_spectrum_2; 501*b843c749SSergey Zigachev u32 mpll_ad_func_cntl; 502*b843c749SSergey Zigachev u32 mpll_ad_func_cntl_2; 503*b843c749SSergey Zigachev u32 mpll_dq_func_cntl; 504*b843c749SSergey Zigachev u32 mpll_dq_func_cntl_2; 505*b843c749SSergey Zigachev u32 mclk_pwrmgt_cntl; 506*b843c749SSergey Zigachev u32 dll_cntl; 507*b843c749SSergey Zigachev u32 mpll_ss1; 508*b843c749SSergey Zigachev u32 mpll_ss2; 509*b843c749SSergey Zigachev }; 510*b843c749SSergey Zigachev 511*b843c749SSergey Zigachev struct rv730_clock_registers { 512*b843c749SSergey Zigachev u32 cg_spll_func_cntl; 513*b843c749SSergey Zigachev u32 cg_spll_func_cntl_2; 514*b843c749SSergey Zigachev u32 cg_spll_func_cntl_3; 515*b843c749SSergey Zigachev u32 cg_spll_spread_spectrum; 516*b843c749SSergey Zigachev u32 cg_spll_spread_spectrum_2; 517*b843c749SSergey Zigachev u32 mclk_pwrmgt_cntl; 518*b843c749SSergey Zigachev u32 dll_cntl; 519*b843c749SSergey Zigachev u32 mpll_func_cntl; 520*b843c749SSergey Zigachev u32 mpll_func_cntl2; 521*b843c749SSergey Zigachev u32 mpll_func_cntl3; 522*b843c749SSergey Zigachev u32 mpll_ss; 523*b843c749SSergey Zigachev u32 mpll_ss2; 524*b843c749SSergey Zigachev }; 525*b843c749SSergey Zigachev 526*b843c749SSergey Zigachev union r7xx_clock_registers { 527*b843c749SSergey Zigachev struct rv770_clock_registers rv770; 528*b843c749SSergey Zigachev struct rv730_clock_registers rv730; 529*b843c749SSergey Zigachev }; 530*b843c749SSergey Zigachev 531*b843c749SSergey Zigachev struct rv7xx_power_info { 532*b843c749SSergey Zigachev /* flags */ 533*b843c749SSergey Zigachev bool mem_gddr5; 534*b843c749SSergey Zigachev bool pcie_gen2; 535*b843c749SSergey Zigachev bool dynamic_pcie_gen2; 536*b843c749SSergey Zigachev bool acpi_pcie_gen2; 537*b843c749SSergey Zigachev bool boot_in_gen2; 538*b843c749SSergey Zigachev bool voltage_control; /* vddc */ 539*b843c749SSergey Zigachev bool mvdd_control; 540*b843c749SSergey Zigachev bool sclk_ss; 541*b843c749SSergey Zigachev bool mclk_ss; 542*b843c749SSergey Zigachev bool dynamic_ss; 543*b843c749SSergey Zigachev bool gfx_clock_gating; 544*b843c749SSergey Zigachev bool mg_clock_gating; 545*b843c749SSergey Zigachev bool mgcgtssm; 546*b843c749SSergey Zigachev bool power_gating; 547*b843c749SSergey Zigachev bool thermal_protection; 548*b843c749SSergey Zigachev bool display_gap; 549*b843c749SSergey Zigachev bool dcodt; 550*b843c749SSergey Zigachev bool ulps; 551*b843c749SSergey Zigachev /* registers */ 552*b843c749SSergey Zigachev union r7xx_clock_registers clk_regs; 553*b843c749SSergey Zigachev u32 s0_vid_lower_smio_cntl; 554*b843c749SSergey Zigachev /* voltage */ 555*b843c749SSergey Zigachev u32 vddc_mask_low; 556*b843c749SSergey Zigachev u32 mvdd_mask_low; 557*b843c749SSergey Zigachev u32 mvdd_split_frequency; 558*b843c749SSergey Zigachev u32 mvdd_low_smio[MAX_NO_OF_MVDD_VALUES]; 559*b843c749SSergey Zigachev u16 max_vddc; 560*b843c749SSergey Zigachev u16 max_vddc_in_table; 561*b843c749SSergey Zigachev u16 min_vddc_in_table; 562*b843c749SSergey Zigachev struct vddc_table_entry vddc_table[MAX_NO_VREG_STEPS]; 563*b843c749SSergey Zigachev u8 valid_vddc_entries; 564*b843c749SSergey Zigachev /* dc odt */ 565*b843c749SSergey Zigachev u32 mclk_odt_threshold; 566*b843c749SSergey Zigachev u8 odt_value_0[2]; 567*b843c749SSergey Zigachev u8 odt_value_1[2]; 568*b843c749SSergey Zigachev /* stored values */ 569*b843c749SSergey Zigachev u32 boot_sclk; 570*b843c749SSergey Zigachev u16 acpi_vddc; 571*b843c749SSergey Zigachev u32 ref_div; 572*b843c749SSergey Zigachev u32 active_auto_throttle_sources; 573*b843c749SSergey Zigachev u32 mclk_stutter_mode_threshold; 574*b843c749SSergey Zigachev u32 mclk_strobe_mode_threshold; 575*b843c749SSergey Zigachev u32 mclk_edc_enable_threshold; 576*b843c749SSergey Zigachev u32 bsp; 577*b843c749SSergey Zigachev u32 bsu; 578*b843c749SSergey Zigachev u32 pbsp; 579*b843c749SSergey Zigachev u32 pbsu; 580*b843c749SSergey Zigachev u32 dsp; 581*b843c749SSergey Zigachev u32 psp; 582*b843c749SSergey Zigachev u32 asi; 583*b843c749SSergey Zigachev u32 pasi; 584*b843c749SSergey Zigachev u32 vrc; 585*b843c749SSergey Zigachev u32 restricted_levels; 586*b843c749SSergey Zigachev u32 rlp; 587*b843c749SSergey Zigachev u32 rmp; 588*b843c749SSergey Zigachev u32 lhp; 589*b843c749SSergey Zigachev u32 lmp; 590*b843c749SSergey Zigachev /* smc offsets */ 591*b843c749SSergey Zigachev u16 state_table_start; 592*b843c749SSergey Zigachev u16 soft_regs_start; 593*b843c749SSergey Zigachev u16 sram_end; 594*b843c749SSergey Zigachev /* scratch structs */ 595*b843c749SSergey Zigachev RV770_SMC_STATETABLE smc_statetable; 596*b843c749SSergey Zigachev }; 597*b843c749SSergey Zigachev 598*b843c749SSergey Zigachev struct rv7xx_pl { 599*b843c749SSergey Zigachev u32 sclk; 600*b843c749SSergey Zigachev u32 mclk; 601*b843c749SSergey Zigachev u16 vddc; 602*b843c749SSergey Zigachev u16 vddci; /* eg+ only */ 603*b843c749SSergey Zigachev u32 flags; 604*b843c749SSergey Zigachev enum amdgpu_pcie_gen pcie_gen; /* si+ only */ 605*b843c749SSergey Zigachev }; 606*b843c749SSergey Zigachev 607*b843c749SSergey Zigachev struct rv7xx_ps { 608*b843c749SSergey Zigachev struct rv7xx_pl high; 609*b843c749SSergey Zigachev struct rv7xx_pl medium; 610*b843c749SSergey Zigachev struct rv7xx_pl low; 611*b843c749SSergey Zigachev bool dc_compatible; 612*b843c749SSergey Zigachev }; 613*b843c749SSergey Zigachev 614*b843c749SSergey Zigachev struct si_ps { 615*b843c749SSergey Zigachev u16 performance_level_count; 616*b843c749SSergey Zigachev bool dc_compatible; 617*b843c749SSergey Zigachev struct rv7xx_pl performance_levels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE]; 618*b843c749SSergey Zigachev }; 619*b843c749SSergey Zigachev 620*b843c749SSergey Zigachev struct ni_mc_reg_table { 621*b843c749SSergey Zigachev u8 last; 622*b843c749SSergey Zigachev u8 num_entries; 623*b843c749SSergey Zigachev u16 valid_flag; 624*b843c749SSergey Zigachev struct ni_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; 625*b843c749SSergey Zigachev SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; 626*b843c749SSergey Zigachev }; 627*b843c749SSergey Zigachev 628*b843c749SSergey Zigachev struct ni_cac_data 629*b843c749SSergey Zigachev { 630*b843c749SSergey Zigachev struct ni_leakage_coeffients leakage_coefficients; 631*b843c749SSergey Zigachev u32 i_leakage; 632*b843c749SSergey Zigachev s32 leakage_minimum_temperature; 633*b843c749SSergey Zigachev u32 pwr_const; 634*b843c749SSergey Zigachev u32 dc_cac_value; 635*b843c749SSergey Zigachev u32 bif_cac_value; 636*b843c749SSergey Zigachev u32 lkge_pwr; 637*b843c749SSergey Zigachev u8 mc_wr_weight; 638*b843c749SSergey Zigachev u8 mc_rd_weight; 639*b843c749SSergey Zigachev u8 allow_ovrflw; 640*b843c749SSergey Zigachev u8 num_win_tdp; 641*b843c749SSergey Zigachev u8 l2num_win_tdp; 642*b843c749SSergey Zigachev u8 lts_truncate_n; 643*b843c749SSergey Zigachev }; 644*b843c749SSergey Zigachev 645*b843c749SSergey Zigachev struct evergreen_power_info { 646*b843c749SSergey Zigachev /* must be first! */ 647*b843c749SSergey Zigachev struct rv7xx_power_info rv7xx; 648*b843c749SSergey Zigachev /* flags */ 649*b843c749SSergey Zigachev bool vddci_control; 650*b843c749SSergey Zigachev bool dynamic_ac_timing; 651*b843c749SSergey Zigachev bool abm; 652*b843c749SSergey Zigachev bool mcls; 653*b843c749SSergey Zigachev bool light_sleep; 654*b843c749SSergey Zigachev bool memory_transition; 655*b843c749SSergey Zigachev bool pcie_performance_request; 656*b843c749SSergey Zigachev bool pcie_performance_request_registered; 657*b843c749SSergey Zigachev bool sclk_deep_sleep; 658*b843c749SSergey Zigachev bool dll_default_on; 659*b843c749SSergey Zigachev bool ls_clock_gating; 660*b843c749SSergey Zigachev bool smu_uvd_hs; 661*b843c749SSergey Zigachev bool uvd_enabled; 662*b843c749SSergey Zigachev /* stored values */ 663*b843c749SSergey Zigachev u16 acpi_vddci; 664*b843c749SSergey Zigachev u8 mvdd_high_index; 665*b843c749SSergey Zigachev u8 mvdd_low_index; 666*b843c749SSergey Zigachev u32 mclk_edc_wr_enable_threshold; 667*b843c749SSergey Zigachev struct evergreen_mc_reg_table mc_reg_table; 668*b843c749SSergey Zigachev struct atom_voltage_table vddc_voltage_table; 669*b843c749SSergey Zigachev struct atom_voltage_table vddci_voltage_table; 670*b843c749SSergey Zigachev struct evergreen_arb_registers bootup_arb_registers; 671*b843c749SSergey Zigachev struct evergreen_ulv_param ulv; 672*b843c749SSergey Zigachev struct at ats[2]; 673*b843c749SSergey Zigachev /* smc offsets */ 674*b843c749SSergey Zigachev u16 mc_reg_table_start; 675*b843c749SSergey Zigachev struct amdgpu_ps current_rps; 676*b843c749SSergey Zigachev struct rv7xx_ps current_ps; 677*b843c749SSergey Zigachev struct amdgpu_ps requested_rps; 678*b843c749SSergey Zigachev struct rv7xx_ps requested_ps; 679*b843c749SSergey Zigachev }; 680*b843c749SSergey Zigachev 681*b843c749SSergey Zigachev struct PP_NIslands_Dpm2PerfLevel 682*b843c749SSergey Zigachev { 683*b843c749SSergey Zigachev uint8_t MaxPS; 684*b843c749SSergey Zigachev uint8_t TgtAct; 685*b843c749SSergey Zigachev uint8_t MaxPS_StepInc; 686*b843c749SSergey Zigachev uint8_t MaxPS_StepDec; 687*b843c749SSergey Zigachev uint8_t PSST; 688*b843c749SSergey Zigachev uint8_t NearTDPDec; 689*b843c749SSergey Zigachev uint8_t AboveSafeInc; 690*b843c749SSergey Zigachev uint8_t BelowSafeInc; 691*b843c749SSergey Zigachev uint8_t PSDeltaLimit; 692*b843c749SSergey Zigachev uint8_t PSDeltaWin; 693*b843c749SSergey Zigachev uint8_t Reserved[6]; 694*b843c749SSergey Zigachev }; 695*b843c749SSergey Zigachev 696*b843c749SSergey Zigachev typedef struct PP_NIslands_Dpm2PerfLevel PP_NIslands_Dpm2PerfLevel; 697*b843c749SSergey Zigachev 698*b843c749SSergey Zigachev struct PP_NIslands_DPM2Parameters 699*b843c749SSergey Zigachev { 700*b843c749SSergey Zigachev uint32_t TDPLimit; 701*b843c749SSergey Zigachev uint32_t NearTDPLimit; 702*b843c749SSergey Zigachev uint32_t SafePowerLimit; 703*b843c749SSergey Zigachev uint32_t PowerBoostLimit; 704*b843c749SSergey Zigachev }; 705*b843c749SSergey Zigachev typedef struct PP_NIslands_DPM2Parameters PP_NIslands_DPM2Parameters; 706*b843c749SSergey Zigachev 707*b843c749SSergey Zigachev struct NISLANDS_SMC_SCLK_VALUE 708*b843c749SSergey Zigachev { 709*b843c749SSergey Zigachev uint32_t vCG_SPLL_FUNC_CNTL; 710*b843c749SSergey Zigachev uint32_t vCG_SPLL_FUNC_CNTL_2; 711*b843c749SSergey Zigachev uint32_t vCG_SPLL_FUNC_CNTL_3; 712*b843c749SSergey Zigachev uint32_t vCG_SPLL_FUNC_CNTL_4; 713*b843c749SSergey Zigachev uint32_t vCG_SPLL_SPREAD_SPECTRUM; 714*b843c749SSergey Zigachev uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; 715*b843c749SSergey Zigachev uint32_t sclk_value; 716*b843c749SSergey Zigachev }; 717*b843c749SSergey Zigachev 718*b843c749SSergey Zigachev typedef struct NISLANDS_SMC_SCLK_VALUE NISLANDS_SMC_SCLK_VALUE; 719*b843c749SSergey Zigachev 720*b843c749SSergey Zigachev struct NISLANDS_SMC_MCLK_VALUE 721*b843c749SSergey Zigachev { 722*b843c749SSergey Zigachev uint32_t vMPLL_FUNC_CNTL; 723*b843c749SSergey Zigachev uint32_t vMPLL_FUNC_CNTL_1; 724*b843c749SSergey Zigachev uint32_t vMPLL_FUNC_CNTL_2; 725*b843c749SSergey Zigachev uint32_t vMPLL_AD_FUNC_CNTL; 726*b843c749SSergey Zigachev uint32_t vMPLL_AD_FUNC_CNTL_2; 727*b843c749SSergey Zigachev uint32_t vMPLL_DQ_FUNC_CNTL; 728*b843c749SSergey Zigachev uint32_t vMPLL_DQ_FUNC_CNTL_2; 729*b843c749SSergey Zigachev uint32_t vMCLK_PWRMGT_CNTL; 730*b843c749SSergey Zigachev uint32_t vDLL_CNTL; 731*b843c749SSergey Zigachev uint32_t vMPLL_SS; 732*b843c749SSergey Zigachev uint32_t vMPLL_SS2; 733*b843c749SSergey Zigachev uint32_t mclk_value; 734*b843c749SSergey Zigachev }; 735*b843c749SSergey Zigachev 736*b843c749SSergey Zigachev typedef struct NISLANDS_SMC_MCLK_VALUE NISLANDS_SMC_MCLK_VALUE; 737*b843c749SSergey Zigachev 738*b843c749SSergey Zigachev struct NISLANDS_SMC_VOLTAGE_VALUE 739*b843c749SSergey Zigachev { 740*b843c749SSergey Zigachev uint16_t value; 741*b843c749SSergey Zigachev uint8_t index; 742*b843c749SSergey Zigachev uint8_t padding; 743*b843c749SSergey Zigachev }; 744*b843c749SSergey Zigachev 745*b843c749SSergey Zigachev typedef struct NISLANDS_SMC_VOLTAGE_VALUE NISLANDS_SMC_VOLTAGE_VALUE; 746*b843c749SSergey Zigachev 747*b843c749SSergey Zigachev struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL 748*b843c749SSergey Zigachev { 749*b843c749SSergey Zigachev uint8_t arbValue; 750*b843c749SSergey Zigachev uint8_t ACIndex; 751*b843c749SSergey Zigachev uint8_t displayWatermark; 752*b843c749SSergey Zigachev uint8_t gen2PCIE; 753*b843c749SSergey Zigachev uint8_t reserved1; 754*b843c749SSergey Zigachev uint8_t reserved2; 755*b843c749SSergey Zigachev uint8_t strobeMode; 756*b843c749SSergey Zigachev uint8_t mcFlags; 757*b843c749SSergey Zigachev uint32_t aT; 758*b843c749SSergey Zigachev uint32_t bSP; 759*b843c749SSergey Zigachev NISLANDS_SMC_SCLK_VALUE sclk; 760*b843c749SSergey Zigachev NISLANDS_SMC_MCLK_VALUE mclk; 761*b843c749SSergey Zigachev NISLANDS_SMC_VOLTAGE_VALUE vddc; 762*b843c749SSergey Zigachev NISLANDS_SMC_VOLTAGE_VALUE mvdd; 763*b843c749SSergey Zigachev NISLANDS_SMC_VOLTAGE_VALUE vddci; 764*b843c749SSergey Zigachev NISLANDS_SMC_VOLTAGE_VALUE std_vddc; 765*b843c749SSergey Zigachev uint32_t powergate_en; 766*b843c749SSergey Zigachev uint8_t hUp; 767*b843c749SSergey Zigachev uint8_t hDown; 768*b843c749SSergey Zigachev uint8_t stateFlags; 769*b843c749SSergey Zigachev uint8_t arbRefreshState; 770*b843c749SSergey Zigachev uint32_t SQPowerThrottle; 771*b843c749SSergey Zigachev uint32_t SQPowerThrottle_2; 772*b843c749SSergey Zigachev uint32_t reserved[2]; 773*b843c749SSergey Zigachev PP_NIslands_Dpm2PerfLevel dpm2; 774*b843c749SSergey Zigachev }; 775*b843c749SSergey Zigachev 776*b843c749SSergey Zigachev typedef struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL NISLANDS_SMC_HW_PERFORMANCE_LEVEL; 777*b843c749SSergey Zigachev 778*b843c749SSergey Zigachev struct NISLANDS_SMC_SWSTATE 779*b843c749SSergey Zigachev { 780*b843c749SSergey Zigachev uint8_t flags; 781*b843c749SSergey Zigachev uint8_t levelCount; 782*b843c749SSergey Zigachev uint8_t padding2; 783*b843c749SSergey Zigachev uint8_t padding3; 784*b843c749SSergey Zigachev NISLANDS_SMC_HW_PERFORMANCE_LEVEL levels[1]; 785*b843c749SSergey Zigachev }; 786*b843c749SSergey Zigachev 787*b843c749SSergey Zigachev typedef struct NISLANDS_SMC_SWSTATE NISLANDS_SMC_SWSTATE; 788*b843c749SSergey Zigachev 789*b843c749SSergey Zigachev struct NISLANDS_SMC_VOLTAGEMASKTABLE 790*b843c749SSergey Zigachev { 791*b843c749SSergey Zigachev uint8_t highMask[NISLANDS_SMC_VOLTAGEMASK_MAX]; 792*b843c749SSergey Zigachev uint32_t lowMask[NISLANDS_SMC_VOLTAGEMASK_MAX]; 793*b843c749SSergey Zigachev }; 794*b843c749SSergey Zigachev 795*b843c749SSergey Zigachev typedef struct NISLANDS_SMC_VOLTAGEMASKTABLE NISLANDS_SMC_VOLTAGEMASKTABLE; 796*b843c749SSergey Zigachev 797*b843c749SSergey Zigachev #define NISLANDS_MAX_NO_VREG_STEPS 32 798*b843c749SSergey Zigachev 799*b843c749SSergey Zigachev struct NISLANDS_SMC_STATETABLE 800*b843c749SSergey Zigachev { 801*b843c749SSergey Zigachev uint8_t thermalProtectType; 802*b843c749SSergey Zigachev uint8_t systemFlags; 803*b843c749SSergey Zigachev uint8_t maxVDDCIndexInPPTable; 804*b843c749SSergey Zigachev uint8_t extraFlags; 805*b843c749SSergey Zigachev uint8_t highSMIO[NISLANDS_MAX_NO_VREG_STEPS]; 806*b843c749SSergey Zigachev uint32_t lowSMIO[NISLANDS_MAX_NO_VREG_STEPS]; 807*b843c749SSergey Zigachev NISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable; 808*b843c749SSergey Zigachev PP_NIslands_DPM2Parameters dpm2Params; 809*b843c749SSergey Zigachev NISLANDS_SMC_SWSTATE initialState; 810*b843c749SSergey Zigachev NISLANDS_SMC_SWSTATE ACPIState; 811*b843c749SSergey Zigachev NISLANDS_SMC_SWSTATE ULVState; 812*b843c749SSergey Zigachev NISLANDS_SMC_SWSTATE driverState; 813*b843c749SSergey Zigachev NISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1]; 814*b843c749SSergey Zigachev }; 815*b843c749SSergey Zigachev 816*b843c749SSergey Zigachev typedef struct NISLANDS_SMC_STATETABLE NISLANDS_SMC_STATETABLE; 817*b843c749SSergey Zigachev 818*b843c749SSergey Zigachev struct ni_power_info { 819*b843c749SSergey Zigachev /* must be first! */ 820*b843c749SSergey Zigachev struct evergreen_power_info eg; 821*b843c749SSergey Zigachev struct ni_clock_registers clock_registers; 822*b843c749SSergey Zigachev struct ni_mc_reg_table mc_reg_table; 823*b843c749SSergey Zigachev u32 mclk_rtt_mode_threshold; 824*b843c749SSergey Zigachev /* flags */ 825*b843c749SSergey Zigachev bool use_power_boost_limit; 826*b843c749SSergey Zigachev bool support_cac_long_term_average; 827*b843c749SSergey Zigachev bool cac_enabled; 828*b843c749SSergey Zigachev bool cac_configuration_required; 829*b843c749SSergey Zigachev bool driver_calculate_cac_leakage; 830*b843c749SSergey Zigachev bool pc_enabled; 831*b843c749SSergey Zigachev bool enable_power_containment; 832*b843c749SSergey Zigachev bool enable_cac; 833*b843c749SSergey Zigachev bool enable_sq_ramping; 834*b843c749SSergey Zigachev /* smc offsets */ 835*b843c749SSergey Zigachev u16 arb_table_start; 836*b843c749SSergey Zigachev u16 fan_table_start; 837*b843c749SSergey Zigachev u16 cac_table_start; 838*b843c749SSergey Zigachev u16 spll_table_start; 839*b843c749SSergey Zigachev /* CAC stuff */ 840*b843c749SSergey Zigachev struct ni_cac_data cac_data; 841*b843c749SSergey Zigachev u32 dc_cac_table[NISLANDS_DCCAC_MAX_LEVELS]; 842*b843c749SSergey Zigachev const struct ni_cac_weights *cac_weights; 843*b843c749SSergey Zigachev u8 lta_window_size; 844*b843c749SSergey Zigachev u8 lts_truncate; 845*b843c749SSergey Zigachev struct si_ps current_ps; 846*b843c749SSergey Zigachev struct si_ps requested_ps; 847*b843c749SSergey Zigachev /* scratch structs */ 848*b843c749SSergey Zigachev SMC_NIslands_MCRegisters smc_mc_reg_table; 849*b843c749SSergey Zigachev NISLANDS_SMC_STATETABLE smc_statetable; 850*b843c749SSergey Zigachev }; 851*b843c749SSergey Zigachev 852*b843c749SSergey Zigachev struct si_cac_config_reg 853*b843c749SSergey Zigachev { 854*b843c749SSergey Zigachev u32 offset; 855*b843c749SSergey Zigachev u32 mask; 856*b843c749SSergey Zigachev u32 shift; 857*b843c749SSergey Zigachev u32 value; 858*b843c749SSergey Zigachev enum si_cac_config_reg_type type; 859*b843c749SSergey Zigachev }; 860*b843c749SSergey Zigachev 861*b843c749SSergey Zigachev struct si_powertune_data 862*b843c749SSergey Zigachev { 863*b843c749SSergey Zigachev u32 cac_window; 864*b843c749SSergey Zigachev u32 l2_lta_window_size_default; 865*b843c749SSergey Zigachev u8 lts_truncate_default; 866*b843c749SSergey Zigachev u8 shift_n_default; 867*b843c749SSergey Zigachev u8 operating_temp; 868*b843c749SSergey Zigachev struct ni_leakage_coeffients leakage_coefficients; 869*b843c749SSergey Zigachev u32 fixed_kt; 870*b843c749SSergey Zigachev u32 lkge_lut_v0_percent; 871*b843c749SSergey Zigachev u8 dc_cac[NISLANDS_DCCAC_MAX_LEVELS]; 872*b843c749SSergey Zigachev bool enable_powertune_by_default; 873*b843c749SSergey Zigachev }; 874*b843c749SSergey Zigachev 875*b843c749SSergey Zigachev struct si_dyn_powertune_data 876*b843c749SSergey Zigachev { 877*b843c749SSergey Zigachev u32 cac_leakage; 878*b843c749SSergey Zigachev s32 leakage_minimum_temperature; 879*b843c749SSergey Zigachev u32 wintime; 880*b843c749SSergey Zigachev u32 l2_lta_window_size; 881*b843c749SSergey Zigachev u8 lts_truncate; 882*b843c749SSergey Zigachev u8 shift_n; 883*b843c749SSergey Zigachev u8 dc_pwr_value; 884*b843c749SSergey Zigachev bool disable_uvd_powertune; 885*b843c749SSergey Zigachev }; 886*b843c749SSergey Zigachev 887*b843c749SSergey Zigachev struct si_dte_data 888*b843c749SSergey Zigachev { 889*b843c749SSergey Zigachev u32 tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; 890*b843c749SSergey Zigachev u32 r[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; 891*b843c749SSergey Zigachev u32 k; 892*b843c749SSergey Zigachev u32 t0; 893*b843c749SSergey Zigachev u32 max_t; 894*b843c749SSergey Zigachev u8 window_size; 895*b843c749SSergey Zigachev u8 temp_select; 896*b843c749SSergey Zigachev u8 dte_mode; 897*b843c749SSergey Zigachev u8 tdep_count; 898*b843c749SSergey Zigachev u8 t_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; 899*b843c749SSergey Zigachev u32 tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; 900*b843c749SSergey Zigachev u32 tdep_r[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; 901*b843c749SSergey Zigachev u32 t_threshold; 902*b843c749SSergey Zigachev bool enable_dte_by_default; 903*b843c749SSergey Zigachev }; 904*b843c749SSergey Zigachev 905*b843c749SSergey Zigachev struct si_clock_registers { 906*b843c749SSergey Zigachev u32 cg_spll_func_cntl; 907*b843c749SSergey Zigachev u32 cg_spll_func_cntl_2; 908*b843c749SSergey Zigachev u32 cg_spll_func_cntl_3; 909*b843c749SSergey Zigachev u32 cg_spll_func_cntl_4; 910*b843c749SSergey Zigachev u32 cg_spll_spread_spectrum; 911*b843c749SSergey Zigachev u32 cg_spll_spread_spectrum_2; 912*b843c749SSergey Zigachev u32 dll_cntl; 913*b843c749SSergey Zigachev u32 mclk_pwrmgt_cntl; 914*b843c749SSergey Zigachev u32 mpll_ad_func_cntl; 915*b843c749SSergey Zigachev u32 mpll_dq_func_cntl; 916*b843c749SSergey Zigachev u32 mpll_func_cntl; 917*b843c749SSergey Zigachev u32 mpll_func_cntl_1; 918*b843c749SSergey Zigachev u32 mpll_func_cntl_2; 919*b843c749SSergey Zigachev u32 mpll_ss1; 920*b843c749SSergey Zigachev u32 mpll_ss2; 921*b843c749SSergey Zigachev }; 922*b843c749SSergey Zigachev 923*b843c749SSergey Zigachev struct si_mc_reg_entry { 924*b843c749SSergey Zigachev u32 mclk_max; 925*b843c749SSergey Zigachev u32 mc_data[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; 926*b843c749SSergey Zigachev }; 927*b843c749SSergey Zigachev 928*b843c749SSergey Zigachev struct si_mc_reg_table { 929*b843c749SSergey Zigachev u8 last; 930*b843c749SSergey Zigachev u8 num_entries; 931*b843c749SSergey Zigachev u16 valid_flag; 932*b843c749SSergey Zigachev struct si_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; 933*b843c749SSergey Zigachev SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; 934*b843c749SSergey Zigachev }; 935*b843c749SSergey Zigachev 936*b843c749SSergey Zigachev struct si_leakage_voltage_entry 937*b843c749SSergey Zigachev { 938*b843c749SSergey Zigachev u16 voltage; 939*b843c749SSergey Zigachev u16 leakage_index; 940*b843c749SSergey Zigachev }; 941*b843c749SSergey Zigachev 942*b843c749SSergey Zigachev struct si_leakage_voltage 943*b843c749SSergey Zigachev { 944*b843c749SSergey Zigachev u16 count; 945*b843c749SSergey Zigachev struct si_leakage_voltage_entry entries[SISLANDS_MAX_LEAKAGE_COUNT]; 946*b843c749SSergey Zigachev }; 947*b843c749SSergey Zigachev 948*b843c749SSergey Zigachev 949*b843c749SSergey Zigachev struct si_ulv_param { 950*b843c749SSergey Zigachev bool supported; 951*b843c749SSergey Zigachev u32 cg_ulv_control; 952*b843c749SSergey Zigachev u32 cg_ulv_parameter; 953*b843c749SSergey Zigachev u32 volt_change_delay; 954*b843c749SSergey Zigachev struct rv7xx_pl pl; 955*b843c749SSergey Zigachev bool one_pcie_lane_in_ulv; 956*b843c749SSergey Zigachev }; 957*b843c749SSergey Zigachev 958*b843c749SSergey Zigachev struct si_power_info { 959*b843c749SSergey Zigachev /* must be first! */ 960*b843c749SSergey Zigachev struct ni_power_info ni; 961*b843c749SSergey Zigachev struct si_clock_registers clock_registers; 962*b843c749SSergey Zigachev struct si_mc_reg_table mc_reg_table; 963*b843c749SSergey Zigachev struct atom_voltage_table mvdd_voltage_table; 964*b843c749SSergey Zigachev struct atom_voltage_table vddc_phase_shed_table; 965*b843c749SSergey Zigachev struct si_leakage_voltage leakage_voltage; 966*b843c749SSergey Zigachev u16 mvdd_bootup_value; 967*b843c749SSergey Zigachev struct si_ulv_param ulv; 968*b843c749SSergey Zigachev u32 max_cu; 969*b843c749SSergey Zigachev /* pcie gen */ 970*b843c749SSergey Zigachev enum amdgpu_pcie_gen force_pcie_gen; 971*b843c749SSergey Zigachev enum amdgpu_pcie_gen boot_pcie_gen; 972*b843c749SSergey Zigachev enum amdgpu_pcie_gen acpi_pcie_gen; 973*b843c749SSergey Zigachev u32 sys_pcie_mask; 974*b843c749SSergey Zigachev /* flags */ 975*b843c749SSergey Zigachev bool enable_dte; 976*b843c749SSergey Zigachev bool enable_ppm; 977*b843c749SSergey Zigachev bool vddc_phase_shed_control; 978*b843c749SSergey Zigachev bool pspp_notify_required; 979*b843c749SSergey Zigachev bool sclk_deep_sleep_above_low; 980*b843c749SSergey Zigachev bool voltage_control_svi2; 981*b843c749SSergey Zigachev bool vddci_control_svi2; 982*b843c749SSergey Zigachev /* smc offsets */ 983*b843c749SSergey Zigachev u32 sram_end; 984*b843c749SSergey Zigachev u32 state_table_start; 985*b843c749SSergey Zigachev u32 soft_regs_start; 986*b843c749SSergey Zigachev u32 mc_reg_table_start; 987*b843c749SSergey Zigachev u32 arb_table_start; 988*b843c749SSergey Zigachev u32 cac_table_start; 989*b843c749SSergey Zigachev u32 dte_table_start; 990*b843c749SSergey Zigachev u32 spll_table_start; 991*b843c749SSergey Zigachev u32 papm_cfg_table_start; 992*b843c749SSergey Zigachev u32 fan_table_start; 993*b843c749SSergey Zigachev /* CAC stuff */ 994*b843c749SSergey Zigachev const struct si_cac_config_reg *cac_weights; 995*b843c749SSergey Zigachev const struct si_cac_config_reg *lcac_config; 996*b843c749SSergey Zigachev const struct si_cac_config_reg *cac_override; 997*b843c749SSergey Zigachev const struct si_powertune_data *powertune_data; 998*b843c749SSergey Zigachev struct si_dyn_powertune_data dyn_powertune_data; 999*b843c749SSergey Zigachev /* DTE stuff */ 1000*b843c749SSergey Zigachev struct si_dte_data dte_data; 1001*b843c749SSergey Zigachev /* scratch structs */ 1002*b843c749SSergey Zigachev SMC_SIslands_MCRegisters smc_mc_reg_table; 1003*b843c749SSergey Zigachev SISLANDS_SMC_STATETABLE smc_statetable; 1004*b843c749SSergey Zigachev PP_SIslands_PAPMParameters papm_parm; 1005*b843c749SSergey Zigachev /* SVI2 */ 1006*b843c749SSergey Zigachev u8 svd_gpio_id; 1007*b843c749SSergey Zigachev u8 svc_gpio_id; 1008*b843c749SSergey Zigachev /* fan control */ 1009*b843c749SSergey Zigachev bool fan_ctrl_is_in_default_mode; 1010*b843c749SSergey Zigachev u32 t_min; 1011*b843c749SSergey Zigachev u32 fan_ctrl_default_mode; 1012*b843c749SSergey Zigachev bool fan_is_controlled_by_smc; 1013*b843c749SSergey Zigachev }; 1014*b843c749SSergey Zigachev 1015*b843c749SSergey Zigachev #endif 1016