1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2013 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev */ 23*b843c749SSergey Zigachev #ifndef PP_SISLANDS_SMC_H 24*b843c749SSergey Zigachev #define PP_SISLANDS_SMC_H 25*b843c749SSergey Zigachev 26*b843c749SSergey Zigachev #include "ppsmc.h" 27*b843c749SSergey Zigachev 28*b843c749SSergey Zigachev #pragma pack(push, 1) 29*b843c749SSergey Zigachev 30*b843c749SSergey Zigachev #define SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16 31*b843c749SSergey Zigachev 32*b843c749SSergey Zigachev struct PP_SIslands_Dpm2PerfLevel 33*b843c749SSergey Zigachev { 34*b843c749SSergey Zigachev uint8_t MaxPS; 35*b843c749SSergey Zigachev uint8_t TgtAct; 36*b843c749SSergey Zigachev uint8_t MaxPS_StepInc; 37*b843c749SSergey Zigachev uint8_t MaxPS_StepDec; 38*b843c749SSergey Zigachev uint8_t PSSamplingTime; 39*b843c749SSergey Zigachev uint8_t NearTDPDec; 40*b843c749SSergey Zigachev uint8_t AboveSafeInc; 41*b843c749SSergey Zigachev uint8_t BelowSafeInc; 42*b843c749SSergey Zigachev uint8_t PSDeltaLimit; 43*b843c749SSergey Zigachev uint8_t PSDeltaWin; 44*b843c749SSergey Zigachev uint16_t PwrEfficiencyRatio; 45*b843c749SSergey Zigachev uint8_t Reserved[4]; 46*b843c749SSergey Zigachev }; 47*b843c749SSergey Zigachev 48*b843c749SSergey Zigachev typedef struct PP_SIslands_Dpm2PerfLevel PP_SIslands_Dpm2PerfLevel; 49*b843c749SSergey Zigachev 50*b843c749SSergey Zigachev struct PP_SIslands_DPM2Status 51*b843c749SSergey Zigachev { 52*b843c749SSergey Zigachev uint32_t dpm2Flags; 53*b843c749SSergey Zigachev uint8_t CurrPSkip; 54*b843c749SSergey Zigachev uint8_t CurrPSkipPowerShift; 55*b843c749SSergey Zigachev uint8_t CurrPSkipTDP; 56*b843c749SSergey Zigachev uint8_t CurrPSkipOCP; 57*b843c749SSergey Zigachev uint8_t MaxSPLLIndex; 58*b843c749SSergey Zigachev uint8_t MinSPLLIndex; 59*b843c749SSergey Zigachev uint8_t CurrSPLLIndex; 60*b843c749SSergey Zigachev uint8_t InfSweepMode; 61*b843c749SSergey Zigachev uint8_t InfSweepDir; 62*b843c749SSergey Zigachev uint8_t TDPexceeded; 63*b843c749SSergey Zigachev uint8_t reserved; 64*b843c749SSergey Zigachev uint8_t SwitchDownThreshold; 65*b843c749SSergey Zigachev uint32_t SwitchDownCounter; 66*b843c749SSergey Zigachev uint32_t SysScalingFactor; 67*b843c749SSergey Zigachev }; 68*b843c749SSergey Zigachev 69*b843c749SSergey Zigachev typedef struct PP_SIslands_DPM2Status PP_SIslands_DPM2Status; 70*b843c749SSergey Zigachev 71*b843c749SSergey Zigachev struct PP_SIslands_DPM2Parameters 72*b843c749SSergey Zigachev { 73*b843c749SSergey Zigachev uint32_t TDPLimit; 74*b843c749SSergey Zigachev uint32_t NearTDPLimit; 75*b843c749SSergey Zigachev uint32_t SafePowerLimit; 76*b843c749SSergey Zigachev uint32_t PowerBoostLimit; 77*b843c749SSergey Zigachev uint32_t MinLimitDelta; 78*b843c749SSergey Zigachev }; 79*b843c749SSergey Zigachev typedef struct PP_SIslands_DPM2Parameters PP_SIslands_DPM2Parameters; 80*b843c749SSergey Zigachev 81*b843c749SSergey Zigachev struct PP_SIslands_PAPMStatus 82*b843c749SSergey Zigachev { 83*b843c749SSergey Zigachev uint32_t EstimatedDGPU_T; 84*b843c749SSergey Zigachev uint32_t EstimatedDGPU_P; 85*b843c749SSergey Zigachev uint32_t EstimatedAPU_T; 86*b843c749SSergey Zigachev uint32_t EstimatedAPU_P; 87*b843c749SSergey Zigachev uint8_t dGPU_T_Limit_Exceeded; 88*b843c749SSergey Zigachev uint8_t reserved[3]; 89*b843c749SSergey Zigachev }; 90*b843c749SSergey Zigachev typedef struct PP_SIslands_PAPMStatus PP_SIslands_PAPMStatus; 91*b843c749SSergey Zigachev 92*b843c749SSergey Zigachev struct PP_SIslands_PAPMParameters 93*b843c749SSergey Zigachev { 94*b843c749SSergey Zigachev uint32_t NearTDPLimitTherm; 95*b843c749SSergey Zigachev uint32_t NearTDPLimitPAPM; 96*b843c749SSergey Zigachev uint32_t PlatformPowerLimit; 97*b843c749SSergey Zigachev uint32_t dGPU_T_Limit; 98*b843c749SSergey Zigachev uint32_t dGPU_T_Warning; 99*b843c749SSergey Zigachev uint32_t dGPU_T_Hysteresis; 100*b843c749SSergey Zigachev }; 101*b843c749SSergey Zigachev typedef struct PP_SIslands_PAPMParameters PP_SIslands_PAPMParameters; 102*b843c749SSergey Zigachev 103*b843c749SSergey Zigachev struct SISLANDS_SMC_SCLK_VALUE 104*b843c749SSergey Zigachev { 105*b843c749SSergey Zigachev uint32_t vCG_SPLL_FUNC_CNTL; 106*b843c749SSergey Zigachev uint32_t vCG_SPLL_FUNC_CNTL_2; 107*b843c749SSergey Zigachev uint32_t vCG_SPLL_FUNC_CNTL_3; 108*b843c749SSergey Zigachev uint32_t vCG_SPLL_FUNC_CNTL_4; 109*b843c749SSergey Zigachev uint32_t vCG_SPLL_SPREAD_SPECTRUM; 110*b843c749SSergey Zigachev uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; 111*b843c749SSergey Zigachev uint32_t sclk_value; 112*b843c749SSergey Zigachev }; 113*b843c749SSergey Zigachev 114*b843c749SSergey Zigachev typedef struct SISLANDS_SMC_SCLK_VALUE SISLANDS_SMC_SCLK_VALUE; 115*b843c749SSergey Zigachev 116*b843c749SSergey Zigachev struct SISLANDS_SMC_MCLK_VALUE 117*b843c749SSergey Zigachev { 118*b843c749SSergey Zigachev uint32_t vMPLL_FUNC_CNTL; 119*b843c749SSergey Zigachev uint32_t vMPLL_FUNC_CNTL_1; 120*b843c749SSergey Zigachev uint32_t vMPLL_FUNC_CNTL_2; 121*b843c749SSergey Zigachev uint32_t vMPLL_AD_FUNC_CNTL; 122*b843c749SSergey Zigachev uint32_t vMPLL_DQ_FUNC_CNTL; 123*b843c749SSergey Zigachev uint32_t vMCLK_PWRMGT_CNTL; 124*b843c749SSergey Zigachev uint32_t vDLL_CNTL; 125*b843c749SSergey Zigachev uint32_t vMPLL_SS; 126*b843c749SSergey Zigachev uint32_t vMPLL_SS2; 127*b843c749SSergey Zigachev uint32_t mclk_value; 128*b843c749SSergey Zigachev }; 129*b843c749SSergey Zigachev 130*b843c749SSergey Zigachev typedef struct SISLANDS_SMC_MCLK_VALUE SISLANDS_SMC_MCLK_VALUE; 131*b843c749SSergey Zigachev 132*b843c749SSergey Zigachev struct SISLANDS_SMC_VOLTAGE_VALUE 133*b843c749SSergey Zigachev { 134*b843c749SSergey Zigachev uint16_t value; 135*b843c749SSergey Zigachev uint8_t index; 136*b843c749SSergey Zigachev uint8_t phase_settings; 137*b843c749SSergey Zigachev }; 138*b843c749SSergey Zigachev 139*b843c749SSergey Zigachev typedef struct SISLANDS_SMC_VOLTAGE_VALUE SISLANDS_SMC_VOLTAGE_VALUE; 140*b843c749SSergey Zigachev 141*b843c749SSergey Zigachev struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL 142*b843c749SSergey Zigachev { 143*b843c749SSergey Zigachev uint8_t ACIndex; 144*b843c749SSergey Zigachev uint8_t displayWatermark; 145*b843c749SSergey Zigachev uint8_t gen2PCIE; 146*b843c749SSergey Zigachev uint8_t UVDWatermark; 147*b843c749SSergey Zigachev uint8_t VCEWatermark; 148*b843c749SSergey Zigachev uint8_t strobeMode; 149*b843c749SSergey Zigachev uint8_t mcFlags; 150*b843c749SSergey Zigachev uint8_t padding; 151*b843c749SSergey Zigachev uint32_t aT; 152*b843c749SSergey Zigachev uint32_t bSP; 153*b843c749SSergey Zigachev SISLANDS_SMC_SCLK_VALUE sclk; 154*b843c749SSergey Zigachev SISLANDS_SMC_MCLK_VALUE mclk; 155*b843c749SSergey Zigachev SISLANDS_SMC_VOLTAGE_VALUE vddc; 156*b843c749SSergey Zigachev SISLANDS_SMC_VOLTAGE_VALUE mvdd; 157*b843c749SSergey Zigachev SISLANDS_SMC_VOLTAGE_VALUE vddci; 158*b843c749SSergey Zigachev SISLANDS_SMC_VOLTAGE_VALUE std_vddc; 159*b843c749SSergey Zigachev uint8_t hysteresisUp; 160*b843c749SSergey Zigachev uint8_t hysteresisDown; 161*b843c749SSergey Zigachev uint8_t stateFlags; 162*b843c749SSergey Zigachev uint8_t arbRefreshState; 163*b843c749SSergey Zigachev uint32_t SQPowerThrottle; 164*b843c749SSergey Zigachev uint32_t SQPowerThrottle_2; 165*b843c749SSergey Zigachev uint32_t MaxPoweredUpCU; 166*b843c749SSergey Zigachev SISLANDS_SMC_VOLTAGE_VALUE high_temp_vddc; 167*b843c749SSergey Zigachev SISLANDS_SMC_VOLTAGE_VALUE low_temp_vddc; 168*b843c749SSergey Zigachev uint32_t reserved[2]; 169*b843c749SSergey Zigachev PP_SIslands_Dpm2PerfLevel dpm2; 170*b843c749SSergey Zigachev }; 171*b843c749SSergey Zigachev 172*b843c749SSergey Zigachev #define SISLANDS_SMC_STROBE_RATIO 0x0F 173*b843c749SSergey Zigachev #define SISLANDS_SMC_STROBE_ENABLE 0x10 174*b843c749SSergey Zigachev 175*b843c749SSergey Zigachev #define SISLANDS_SMC_MC_EDC_RD_FLAG 0x01 176*b843c749SSergey Zigachev #define SISLANDS_SMC_MC_EDC_WR_FLAG 0x02 177*b843c749SSergey Zigachev #define SISLANDS_SMC_MC_RTT_ENABLE 0x04 178*b843c749SSergey Zigachev #define SISLANDS_SMC_MC_STUTTER_EN 0x08 179*b843c749SSergey Zigachev #define SISLANDS_SMC_MC_PG_EN 0x10 180*b843c749SSergey Zigachev 181*b843c749SSergey Zigachev typedef struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL SISLANDS_SMC_HW_PERFORMANCE_LEVEL; 182*b843c749SSergey Zigachev 183*b843c749SSergey Zigachev struct SISLANDS_SMC_SWSTATE 184*b843c749SSergey Zigachev { 185*b843c749SSergey Zigachev uint8_t flags; 186*b843c749SSergey Zigachev uint8_t levelCount; 187*b843c749SSergey Zigachev uint8_t padding2; 188*b843c749SSergey Zigachev uint8_t padding3; 189*b843c749SSergey Zigachev SISLANDS_SMC_HW_PERFORMANCE_LEVEL levels[1]; 190*b843c749SSergey Zigachev }; 191*b843c749SSergey Zigachev 192*b843c749SSergey Zigachev typedef struct SISLANDS_SMC_SWSTATE SISLANDS_SMC_SWSTATE; 193*b843c749SSergey Zigachev 194*b843c749SSergey Zigachev #define SISLANDS_SMC_VOLTAGEMASK_VDDC 0 195*b843c749SSergey Zigachev #define SISLANDS_SMC_VOLTAGEMASK_MVDD 1 196*b843c749SSergey Zigachev #define SISLANDS_SMC_VOLTAGEMASK_VDDCI 2 197*b843c749SSergey Zigachev #define SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING 3 198*b843c749SSergey Zigachev #define SISLANDS_SMC_VOLTAGEMASK_MAX 4 199*b843c749SSergey Zigachev 200*b843c749SSergey Zigachev struct SISLANDS_SMC_VOLTAGEMASKTABLE 201*b843c749SSergey Zigachev { 202*b843c749SSergey Zigachev uint32_t lowMask[SISLANDS_SMC_VOLTAGEMASK_MAX]; 203*b843c749SSergey Zigachev }; 204*b843c749SSergey Zigachev 205*b843c749SSergey Zigachev typedef struct SISLANDS_SMC_VOLTAGEMASKTABLE SISLANDS_SMC_VOLTAGEMASKTABLE; 206*b843c749SSergey Zigachev 207*b843c749SSergey Zigachev #define SISLANDS_MAX_NO_VREG_STEPS 32 208*b843c749SSergey Zigachev 209*b843c749SSergey Zigachev struct SISLANDS_SMC_STATETABLE 210*b843c749SSergey Zigachev { 211*b843c749SSergey Zigachev uint8_t thermalProtectType; 212*b843c749SSergey Zigachev uint8_t systemFlags; 213*b843c749SSergey Zigachev uint8_t maxVDDCIndexInPPTable; 214*b843c749SSergey Zigachev uint8_t extraFlags; 215*b843c749SSergey Zigachev uint32_t lowSMIO[SISLANDS_MAX_NO_VREG_STEPS]; 216*b843c749SSergey Zigachev SISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable; 217*b843c749SSergey Zigachev SISLANDS_SMC_VOLTAGEMASKTABLE phaseMaskTable; 218*b843c749SSergey Zigachev PP_SIslands_DPM2Parameters dpm2Params; 219*b843c749SSergey Zigachev SISLANDS_SMC_SWSTATE initialState; 220*b843c749SSergey Zigachev SISLANDS_SMC_SWSTATE ACPIState; 221*b843c749SSergey Zigachev SISLANDS_SMC_SWSTATE ULVState; 222*b843c749SSergey Zigachev SISLANDS_SMC_SWSTATE driverState; 223*b843c749SSergey Zigachev SISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1]; 224*b843c749SSergey Zigachev }; 225*b843c749SSergey Zigachev 226*b843c749SSergey Zigachev typedef struct SISLANDS_SMC_STATETABLE SISLANDS_SMC_STATETABLE; 227*b843c749SSergey Zigachev 228*b843c749SSergey Zigachev #define SI_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0 229*b843c749SSergey Zigachev #define SI_SMC_SOFT_REGISTER_delay_vreg 0xC 230*b843c749SSergey Zigachev #define SI_SMC_SOFT_REGISTER_delay_acpi 0x28 231*b843c749SSergey Zigachev #define SI_SMC_SOFT_REGISTER_seq_index 0x5C 232*b843c749SSergey Zigachev #define SI_SMC_SOFT_REGISTER_mvdd_chg_time 0x60 233*b843c749SSergey Zigachev #define SI_SMC_SOFT_REGISTER_mclk_switch_lim 0x70 234*b843c749SSergey Zigachev #define SI_SMC_SOFT_REGISTER_watermark_threshold 0x78 235*b843c749SSergey Zigachev #define SI_SMC_SOFT_REGISTER_phase_shedding_delay 0x88 236*b843c749SSergey Zigachev #define SI_SMC_SOFT_REGISTER_ulv_volt_change_delay 0x8C 237*b843c749SSergey Zigachev #define SI_SMC_SOFT_REGISTER_mc_block_delay 0x98 238*b843c749SSergey Zigachev #define SI_SMC_SOFT_REGISTER_ticks_per_us 0xA8 239*b843c749SSergey Zigachev #define SI_SMC_SOFT_REGISTER_crtc_index 0xC4 240*b843c749SSergey Zigachev #define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min 0xC8 241*b843c749SSergey Zigachev #define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max 0xCC 242*b843c749SSergey Zigachev #define SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width 0xF4 243*b843c749SSergey Zigachev #define SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen 0xFC 244*b843c749SSergey Zigachev #define SI_SMC_SOFT_REGISTER_vr_hot_gpio 0x100 245*b843c749SSergey Zigachev #define SI_SMC_SOFT_REGISTER_svi_rework_plat_type 0x118 246*b843c749SSergey Zigachev #define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd 0x11c 247*b843c749SSergey Zigachev #define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc 0x120 248*b843c749SSergey Zigachev 249*b843c749SSergey Zigachev struct PP_SIslands_FanTable 250*b843c749SSergey Zigachev { 251*b843c749SSergey Zigachev uint8_t fdo_mode; 252*b843c749SSergey Zigachev uint8_t padding; 253*b843c749SSergey Zigachev int16_t temp_min; 254*b843c749SSergey Zigachev int16_t temp_med; 255*b843c749SSergey Zigachev int16_t temp_max; 256*b843c749SSergey Zigachev int16_t slope1; 257*b843c749SSergey Zigachev int16_t slope2; 258*b843c749SSergey Zigachev int16_t fdo_min; 259*b843c749SSergey Zigachev int16_t hys_up; 260*b843c749SSergey Zigachev int16_t hys_down; 261*b843c749SSergey Zigachev int16_t hys_slope; 262*b843c749SSergey Zigachev int16_t temp_resp_lim; 263*b843c749SSergey Zigachev int16_t temp_curr; 264*b843c749SSergey Zigachev int16_t slope_curr; 265*b843c749SSergey Zigachev int16_t pwm_curr; 266*b843c749SSergey Zigachev uint32_t refresh_period; 267*b843c749SSergey Zigachev int16_t fdo_max; 268*b843c749SSergey Zigachev uint8_t temp_src; 269*b843c749SSergey Zigachev int8_t padding2; 270*b843c749SSergey Zigachev }; 271*b843c749SSergey Zigachev 272*b843c749SSergey Zigachev typedef struct PP_SIslands_FanTable PP_SIslands_FanTable; 273*b843c749SSergey Zigachev 274*b843c749SSergey Zigachev #define SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16 275*b843c749SSergey Zigachev #define SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES 32 276*b843c749SSergey Zigachev 277*b843c749SSergey Zigachev #define SMC_SISLANDS_SCALE_I 7 278*b843c749SSergey Zigachev #define SMC_SISLANDS_SCALE_R 12 279*b843c749SSergey Zigachev 280*b843c749SSergey Zigachev struct PP_SIslands_CacConfig 281*b843c749SSergey Zigachev { 282*b843c749SSergey Zigachev uint16_t cac_lkge_lut[SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES]; 283*b843c749SSergey Zigachev uint32_t lkge_lut_V0; 284*b843c749SSergey Zigachev uint32_t lkge_lut_Vstep; 285*b843c749SSergey Zigachev uint32_t WinTime; 286*b843c749SSergey Zigachev uint32_t R_LL; 287*b843c749SSergey Zigachev uint32_t calculation_repeats; 288*b843c749SSergey Zigachev uint32_t l2numWin_TDP; 289*b843c749SSergey Zigachev uint32_t dc_cac; 290*b843c749SSergey Zigachev uint8_t lts_truncate_n; 291*b843c749SSergey Zigachev uint8_t SHIFT_N; 292*b843c749SSergey Zigachev uint8_t log2_PG_LKG_SCALE; 293*b843c749SSergey Zigachev uint8_t cac_temp; 294*b843c749SSergey Zigachev uint32_t lkge_lut_T0; 295*b843c749SSergey Zigachev uint32_t lkge_lut_Tstep; 296*b843c749SSergey Zigachev }; 297*b843c749SSergey Zigachev 298*b843c749SSergey Zigachev typedef struct PP_SIslands_CacConfig PP_SIslands_CacConfig; 299*b843c749SSergey Zigachev 300*b843c749SSergey Zigachev #define SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE 16 301*b843c749SSergey Zigachev #define SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20 302*b843c749SSergey Zigachev 303*b843c749SSergey Zigachev struct SMC_SIslands_MCRegisterAddress 304*b843c749SSergey Zigachev { 305*b843c749SSergey Zigachev uint16_t s0; 306*b843c749SSergey Zigachev uint16_t s1; 307*b843c749SSergey Zigachev }; 308*b843c749SSergey Zigachev 309*b843c749SSergey Zigachev typedef struct SMC_SIslands_MCRegisterAddress SMC_SIslands_MCRegisterAddress; 310*b843c749SSergey Zigachev 311*b843c749SSergey Zigachev struct SMC_SIslands_MCRegisterSet 312*b843c749SSergey Zigachev { 313*b843c749SSergey Zigachev uint32_t value[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; 314*b843c749SSergey Zigachev }; 315*b843c749SSergey Zigachev 316*b843c749SSergey Zigachev typedef struct SMC_SIslands_MCRegisterSet SMC_SIslands_MCRegisterSet; 317*b843c749SSergey Zigachev 318*b843c749SSergey Zigachev struct SMC_SIslands_MCRegisters 319*b843c749SSergey Zigachev { 320*b843c749SSergey Zigachev uint8_t last; 321*b843c749SSergey Zigachev uint8_t reserved[3]; 322*b843c749SSergey Zigachev SMC_SIslands_MCRegisterAddress address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; 323*b843c749SSergey Zigachev SMC_SIslands_MCRegisterSet data[SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT]; 324*b843c749SSergey Zigachev }; 325*b843c749SSergey Zigachev 326*b843c749SSergey Zigachev typedef struct SMC_SIslands_MCRegisters SMC_SIslands_MCRegisters; 327*b843c749SSergey Zigachev 328*b843c749SSergey Zigachev struct SMC_SIslands_MCArbDramTimingRegisterSet 329*b843c749SSergey Zigachev { 330*b843c749SSergey Zigachev uint32_t mc_arb_dram_timing; 331*b843c749SSergey Zigachev uint32_t mc_arb_dram_timing2; 332*b843c749SSergey Zigachev uint8_t mc_arb_rfsh_rate; 333*b843c749SSergey Zigachev uint8_t mc_arb_burst_time; 334*b843c749SSergey Zigachev uint8_t padding[2]; 335*b843c749SSergey Zigachev }; 336*b843c749SSergey Zigachev 337*b843c749SSergey Zigachev typedef struct SMC_SIslands_MCArbDramTimingRegisterSet SMC_SIslands_MCArbDramTimingRegisterSet; 338*b843c749SSergey Zigachev 339*b843c749SSergey Zigachev struct SMC_SIslands_MCArbDramTimingRegisters 340*b843c749SSergey Zigachev { 341*b843c749SSergey Zigachev uint8_t arb_current; 342*b843c749SSergey Zigachev uint8_t reserved[3]; 343*b843c749SSergey Zigachev SMC_SIslands_MCArbDramTimingRegisterSet data[16]; 344*b843c749SSergey Zigachev }; 345*b843c749SSergey Zigachev 346*b843c749SSergey Zigachev typedef struct SMC_SIslands_MCArbDramTimingRegisters SMC_SIslands_MCArbDramTimingRegisters; 347*b843c749SSergey Zigachev 348*b843c749SSergey Zigachev struct SMC_SISLANDS_SPLL_DIV_TABLE 349*b843c749SSergey Zigachev { 350*b843c749SSergey Zigachev uint32_t freq[256]; 351*b843c749SSergey Zigachev uint32_t ss[256]; 352*b843c749SSergey Zigachev }; 353*b843c749SSergey Zigachev 354*b843c749SSergey Zigachev #define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK 0x01ffffff 355*b843c749SSergey Zigachev #define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT 0 356*b843c749SSergey Zigachev #define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK 0xfe000000 357*b843c749SSergey Zigachev #define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT 25 358*b843c749SSergey Zigachev #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK 0x000fffff 359*b843c749SSergey Zigachev #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT 0 360*b843c749SSergey Zigachev #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK 0xfff00000 361*b843c749SSergey Zigachev #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT 20 362*b843c749SSergey Zigachev 363*b843c749SSergey Zigachev typedef struct SMC_SISLANDS_SPLL_DIV_TABLE SMC_SISLANDS_SPLL_DIV_TABLE; 364*b843c749SSergey Zigachev 365*b843c749SSergey Zigachev #define SMC_SISLANDS_DTE_MAX_FILTER_STAGES 5 366*b843c749SSergey Zigachev 367*b843c749SSergey Zigachev #define SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE 16 368*b843c749SSergey Zigachev 369*b843c749SSergey Zigachev struct Smc_SIslands_DTE_Configuration 370*b843c749SSergey Zigachev { 371*b843c749SSergey Zigachev uint32_t tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; 372*b843c749SSergey Zigachev uint32_t R[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; 373*b843c749SSergey Zigachev uint32_t K; 374*b843c749SSergey Zigachev uint32_t T0; 375*b843c749SSergey Zigachev uint32_t MaxT; 376*b843c749SSergey Zigachev uint8_t WindowSize; 377*b843c749SSergey Zigachev uint8_t Tdep_count; 378*b843c749SSergey Zigachev uint8_t temp_select; 379*b843c749SSergey Zigachev uint8_t DTE_mode; 380*b843c749SSergey Zigachev uint8_t T_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; 381*b843c749SSergey Zigachev uint32_t Tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; 382*b843c749SSergey Zigachev uint32_t Tdep_R[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; 383*b843c749SSergey Zigachev uint32_t Tthreshold; 384*b843c749SSergey Zigachev }; 385*b843c749SSergey Zigachev 386*b843c749SSergey Zigachev typedef struct Smc_SIslands_DTE_Configuration Smc_SIslands_DTE_Configuration; 387*b843c749SSergey Zigachev 388*b843c749SSergey Zigachev #define SMC_SISLANDS_DTE_STATUS_FLAG_DTE_ON 1 389*b843c749SSergey Zigachev 390*b843c749SSergey Zigachev #define SISLANDS_SMC_FIRMWARE_HEADER_LOCATION 0x10000 391*b843c749SSergey Zigachev 392*b843c749SSergey Zigachev #define SISLANDS_SMC_FIRMWARE_HEADER_version 0x0 393*b843c749SSergey Zigachev #define SISLANDS_SMC_FIRMWARE_HEADER_flags 0x4 394*b843c749SSergey Zigachev #define SISLANDS_SMC_FIRMWARE_HEADER_softRegisters 0xC 395*b843c749SSergey Zigachev #define SISLANDS_SMC_FIRMWARE_HEADER_stateTable 0x10 396*b843c749SSergey Zigachev #define SISLANDS_SMC_FIRMWARE_HEADER_fanTable 0x14 397*b843c749SSergey Zigachev #define SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable 0x18 398*b843c749SSergey Zigachev #define SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable 0x24 399*b843c749SSergey Zigachev #define SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable 0x30 400*b843c749SSergey Zigachev #define SISLANDS_SMC_FIRMWARE_HEADER_spllTable 0x38 401*b843c749SSergey Zigachev #define SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration 0x40 402*b843c749SSergey Zigachev #define SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters 0x48 403*b843c749SSergey Zigachev 404*b843c749SSergey Zigachev #pragma pack(pop) 405*b843c749SSergey Zigachev 406*b843c749SSergey Zigachev int amdgpu_si_copy_bytes_to_smc(struct amdgpu_device *adev, 407*b843c749SSergey Zigachev u32 smc_start_address, 408*b843c749SSergey Zigachev const u8 *src, u32 byte_count, u32 limit); 409*b843c749SSergey Zigachev void amdgpu_si_start_smc(struct amdgpu_device *adev); 410*b843c749SSergey Zigachev void amdgpu_si_reset_smc(struct amdgpu_device *adev); 411*b843c749SSergey Zigachev int amdgpu_si_program_jump_on_start(struct amdgpu_device *adev); 412*b843c749SSergey Zigachev void amdgpu_si_smc_clock(struct amdgpu_device *adev, bool enable); 413*b843c749SSergey Zigachev bool amdgpu_si_is_smc_running(struct amdgpu_device *adev); 414*b843c749SSergey Zigachev PPSMC_Result amdgpu_si_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg); 415*b843c749SSergey Zigachev PPSMC_Result amdgpu_si_wait_for_smc_inactive(struct amdgpu_device *adev); 416*b843c749SSergey Zigachev int amdgpu_si_load_smc_ucode(struct amdgpu_device *adev, u32 limit); 417*b843c749SSergey Zigachev int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, 418*b843c749SSergey Zigachev u32 *value, u32 limit); 419*b843c749SSergey Zigachev int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, 420*b843c749SSergey Zigachev u32 value, u32 limit); 421*b843c749SSergey Zigachev 422*b843c749SSergey Zigachev #endif 423*b843c749SSergey Zigachev 424