1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_vcn.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "soc15_common.h" 31 32 #include "vcn/vcn_1_0_offset.h" 33 #include "vcn/vcn_1_0_sh_mask.h" 34 #include "hdp/hdp_4_0_offset.h" 35 #include "mmhub/mmhub_9_1_offset.h" 36 #include "mmhub/mmhub_9_1_sh_mask.h" 37 38 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h" 39 40 static int vcn_v1_0_stop(struct amdgpu_device *adev); 41 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev); 42 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev); 43 static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev); 44 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev); 45 static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr); 46 static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state); 47 48 /** 49 * vcn_v1_0_early_init - set function pointers 50 * 51 * @handle: amdgpu_device pointer 52 * 53 * Set ring and irq function pointers 54 */ 55 static int vcn_v1_0_early_init(void *handle) 56 { 57 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 58 59 adev->vcn.num_enc_rings = 2; 60 61 vcn_v1_0_set_dec_ring_funcs(adev); 62 vcn_v1_0_set_enc_ring_funcs(adev); 63 vcn_v1_0_set_jpeg_ring_funcs(adev); 64 vcn_v1_0_set_irq_funcs(adev); 65 66 return 0; 67 } 68 69 /** 70 * vcn_v1_0_sw_init - sw init for VCN block 71 * 72 * @handle: amdgpu_device pointer 73 * 74 * Load firmware and sw initialization 75 */ 76 static int vcn_v1_0_sw_init(void *handle) 77 { 78 struct amdgpu_ring *ring; 79 int i, r; 80 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 81 82 /* VCN DEC TRAP */ 83 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.irq); 84 if (r) 85 return r; 86 87 /* VCN ENC TRAP */ 88 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 89 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE, 90 &adev->vcn.irq); 91 if (r) 92 return r; 93 } 94 95 /* VCN JPEG TRAP */ 96 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->vcn.irq); 97 if (r) 98 return r; 99 100 r = amdgpu_vcn_sw_init(adev); 101 if (r) 102 return r; 103 104 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 105 const struct common_firmware_header *hdr; 106 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 107 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; 108 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; 109 adev->firmware.fw_size += 110 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 111 DRM_INFO("PSP loading VCN firmware\n"); 112 } 113 114 r = amdgpu_vcn_resume(adev); 115 if (r) 116 return r; 117 118 ring = &adev->vcn.ring_dec; 119 ksprintf(ring->name, "vcn_dec"); 120 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0); 121 if (r) 122 return r; 123 124 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 125 ring = &adev->vcn.ring_enc[i]; 126 ksprintf(ring->name, "vcn_enc%d", i); 127 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0); 128 if (r) 129 return r; 130 } 131 132 ring = &adev->vcn.ring_jpeg; 133 ksprintf(ring->name, "vcn_jpeg"); 134 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0); 135 if (r) 136 return r; 137 138 return r; 139 } 140 141 /** 142 * vcn_v1_0_sw_fini - sw fini for VCN block 143 * 144 * @handle: amdgpu_device pointer 145 * 146 * VCN suspend and free up sw allocation 147 */ 148 static int vcn_v1_0_sw_fini(void *handle) 149 { 150 int r; 151 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 152 153 r = amdgpu_vcn_suspend(adev); 154 if (r) 155 return r; 156 157 r = amdgpu_vcn_sw_fini(adev); 158 159 return r; 160 } 161 162 /** 163 * vcn_v1_0_hw_init - start and test VCN block 164 * 165 * @handle: amdgpu_device pointer 166 * 167 * Initialize the hardware, boot up the VCPU and do some testing 168 */ 169 static int vcn_v1_0_hw_init(void *handle) 170 { 171 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 172 struct amdgpu_ring *ring = &adev->vcn.ring_dec; 173 int i, r; 174 175 ring->ready = true; 176 r = amdgpu_ring_test_ring(ring); 177 if (r) { 178 ring->ready = false; 179 goto done; 180 } 181 182 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 183 ring = &adev->vcn.ring_enc[i]; 184 ring->ready = true; 185 r = amdgpu_ring_test_ring(ring); 186 if (r) { 187 ring->ready = false; 188 goto done; 189 } 190 } 191 192 ring = &adev->vcn.ring_jpeg; 193 ring->ready = true; 194 r = amdgpu_ring_test_ring(ring); 195 if (r) { 196 ring->ready = false; 197 goto done; 198 } 199 200 done: 201 if (!r) 202 DRM_INFO("VCN decode and encode initialized successfully.\n"); 203 204 return r; 205 } 206 207 /** 208 * vcn_v1_0_hw_fini - stop the hardware block 209 * 210 * @handle: amdgpu_device pointer 211 * 212 * Stop the VCN block, mark ring as not ready any more 213 */ 214 static int vcn_v1_0_hw_fini(void *handle) 215 { 216 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 217 struct amdgpu_ring *ring = &adev->vcn.ring_dec; 218 219 if (RREG32_SOC15(VCN, 0, mmUVD_STATUS)) 220 vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 221 222 ring->ready = false; 223 224 return 0; 225 } 226 227 /** 228 * vcn_v1_0_suspend - suspend VCN block 229 * 230 * @handle: amdgpu_device pointer 231 * 232 * HW fini and suspend VCN block 233 */ 234 static int vcn_v1_0_suspend(void *handle) 235 { 236 int r; 237 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 238 239 r = vcn_v1_0_hw_fini(adev); 240 if (r) 241 return r; 242 243 r = amdgpu_vcn_suspend(adev); 244 245 return r; 246 } 247 248 /** 249 * vcn_v1_0_resume - resume VCN block 250 * 251 * @handle: amdgpu_device pointer 252 * 253 * Resume firmware and hw init VCN block 254 */ 255 static int vcn_v1_0_resume(void *handle) 256 { 257 int r; 258 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 259 260 r = amdgpu_vcn_resume(adev); 261 if (r) 262 return r; 263 264 r = vcn_v1_0_hw_init(adev); 265 266 return r; 267 } 268 269 /** 270 * vcn_v1_0_mc_resume - memory controller programming 271 * 272 * @adev: amdgpu_device pointer 273 * 274 * Let the VCN memory controller know it's offsets 275 */ 276 static void vcn_v1_0_mc_resume(struct amdgpu_device *adev) 277 { 278 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->datasize + 4); 279 uint32_t offset; 280 281 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 282 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 283 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo)); 284 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 285 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi)); 286 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); 287 offset = 0; 288 } else { 289 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 290 lower_32_bits(adev->vcn.gpu_addr)); 291 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 292 upper_32_bits(adev->vcn.gpu_addr)); 293 offset = size; 294 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 295 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 296 } 297 298 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); 299 300 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 301 lower_32_bits(adev->vcn.gpu_addr + offset)); 302 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 303 upper_32_bits(adev->vcn.gpu_addr + offset)); 304 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); 305 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_HEAP_SIZE); 306 307 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 308 lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE)); 309 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 310 upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE)); 311 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); 312 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, 313 AMDGPU_VCN_STACK_SIZE + (AMDGPU_VCN_SESSION_SIZE * 40)); 314 315 WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, 316 adev->gfx.config.gb_addr_config); 317 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, 318 adev->gfx.config.gb_addr_config); 319 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 320 adev->gfx.config.gb_addr_config); 321 } 322 323 /** 324 * vcn_v1_0_disable_clock_gating - disable VCN clock gating 325 * 326 * @adev: amdgpu_device pointer 327 * @sw: enable SW clock gating 328 * 329 * Disable clock gating for VCN block 330 */ 331 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev) 332 { 333 uint32_t data; 334 335 /* JPEG disable CGC */ 336 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 337 338 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 339 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 340 else 341 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK; 342 343 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 344 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 345 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); 346 347 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 348 data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); 349 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); 350 351 /* UVD disable CGC */ 352 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 353 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 354 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 355 else 356 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 357 358 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 359 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 360 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 361 362 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); 363 data &= ~(UVD_CGC_GATE__SYS_MASK 364 | UVD_CGC_GATE__UDEC_MASK 365 | UVD_CGC_GATE__MPEG2_MASK 366 | UVD_CGC_GATE__REGS_MASK 367 | UVD_CGC_GATE__RBC_MASK 368 | UVD_CGC_GATE__LMI_MC_MASK 369 | UVD_CGC_GATE__LMI_UMC_MASK 370 | UVD_CGC_GATE__IDCT_MASK 371 | UVD_CGC_GATE__MPRD_MASK 372 | UVD_CGC_GATE__MPC_MASK 373 | UVD_CGC_GATE__LBSI_MASK 374 | UVD_CGC_GATE__LRBBM_MASK 375 | UVD_CGC_GATE__UDEC_RE_MASK 376 | UVD_CGC_GATE__UDEC_CM_MASK 377 | UVD_CGC_GATE__UDEC_IT_MASK 378 | UVD_CGC_GATE__UDEC_DB_MASK 379 | UVD_CGC_GATE__UDEC_MP_MASK 380 | UVD_CGC_GATE__WCB_MASK 381 | UVD_CGC_GATE__VCPU_MASK 382 | UVD_CGC_GATE__SCPU_MASK); 383 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); 384 385 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 386 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 387 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 388 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 389 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 390 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 391 | UVD_CGC_CTRL__SYS_MODE_MASK 392 | UVD_CGC_CTRL__UDEC_MODE_MASK 393 | UVD_CGC_CTRL__MPEG2_MODE_MASK 394 | UVD_CGC_CTRL__REGS_MODE_MASK 395 | UVD_CGC_CTRL__RBC_MODE_MASK 396 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 397 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 398 | UVD_CGC_CTRL__IDCT_MODE_MASK 399 | UVD_CGC_CTRL__MPRD_MODE_MASK 400 | UVD_CGC_CTRL__MPC_MODE_MASK 401 | UVD_CGC_CTRL__LBSI_MODE_MASK 402 | UVD_CGC_CTRL__LRBBM_MODE_MASK 403 | UVD_CGC_CTRL__WCB_MODE_MASK 404 | UVD_CGC_CTRL__VCPU_MODE_MASK 405 | UVD_CGC_CTRL__SCPU_MODE_MASK); 406 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 407 408 /* turn on */ 409 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); 410 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 411 | UVD_SUVD_CGC_GATE__SIT_MASK 412 | UVD_SUVD_CGC_GATE__SMP_MASK 413 | UVD_SUVD_CGC_GATE__SCM_MASK 414 | UVD_SUVD_CGC_GATE__SDB_MASK 415 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 416 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 417 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 418 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 419 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 420 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 421 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 422 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 423 | UVD_SUVD_CGC_GATE__SCLR_MASK 424 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 425 | UVD_SUVD_CGC_GATE__ENT_MASK 426 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 427 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 428 | UVD_SUVD_CGC_GATE__SITE_MASK 429 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 430 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 431 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 432 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 433 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 434 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); 435 436 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 437 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 438 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 439 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 440 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 441 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 442 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 443 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 444 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 445 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 446 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 447 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 448 } 449 450 /** 451 * vcn_v1_0_enable_clock_gating - enable VCN clock gating 452 * 453 * @adev: amdgpu_device pointer 454 * @sw: enable SW clock gating 455 * 456 * Enable clock gating for VCN block 457 */ 458 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev) 459 { 460 uint32_t data = 0; 461 462 /* enable JPEG CGC */ 463 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 464 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 465 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 466 else 467 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 468 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 469 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 470 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); 471 472 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 473 data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); 474 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); 475 476 /* enable UVD CGC */ 477 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 478 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 479 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 480 else 481 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 482 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 483 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 484 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 485 486 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 487 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 488 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 489 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 490 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 491 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 492 | UVD_CGC_CTRL__SYS_MODE_MASK 493 | UVD_CGC_CTRL__UDEC_MODE_MASK 494 | UVD_CGC_CTRL__MPEG2_MODE_MASK 495 | UVD_CGC_CTRL__REGS_MODE_MASK 496 | UVD_CGC_CTRL__RBC_MODE_MASK 497 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 498 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 499 | UVD_CGC_CTRL__IDCT_MODE_MASK 500 | UVD_CGC_CTRL__MPRD_MODE_MASK 501 | UVD_CGC_CTRL__MPC_MODE_MASK 502 | UVD_CGC_CTRL__LBSI_MODE_MASK 503 | UVD_CGC_CTRL__LRBBM_MODE_MASK 504 | UVD_CGC_CTRL__WCB_MODE_MASK 505 | UVD_CGC_CTRL__VCPU_MODE_MASK 506 | UVD_CGC_CTRL__SCPU_MODE_MASK); 507 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 508 509 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 510 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 511 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 512 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 513 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 514 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 515 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 516 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 517 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 518 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 519 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 520 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 521 } 522 523 static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev) 524 { 525 uint32_t data = 0; 526 int ret; 527 528 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 529 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 530 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 531 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 532 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 533 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 534 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 535 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 536 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 537 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 538 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 539 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 540 541 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 542 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF, ret); 543 } else { 544 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 545 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 546 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 547 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 548 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 549 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 550 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 551 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 552 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 553 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 554 | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 555 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 556 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF, ret); 557 } 558 559 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */ 560 561 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 562 data &= ~0x103; 563 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 564 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK; 565 566 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 567 } 568 569 static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev) 570 { 571 uint32_t data = 0; 572 int ret; 573 574 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 575 /* Before power off, this indicator has to be turned on */ 576 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 577 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 578 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 579 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 580 581 582 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 583 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 584 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 585 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 586 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 587 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 588 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 589 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 590 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 591 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 592 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 593 594 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 595 596 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 597 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 598 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 599 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 600 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 601 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 602 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 603 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 604 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 605 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 606 | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT); 607 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF, ret); 608 } 609 } 610 611 /** 612 * vcn_v1_0_start - start VCN block 613 * 614 * @adev: amdgpu_device pointer 615 * 616 * Setup and start the VCN block 617 */ 618 static int vcn_v1_0_start(struct amdgpu_device *adev) 619 { 620 struct amdgpu_ring *ring = &adev->vcn.ring_dec; 621 uint32_t rb_bufsz, tmp; 622 uint32_t lmi_swap_cntl; 623 int i, j, r; 624 625 /* disable byte swapping */ 626 lmi_swap_cntl = 0; 627 628 vcn_1_0_disable_static_power_gating(adev); 629 /* disable clock gating */ 630 vcn_v1_0_disable_clock_gating(adev); 631 632 vcn_v1_0_mc_resume(adev); 633 634 /* disable interupt */ 635 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, 636 ~UVD_MASTINT_EN__VCPU_EN_MASK); 637 638 /* stall UMC and register bus before resetting VCPU */ 639 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 640 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 641 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 642 mdelay(1); 643 644 /* put LMI, VCPU, RBC etc... into reset */ 645 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 646 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 647 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 648 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 649 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | 650 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 651 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | 652 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 653 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 654 mdelay(5); 655 656 /* initialize VCN memory controller */ 657 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, 658 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 659 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 660 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 661 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 662 UVD_LMI_CTRL__REQ_MODE_MASK | 663 0x00100000L); 664 665 #ifdef __BIG_ENDIAN 666 /* swap (8 in 32) RB and IB */ 667 lmi_swap_cntl = 0xa; 668 #endif 669 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 670 671 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 0x40c2040); 672 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA1, 0x0); 673 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 0x40c2040); 674 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB1, 0x0); 675 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_ALU, 0); 676 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 0x88); 677 678 /* take all subblocks out of reset, except VCPU */ 679 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 680 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 681 mdelay(5); 682 683 /* enable VCPU clock */ 684 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, 685 UVD_VCPU_CNTL__CLK_EN_MASK); 686 687 /* enable UMC */ 688 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 689 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 690 691 /* boot up the VCPU */ 692 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 0); 693 mdelay(10); 694 695 for (i = 0; i < 10; ++i) { 696 uint32_t status; 697 698 for (j = 0; j < 100; ++j) { 699 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); 700 if (status & 2) 701 break; 702 mdelay(10); 703 } 704 r = 0; 705 if (status & 2) 706 break; 707 708 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 709 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 710 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 711 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 712 mdelay(10); 713 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 714 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 715 mdelay(10); 716 r = -1; 717 } 718 719 if (r) { 720 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 721 return r; 722 } 723 /* enable master interrupt */ 724 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 725 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 726 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); 727 728 /* clear the bit 4 of VCN_STATUS */ 729 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, 730 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 731 732 /* force RBC into idle state */ 733 rb_bufsz = order_base_2(ring->ring_size); 734 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 735 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 736 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 737 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 738 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 739 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 740 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 741 742 /* set the write pointer delay */ 743 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 744 745 /* set the wb address */ 746 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 747 (upper_32_bits(ring->gpu_addr) >> 2)); 748 749 /* programm the RB_BASE for ring buffer */ 750 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 751 lower_32_bits(ring->gpu_addr)); 752 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 753 upper_32_bits(ring->gpu_addr)); 754 755 /* Initialize the ring buffer's read and write pointers */ 756 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 757 758 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 759 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 760 lower_32_bits(ring->wptr)); 761 762 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, 763 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 764 765 ring = &adev->vcn.ring_enc[0]; 766 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 767 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 768 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 769 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 770 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 771 772 ring = &adev->vcn.ring_enc[1]; 773 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 774 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 775 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 776 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 777 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 778 779 ring = &adev->vcn.ring_jpeg; 780 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 781 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 782 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr)); 783 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr)); 784 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0); 785 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0); 786 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L); 787 788 /* initialize wptr */ 789 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); 790 791 /* copy patch commands to the jpeg ring */ 792 vcn_v1_0_jpeg_ring_set_patch_ring(ring, 793 (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission)); 794 795 return 0; 796 } 797 798 /** 799 * vcn_v1_0_stop - stop VCN block 800 * 801 * @adev: amdgpu_device pointer 802 * 803 * stop the VCN block 804 */ 805 static int vcn_v1_0_stop(struct amdgpu_device *adev) 806 { 807 /* force RBC into idle state */ 808 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, 0x11010101); 809 810 /* Stall UMC and register bus before resetting VCPU */ 811 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 812 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 813 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 814 mdelay(1); 815 816 /* put VCPU into reset */ 817 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 818 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 819 mdelay(5); 820 821 /* disable VCPU clock */ 822 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, 0x0); 823 824 /* Unstall UMC and register bus */ 825 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 826 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 827 828 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0); 829 830 vcn_v1_0_enable_clock_gating(adev); 831 vcn_1_0_enable_static_power_gating(adev); 832 return 0; 833 } 834 835 static bool vcn_v1_0_is_idle(void *handle) 836 { 837 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 838 839 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == 0x2); 840 } 841 842 static int vcn_v1_0_wait_for_idle(void *handle) 843 { 844 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 845 int ret = 0; 846 847 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, 0x2, 0x2, ret); 848 849 return ret; 850 } 851 852 static int vcn_v1_0_set_clockgating_state(void *handle, 853 enum amd_clockgating_state state) 854 { 855 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 856 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 857 858 if (enable) { 859 /* wait for STATUS to clear */ 860 if (!vcn_v1_0_is_idle(handle)) 861 return -EBUSY; 862 vcn_v1_0_enable_clock_gating(adev); 863 } else { 864 /* disable HW gating and enable Sw gating */ 865 vcn_v1_0_disable_clock_gating(adev); 866 } 867 return 0; 868 } 869 870 /** 871 * vcn_v1_0_dec_ring_get_rptr - get read pointer 872 * 873 * @ring: amdgpu_ring pointer 874 * 875 * Returns the current hardware read pointer 876 */ 877 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 878 { 879 struct amdgpu_device *adev = ring->adev; 880 881 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 882 } 883 884 /** 885 * vcn_v1_0_dec_ring_get_wptr - get write pointer 886 * 887 * @ring: amdgpu_ring pointer 888 * 889 * Returns the current hardware write pointer 890 */ 891 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 892 { 893 struct amdgpu_device *adev = ring->adev; 894 895 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); 896 } 897 898 /** 899 * vcn_v1_0_dec_ring_set_wptr - set write pointer 900 * 901 * @ring: amdgpu_ring pointer 902 * 903 * Commits the write pointer to the hardware 904 */ 905 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 906 { 907 struct amdgpu_device *adev = ring->adev; 908 909 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 910 } 911 912 /** 913 * vcn_v1_0_dec_ring_insert_start - insert a start command 914 * 915 * @ring: amdgpu_ring pointer 916 * 917 * Write a start command to the ring. 918 */ 919 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring) 920 { 921 struct amdgpu_device *adev = ring->adev; 922 923 amdgpu_ring_write(ring, 924 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 925 amdgpu_ring_write(ring, 0); 926 amdgpu_ring_write(ring, 927 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 928 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); 929 } 930 931 /** 932 * vcn_v1_0_dec_ring_insert_end - insert a end command 933 * 934 * @ring: amdgpu_ring pointer 935 * 936 * Write a end command to the ring. 937 */ 938 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring) 939 { 940 struct amdgpu_device *adev = ring->adev; 941 942 amdgpu_ring_write(ring, 943 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 944 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); 945 } 946 947 /** 948 * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command 949 * 950 * @ring: amdgpu_ring pointer 951 * @fence: fence to emit 952 * 953 * Write a fence and a trap command to the ring. 954 */ 955 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, uint64_t addr, uint64_t seq, 956 unsigned flags) 957 { 958 struct amdgpu_device *adev = ring->adev; 959 960 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 961 962 amdgpu_ring_write(ring, 963 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); 964 amdgpu_ring_write(ring, seq); 965 amdgpu_ring_write(ring, 966 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 967 amdgpu_ring_write(ring, addr & 0xffffffff); 968 amdgpu_ring_write(ring, 969 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 970 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 971 amdgpu_ring_write(ring, 972 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 973 amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1); 974 975 amdgpu_ring_write(ring, 976 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 977 amdgpu_ring_write(ring, 0); 978 amdgpu_ring_write(ring, 979 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 980 amdgpu_ring_write(ring, 0); 981 amdgpu_ring_write(ring, 982 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 983 amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1); 984 } 985 986 /** 987 * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer 988 * 989 * @ring: amdgpu_ring pointer 990 * @ib: indirect buffer to execute 991 * 992 * Write ring commands to execute the indirect buffer 993 */ 994 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 995 struct amdgpu_ib *ib, 996 unsigned vmid, bool ctx_switch) 997 { 998 struct amdgpu_device *adev = ring->adev; 999 1000 amdgpu_ring_write(ring, 1001 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0)); 1002 amdgpu_ring_write(ring, vmid); 1003 1004 amdgpu_ring_write(ring, 1005 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); 1006 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1007 amdgpu_ring_write(ring, 1008 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); 1009 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1010 amdgpu_ring_write(ring, 1011 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0)); 1012 amdgpu_ring_write(ring, ib->length_dw); 1013 } 1014 1015 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, 1016 uint32_t reg, uint32_t val, 1017 uint32_t mask) 1018 { 1019 struct amdgpu_device *adev = ring->adev; 1020 1021 amdgpu_ring_write(ring, 1022 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1023 amdgpu_ring_write(ring, reg << 2); 1024 amdgpu_ring_write(ring, 1025 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1026 amdgpu_ring_write(ring, val); 1027 amdgpu_ring_write(ring, 1028 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0)); 1029 amdgpu_ring_write(ring, mask); 1030 amdgpu_ring_write(ring, 1031 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1032 amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1); 1033 } 1034 1035 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 1036 unsigned vmid, uint64_t pd_addr) 1037 { 1038 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1039 uint32_t data0, data1, mask; 1040 1041 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1042 1043 /* wait for register write */ 1044 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2; 1045 data1 = lower_32_bits(pd_addr); 1046 mask = 0xffffffff; 1047 vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); 1048 } 1049 1050 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, 1051 uint32_t reg, uint32_t val) 1052 { 1053 struct amdgpu_device *adev = ring->adev; 1054 1055 amdgpu_ring_write(ring, 1056 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1057 amdgpu_ring_write(ring, reg << 2); 1058 amdgpu_ring_write(ring, 1059 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1060 amdgpu_ring_write(ring, val); 1061 amdgpu_ring_write(ring, 1062 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1063 amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1); 1064 } 1065 1066 /** 1067 * vcn_v1_0_enc_ring_get_rptr - get enc read pointer 1068 * 1069 * @ring: amdgpu_ring pointer 1070 * 1071 * Returns the current hardware enc read pointer 1072 */ 1073 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1074 { 1075 struct amdgpu_device *adev = ring->adev; 1076 1077 if (ring == &adev->vcn.ring_enc[0]) 1078 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); 1079 else 1080 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); 1081 } 1082 1083 /** 1084 * vcn_v1_0_enc_ring_get_wptr - get enc write pointer 1085 * 1086 * @ring: amdgpu_ring pointer 1087 * 1088 * Returns the current hardware enc write pointer 1089 */ 1090 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 1091 { 1092 struct amdgpu_device *adev = ring->adev; 1093 1094 if (ring == &adev->vcn.ring_enc[0]) 1095 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1096 else 1097 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1098 } 1099 1100 /** 1101 * vcn_v1_0_enc_ring_set_wptr - set enc write pointer 1102 * 1103 * @ring: amdgpu_ring pointer 1104 * 1105 * Commits the enc write pointer to the hardware 1106 */ 1107 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 1108 { 1109 struct amdgpu_device *adev = ring->adev; 1110 1111 if (ring == &adev->vcn.ring_enc[0]) 1112 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, 1113 lower_32_bits(ring->wptr)); 1114 else 1115 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, 1116 lower_32_bits(ring->wptr)); 1117 } 1118 1119 /** 1120 * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command 1121 * 1122 * @ring: amdgpu_ring pointer 1123 * @fence: fence to emit 1124 * 1125 * Write enc a fence and a trap command to the ring. 1126 */ 1127 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, uint64_t addr, 1128 uint64_t seq, unsigned flags) 1129 { 1130 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1131 1132 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE); 1133 amdgpu_ring_write(ring, addr); 1134 amdgpu_ring_write(ring, upper_32_bits(addr)); 1135 amdgpu_ring_write(ring, seq); 1136 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); 1137 } 1138 1139 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1140 { 1141 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 1142 } 1143 1144 /** 1145 * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer 1146 * 1147 * @ring: amdgpu_ring pointer 1148 * @ib: indirect buffer to execute 1149 * 1150 * Write enc ring commands to execute the indirect buffer 1151 */ 1152 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1153 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch) 1154 { 1155 amdgpu_ring_write(ring, VCN_ENC_CMD_IB); 1156 amdgpu_ring_write(ring, vmid); 1157 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1158 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1159 amdgpu_ring_write(ring, ib->length_dw); 1160 } 1161 1162 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, 1163 uint32_t reg, uint32_t val, 1164 uint32_t mask) 1165 { 1166 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1167 amdgpu_ring_write(ring, reg << 2); 1168 amdgpu_ring_write(ring, mask); 1169 amdgpu_ring_write(ring, val); 1170 } 1171 1172 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1173 unsigned int vmid, uint64_t pd_addr) 1174 { 1175 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1176 1177 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1178 1179 /* wait for reg writes */ 1180 vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2, 1181 lower_32_bits(pd_addr), 0xffffffff); 1182 } 1183 1184 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, 1185 uint32_t reg, uint32_t val) 1186 { 1187 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1188 amdgpu_ring_write(ring, reg << 2); 1189 amdgpu_ring_write(ring, val); 1190 } 1191 1192 1193 /** 1194 * vcn_v1_0_jpeg_ring_get_rptr - get read pointer 1195 * 1196 * @ring: amdgpu_ring pointer 1197 * 1198 * Returns the current hardware read pointer 1199 */ 1200 static uint64_t vcn_v1_0_jpeg_ring_get_rptr(struct amdgpu_ring *ring) 1201 { 1202 struct amdgpu_device *adev = ring->adev; 1203 1204 return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR); 1205 } 1206 1207 /** 1208 * vcn_v1_0_jpeg_ring_get_wptr - get write pointer 1209 * 1210 * @ring: amdgpu_ring pointer 1211 * 1212 * Returns the current hardware write pointer 1213 */ 1214 static uint64_t vcn_v1_0_jpeg_ring_get_wptr(struct amdgpu_ring *ring) 1215 { 1216 struct amdgpu_device *adev = ring->adev; 1217 1218 return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); 1219 } 1220 1221 /** 1222 * vcn_v1_0_jpeg_ring_set_wptr - set write pointer 1223 * 1224 * @ring: amdgpu_ring pointer 1225 * 1226 * Commits the write pointer to the hardware 1227 */ 1228 static void vcn_v1_0_jpeg_ring_set_wptr(struct amdgpu_ring *ring) 1229 { 1230 struct amdgpu_device *adev = ring->adev; 1231 1232 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 1233 } 1234 1235 /** 1236 * vcn_v1_0_jpeg_ring_insert_start - insert a start command 1237 * 1238 * @ring: amdgpu_ring pointer 1239 * 1240 * Write a start command to the ring. 1241 */ 1242 static void vcn_v1_0_jpeg_ring_insert_start(struct amdgpu_ring *ring) 1243 { 1244 struct amdgpu_device *adev = ring->adev; 1245 1246 amdgpu_ring_write(ring, 1247 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); 1248 amdgpu_ring_write(ring, 0x68e04); 1249 1250 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0)); 1251 amdgpu_ring_write(ring, 0x80010000); 1252 } 1253 1254 /** 1255 * vcn_v1_0_jpeg_ring_insert_end - insert a end command 1256 * 1257 * @ring: amdgpu_ring pointer 1258 * 1259 * Write a end command to the ring. 1260 */ 1261 static void vcn_v1_0_jpeg_ring_insert_end(struct amdgpu_ring *ring) 1262 { 1263 struct amdgpu_device *adev = ring->adev; 1264 1265 amdgpu_ring_write(ring, 1266 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); 1267 amdgpu_ring_write(ring, 0x68e04); 1268 1269 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0)); 1270 amdgpu_ring_write(ring, 0x00010000); 1271 } 1272 1273 /** 1274 * vcn_v1_0_jpeg_ring_emit_fence - emit an fence & trap command 1275 * 1276 * @ring: amdgpu_ring pointer 1277 * @fence: fence to emit 1278 * 1279 * Write a fence and a trap command to the ring. 1280 */ 1281 static void vcn_v1_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, uint64_t addr, uint64_t seq, 1282 unsigned flags) 1283 { 1284 struct amdgpu_device *adev = ring->adev; 1285 1286 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1287 1288 amdgpu_ring_write(ring, 1289 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA0), 0, 0, PACKETJ_TYPE0)); 1290 amdgpu_ring_write(ring, seq); 1291 1292 amdgpu_ring_write(ring, 1293 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA1), 0, 0, PACKETJ_TYPE0)); 1294 amdgpu_ring_write(ring, seq); 1295 1296 amdgpu_ring_write(ring, 1297 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0)); 1298 amdgpu_ring_write(ring, lower_32_bits(addr)); 1299 1300 amdgpu_ring_write(ring, 1301 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); 1302 amdgpu_ring_write(ring, upper_32_bits(addr)); 1303 1304 amdgpu_ring_write(ring, 1305 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, 0, PACKETJ_TYPE0)); 1306 amdgpu_ring_write(ring, 0x8); 1307 1308 amdgpu_ring_write(ring, 1309 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); 1310 amdgpu_ring_write(ring, 0); 1311 1312 amdgpu_ring_write(ring, 1313 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0)); 1314 amdgpu_ring_write(ring, 0x01400200); 1315 1316 amdgpu_ring_write(ring, 1317 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0)); 1318 amdgpu_ring_write(ring, seq); 1319 1320 amdgpu_ring_write(ring, 1321 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0)); 1322 amdgpu_ring_write(ring, lower_32_bits(addr)); 1323 1324 amdgpu_ring_write(ring, 1325 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); 1326 amdgpu_ring_write(ring, upper_32_bits(addr)); 1327 1328 amdgpu_ring_write(ring, 1329 PACKETJ(0, 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE2)); 1330 amdgpu_ring_write(ring, 0xffffffff); 1331 1332 amdgpu_ring_write(ring, 1333 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); 1334 amdgpu_ring_write(ring, 0x3fbc); 1335 1336 amdgpu_ring_write(ring, 1337 PACKETJ(0, 0, 0, PACKETJ_TYPE0)); 1338 amdgpu_ring_write(ring, 0x1); 1339 } 1340 1341 /** 1342 * vcn_v1_0_jpeg_ring_emit_ib - execute indirect buffer 1343 * 1344 * @ring: amdgpu_ring pointer 1345 * @ib: indirect buffer to execute 1346 * 1347 * Write ring commands to execute the indirect buffer. 1348 */ 1349 static void vcn_v1_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring, 1350 struct amdgpu_ib *ib, 1351 unsigned vmid, bool ctx_switch) 1352 { 1353 struct amdgpu_device *adev = ring->adev; 1354 1355 amdgpu_ring_write(ring, 1356 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0)); 1357 amdgpu_ring_write(ring, (vmid | (vmid << 4))); 1358 1359 amdgpu_ring_write(ring, 1360 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0)); 1361 amdgpu_ring_write(ring, (vmid | (vmid << 4))); 1362 1363 amdgpu_ring_write(ring, 1364 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0)); 1365 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1366 1367 amdgpu_ring_write(ring, 1368 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); 1369 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1370 1371 amdgpu_ring_write(ring, 1372 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_IB_SIZE), 0, 0, PACKETJ_TYPE0)); 1373 amdgpu_ring_write(ring, ib->length_dw); 1374 1375 amdgpu_ring_write(ring, 1376 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0)); 1377 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); 1378 1379 amdgpu_ring_write(ring, 1380 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0)); 1381 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); 1382 1383 amdgpu_ring_write(ring, 1384 PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); 1385 amdgpu_ring_write(ring, 0); 1386 1387 amdgpu_ring_write(ring, 1388 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0)); 1389 amdgpu_ring_write(ring, 0x01400200); 1390 1391 amdgpu_ring_write(ring, 1392 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0)); 1393 amdgpu_ring_write(ring, 0x2); 1394 1395 amdgpu_ring_write(ring, 1396 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_STATUS), 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); 1397 amdgpu_ring_write(ring, 0x2); 1398 } 1399 1400 static void vcn_v1_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring, 1401 uint32_t reg, uint32_t val, 1402 uint32_t mask) 1403 { 1404 struct amdgpu_device *adev = ring->adev; 1405 uint32_t reg_offset = (reg << 2); 1406 1407 amdgpu_ring_write(ring, 1408 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0)); 1409 amdgpu_ring_write(ring, 0x01400200); 1410 1411 amdgpu_ring_write(ring, 1412 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0)); 1413 amdgpu_ring_write(ring, val); 1414 1415 amdgpu_ring_write(ring, 1416 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); 1417 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || 1418 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { 1419 amdgpu_ring_write(ring, 0); 1420 amdgpu_ring_write(ring, 1421 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); 1422 } else { 1423 amdgpu_ring_write(ring, reg_offset); 1424 amdgpu_ring_write(ring, 1425 PACKETJ(0, 0, 0, PACKETJ_TYPE3)); 1426 } 1427 amdgpu_ring_write(ring, mask); 1428 } 1429 1430 static void vcn_v1_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring, 1431 unsigned vmid, uint64_t pd_addr) 1432 { 1433 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1434 uint32_t data0, data1, mask; 1435 1436 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1437 1438 /* wait for register write */ 1439 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2; 1440 data1 = lower_32_bits(pd_addr); 1441 mask = 0xffffffff; 1442 vcn_v1_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask); 1443 } 1444 1445 static void vcn_v1_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, 1446 uint32_t reg, uint32_t val) 1447 { 1448 struct amdgpu_device *adev = ring->adev; 1449 uint32_t reg_offset = (reg << 2); 1450 1451 amdgpu_ring_write(ring, 1452 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0)); 1453 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || 1454 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { 1455 amdgpu_ring_write(ring, 0); 1456 amdgpu_ring_write(ring, 1457 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); 1458 } else { 1459 amdgpu_ring_write(ring, reg_offset); 1460 amdgpu_ring_write(ring, 1461 PACKETJ(0, 0, 0, PACKETJ_TYPE0)); 1462 } 1463 amdgpu_ring_write(ring, val); 1464 } 1465 1466 static void vcn_v1_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count) 1467 { 1468 int i; 1469 1470 WARN_ON(ring->wptr % 2 || count % 2); 1471 1472 for (i = 0; i < count / 2; i++) { 1473 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 1474 amdgpu_ring_write(ring, 0); 1475 } 1476 } 1477 1478 static void vcn_v1_0_jpeg_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val) 1479 { 1480 struct amdgpu_device *adev = ring->adev; 1481 ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0); 1482 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || 1483 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { 1484 ring->ring[(*ptr)++] = 0; 1485 ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0); 1486 } else { 1487 ring->ring[(*ptr)++] = reg_offset; 1488 ring->ring[(*ptr)++] = PACKETJ(0, 0, 0, PACKETJ_TYPE0); 1489 } 1490 ring->ring[(*ptr)++] = val; 1491 } 1492 1493 static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr) 1494 { 1495 struct amdgpu_device *adev = ring->adev; 1496 1497 uint32_t reg, reg_offset, val, mask, i; 1498 1499 // 1st: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 1500 reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW); 1501 reg_offset = (reg << 2); 1502 val = lower_32_bits(ring->gpu_addr); 1503 vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); 1504 1505 // 2nd: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 1506 reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH); 1507 reg_offset = (reg << 2); 1508 val = upper_32_bits(ring->gpu_addr); 1509 vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); 1510 1511 // 3rd to 5th: issue MEM_READ commands 1512 for (i = 0; i <= 2; i++) { 1513 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE2); 1514 ring->ring[ptr++] = 0; 1515 } 1516 1517 // 6th: program mmUVD_JRBC_RB_CNTL register to enable NO_FETCH and RPTR write ability 1518 reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL); 1519 reg_offset = (reg << 2); 1520 val = 0x13; 1521 vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); 1522 1523 // 7th: program mmUVD_JRBC_RB_REF_DATA 1524 reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA); 1525 reg_offset = (reg << 2); 1526 val = 0x1; 1527 vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); 1528 1529 // 8th: issue conditional register read mmUVD_JRBC_RB_CNTL 1530 reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL); 1531 reg_offset = (reg << 2); 1532 val = 0x1; 1533 mask = 0x1; 1534 1535 ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0); 1536 ring->ring[ptr++] = 0x01400200; 1537 ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0); 1538 ring->ring[ptr++] = val; 1539 ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0); 1540 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || 1541 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { 1542 ring->ring[ptr++] = 0; 1543 ring->ring[ptr++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3); 1544 } else { 1545 ring->ring[ptr++] = reg_offset; 1546 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE3); 1547 } 1548 ring->ring[ptr++] = mask; 1549 1550 //9th to 21st: insert no-op 1551 for (i = 0; i <= 12; i++) { 1552 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE6); 1553 ring->ring[ptr++] = 0; 1554 } 1555 1556 //22nd: reset mmUVD_JRBC_RB_RPTR 1557 reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_RPTR); 1558 reg_offset = (reg << 2); 1559 val = 0; 1560 vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); 1561 1562 //23rd: program mmUVD_JRBC_RB_CNTL to disable no_fetch 1563 reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL); 1564 reg_offset = (reg << 2); 1565 val = 0x12; 1566 vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); 1567 } 1568 1569 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev, 1570 struct amdgpu_irq_src *source, 1571 unsigned type, 1572 enum amdgpu_interrupt_state state) 1573 { 1574 return 0; 1575 } 1576 1577 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev, 1578 struct amdgpu_irq_src *source, 1579 struct amdgpu_iv_entry *entry) 1580 { 1581 DRM_DEBUG("IH: VCN TRAP\n"); 1582 1583 switch (entry->src_id) { 1584 case 124: 1585 amdgpu_fence_process(&adev->vcn.ring_dec); 1586 break; 1587 case 119: 1588 amdgpu_fence_process(&adev->vcn.ring_enc[0]); 1589 break; 1590 case 120: 1591 amdgpu_fence_process(&adev->vcn.ring_enc[1]); 1592 break; 1593 case 126: 1594 amdgpu_fence_process(&adev->vcn.ring_jpeg); 1595 break; 1596 default: 1597 DRM_ERROR("Unhandled interrupt: %d %d\n", 1598 entry->src_id, entry->src_data[0]); 1599 break; 1600 } 1601 1602 return 0; 1603 } 1604 1605 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1606 { 1607 struct amdgpu_device *adev = ring->adev; 1608 int i; 1609 1610 WARN_ON(ring->wptr % 2 || count % 2); 1611 1612 for (i = 0; i < count / 2; i++) { 1613 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0)); 1614 amdgpu_ring_write(ring, 0); 1615 } 1616 } 1617 1618 static int vcn_v1_0_set_powergating_state(void *handle, 1619 enum amd_powergating_state state) 1620 { 1621 /* This doesn't actually powergate the VCN block. 1622 * That's done in the dpm code via the SMC. This 1623 * just re-inits the block as necessary. The actual 1624 * gating still happens in the dpm code. We should 1625 * revisit this when there is a cleaner line between 1626 * the smc and the hw blocks 1627 */ 1628 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1629 1630 if (state == AMD_PG_STATE_GATE) 1631 return vcn_v1_0_stop(adev); 1632 else 1633 return vcn_v1_0_start(adev); 1634 } 1635 1636 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = { 1637 .name = "vcn_v1_0", 1638 .early_init = vcn_v1_0_early_init, 1639 .late_init = NULL, 1640 .sw_init = vcn_v1_0_sw_init, 1641 .sw_fini = vcn_v1_0_sw_fini, 1642 .hw_init = vcn_v1_0_hw_init, 1643 .hw_fini = vcn_v1_0_hw_fini, 1644 .suspend = vcn_v1_0_suspend, 1645 .resume = vcn_v1_0_resume, 1646 .is_idle = vcn_v1_0_is_idle, 1647 .wait_for_idle = vcn_v1_0_wait_for_idle, 1648 .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */, 1649 .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */, 1650 .soft_reset = NULL /* vcn_v1_0_soft_reset */, 1651 .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */, 1652 .set_clockgating_state = vcn_v1_0_set_clockgating_state, 1653 .set_powergating_state = vcn_v1_0_set_powergating_state, 1654 }; 1655 1656 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { 1657 .type = AMDGPU_RING_TYPE_VCN_DEC, 1658 .align_mask = 0xf, 1659 .support_64bit_ptrs = false, 1660 .vmhub = AMDGPU_MMHUB, 1661 .get_rptr = vcn_v1_0_dec_ring_get_rptr, 1662 .get_wptr = vcn_v1_0_dec_ring_get_wptr, 1663 .set_wptr = vcn_v1_0_dec_ring_set_wptr, 1664 .emit_frame_size = 1665 6 + 6 + /* hdp invalidate / flush */ 1666 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1667 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1668 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */ 1669 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */ 1670 6, 1671 .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */ 1672 .emit_ib = vcn_v1_0_dec_ring_emit_ib, 1673 .emit_fence = vcn_v1_0_dec_ring_emit_fence, 1674 .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush, 1675 .test_ring = amdgpu_vcn_dec_ring_test_ring, 1676 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1677 .insert_nop = vcn_v1_0_dec_ring_insert_nop, 1678 .insert_start = vcn_v1_0_dec_ring_insert_start, 1679 .insert_end = vcn_v1_0_dec_ring_insert_end, 1680 .pad_ib = amdgpu_ring_generic_pad_ib, 1681 .begin_use = amdgpu_vcn_ring_begin_use, 1682 .end_use = amdgpu_vcn_ring_end_use, 1683 .emit_wreg = vcn_v1_0_dec_ring_emit_wreg, 1684 .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait, 1685 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1686 }; 1687 1688 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = { 1689 .type = AMDGPU_RING_TYPE_VCN_ENC, 1690 .align_mask = 0x3f, 1691 .nop = VCN_ENC_CMD_NO_OP, 1692 .support_64bit_ptrs = false, 1693 .vmhub = AMDGPU_MMHUB, 1694 .get_rptr = vcn_v1_0_enc_ring_get_rptr, 1695 .get_wptr = vcn_v1_0_enc_ring_get_wptr, 1696 .set_wptr = vcn_v1_0_enc_ring_set_wptr, 1697 .emit_frame_size = 1698 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1699 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1700 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */ 1701 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */ 1702 1, /* vcn_v1_0_enc_ring_insert_end */ 1703 .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */ 1704 .emit_ib = vcn_v1_0_enc_ring_emit_ib, 1705 .emit_fence = vcn_v1_0_enc_ring_emit_fence, 1706 .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush, 1707 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1708 .test_ib = amdgpu_vcn_enc_ring_test_ib, 1709 .insert_nop = amdgpu_ring_insert_nop, 1710 .insert_end = vcn_v1_0_enc_ring_insert_end, 1711 .pad_ib = amdgpu_ring_generic_pad_ib, 1712 .begin_use = amdgpu_vcn_ring_begin_use, 1713 .end_use = amdgpu_vcn_ring_end_use, 1714 .emit_wreg = vcn_v1_0_enc_ring_emit_wreg, 1715 .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait, 1716 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1717 }; 1718 1719 static const struct amdgpu_ring_funcs vcn_v1_0_jpeg_ring_vm_funcs = { 1720 .type = AMDGPU_RING_TYPE_VCN_JPEG, 1721 .align_mask = 0xf, 1722 .nop = PACKET0(0x81ff, 0), 1723 .support_64bit_ptrs = false, 1724 .vmhub = AMDGPU_MMHUB, 1725 .extra_dw = 64, 1726 .get_rptr = vcn_v1_0_jpeg_ring_get_rptr, 1727 .get_wptr = vcn_v1_0_jpeg_ring_get_wptr, 1728 .set_wptr = vcn_v1_0_jpeg_ring_set_wptr, 1729 .emit_frame_size = 1730 6 + 6 + /* hdp invalidate / flush */ 1731 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1732 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1733 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */ 1734 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */ 1735 6, 1736 .emit_ib_size = 22, /* vcn_v1_0_dec_ring_emit_ib */ 1737 .emit_ib = vcn_v1_0_jpeg_ring_emit_ib, 1738 .emit_fence = vcn_v1_0_jpeg_ring_emit_fence, 1739 .emit_vm_flush = vcn_v1_0_jpeg_ring_emit_vm_flush, 1740 .test_ring = amdgpu_vcn_jpeg_ring_test_ring, 1741 .test_ib = amdgpu_vcn_jpeg_ring_test_ib, 1742 .insert_nop = vcn_v1_0_jpeg_ring_nop, 1743 .insert_start = vcn_v1_0_jpeg_ring_insert_start, 1744 .insert_end = vcn_v1_0_jpeg_ring_insert_end, 1745 .pad_ib = amdgpu_ring_generic_pad_ib, 1746 .begin_use = amdgpu_vcn_ring_begin_use, 1747 .end_use = amdgpu_vcn_ring_end_use, 1748 .emit_wreg = vcn_v1_0_jpeg_ring_emit_wreg, 1749 .emit_reg_wait = vcn_v1_0_jpeg_ring_emit_reg_wait, 1750 }; 1751 1752 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev) 1753 { 1754 adev->vcn.ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs; 1755 DRM_INFO("VCN decode is enabled in VM mode\n"); 1756 } 1757 1758 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev) 1759 { 1760 int i; 1761 1762 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 1763 adev->vcn.ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs; 1764 1765 DRM_INFO("VCN encode is enabled in VM mode\n"); 1766 } 1767 1768 static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev) 1769 { 1770 adev->vcn.ring_jpeg.funcs = &vcn_v1_0_jpeg_ring_vm_funcs; 1771 DRM_INFO("VCN jpeg decode is enabled in VM mode\n"); 1772 } 1773 1774 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = { 1775 .set = vcn_v1_0_set_interrupt_state, 1776 .process = vcn_v1_0_process_interrupt, 1777 }; 1778 1779 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev) 1780 { 1781 adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 1; 1782 adev->vcn.irq.funcs = &vcn_v1_0_irq_funcs; 1783 } 1784 1785 const struct amdgpu_ip_block_version vcn_v1_0_ip_block = 1786 { 1787 .type = AMD_IP_BLOCK_TYPE_VCN, 1788 .major = 1, 1789 .minor = 0, 1790 .rev = 0, 1791 .funcs = &vcn_v1_0_ip_funcs, 1792 }; 1793