1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2014 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev */ 23*b843c749SSergey Zigachev #ifndef VI_H 24*b843c749SSergey Zigachev #define VI_H 25*b843c749SSergey Zigachev 26*b843c749SSergey Zigachev #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ 27*b843c749SSergey Zigachev #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ 28*b843c749SSergey Zigachev #define SDMA_MAX_INSTANCE 2 29*b843c749SSergey Zigachev 30*b843c749SSergey Zigachev #define KFD_VI_SDMA_QUEUE_OFFSET 0x80 /* not a register */ 31*b843c749SSergey Zigachev 32*b843c749SSergey Zigachev /* crtc instance offsets */ 33*b843c749SSergey Zigachev #define CRTC0_REGISTER_OFFSET (0x1b9c - 0x1b9c) 34*b843c749SSergey Zigachev #define CRTC1_REGISTER_OFFSET (0x1d9c - 0x1b9c) 35*b843c749SSergey Zigachev #define CRTC2_REGISTER_OFFSET (0x1f9c - 0x1b9c) 36*b843c749SSergey Zigachev #define CRTC3_REGISTER_OFFSET (0x419c - 0x1b9c) 37*b843c749SSergey Zigachev #define CRTC4_REGISTER_OFFSET (0x439c - 0x1b9c) 38*b843c749SSergey Zigachev #define CRTC5_REGISTER_OFFSET (0x459c - 0x1b9c) 39*b843c749SSergey Zigachev #define CRTC6_REGISTER_OFFSET (0x479c - 0x1b9c) 40*b843c749SSergey Zigachev 41*b843c749SSergey Zigachev /* dig instance offsets */ 42*b843c749SSergey Zigachev #define DIG0_REGISTER_OFFSET (0x4a00 - 0x4a00) 43*b843c749SSergey Zigachev #define DIG1_REGISTER_OFFSET (0x4b00 - 0x4a00) 44*b843c749SSergey Zigachev #define DIG2_REGISTER_OFFSET (0x4c00 - 0x4a00) 45*b843c749SSergey Zigachev #define DIG3_REGISTER_OFFSET (0x4d00 - 0x4a00) 46*b843c749SSergey Zigachev #define DIG4_REGISTER_OFFSET (0x4e00 - 0x4a00) 47*b843c749SSergey Zigachev #define DIG5_REGISTER_OFFSET (0x4f00 - 0x4a00) 48*b843c749SSergey Zigachev #define DIG6_REGISTER_OFFSET (0x5400 - 0x4a00) 49*b843c749SSergey Zigachev #define DIG7_REGISTER_OFFSET (0x5600 - 0x4a00) 50*b843c749SSergey Zigachev #define DIG8_REGISTER_OFFSET (0x5700 - 0x4a00) 51*b843c749SSergey Zigachev 52*b843c749SSergey Zigachev /* audio endpt instance offsets */ 53*b843c749SSergey Zigachev #define AUD0_REGISTER_OFFSET (0x17a8 - 0x17a8) 54*b843c749SSergey Zigachev #define AUD1_REGISTER_OFFSET (0x17ac - 0x17a8) 55*b843c749SSergey Zigachev #define AUD2_REGISTER_OFFSET (0x17b0 - 0x17a8) 56*b843c749SSergey Zigachev #define AUD3_REGISTER_OFFSET (0x17b4 - 0x17a8) 57*b843c749SSergey Zigachev #define AUD4_REGISTER_OFFSET (0x17b8 - 0x17a8) 58*b843c749SSergey Zigachev #define AUD5_REGISTER_OFFSET (0x17bc - 0x17a8) 59*b843c749SSergey Zigachev #define AUD6_REGISTER_OFFSET (0x17c0 - 0x17a8) 60*b843c749SSergey Zigachev #define AUD7_REGISTER_OFFSET (0x17c4 - 0x17a8) 61*b843c749SSergey Zigachev 62*b843c749SSergey Zigachev /* hpd instance offsets */ 63*b843c749SSergey Zigachev #define HPD0_REGISTER_OFFSET (0x1898 - 0x1898) 64*b843c749SSergey Zigachev #define HPD1_REGISTER_OFFSET (0x18a0 - 0x1898) 65*b843c749SSergey Zigachev #define HPD2_REGISTER_OFFSET (0x18a8 - 0x1898) 66*b843c749SSergey Zigachev #define HPD3_REGISTER_OFFSET (0x18b0 - 0x1898) 67*b843c749SSergey Zigachev #define HPD4_REGISTER_OFFSET (0x18b8 - 0x1898) 68*b843c749SSergey Zigachev #define HPD5_REGISTER_OFFSET (0x18c0 - 0x1898) 69*b843c749SSergey Zigachev 70*b843c749SSergey Zigachev #define AMDGPU_NUM_OF_VMIDS 8 71*b843c749SSergey Zigachev 72*b843c749SSergey Zigachev #define PIPEID(x) ((x) << 0) 73*b843c749SSergey Zigachev #define MEID(x) ((x) << 2) 74*b843c749SSergey Zigachev #define VMID(x) ((x) << 4) 75*b843c749SSergey Zigachev #define QUEUEID(x) ((x) << 8) 76*b843c749SSergey Zigachev 77*b843c749SSergey Zigachev #define MC_SEQ_MISC0__MT__MASK 0xf0000000 78*b843c749SSergey Zigachev #define MC_SEQ_MISC0__MT__GDDR1 0x10000000 79*b843c749SSergey Zigachev #define MC_SEQ_MISC0__MT__DDR2 0x20000000 80*b843c749SSergey Zigachev #define MC_SEQ_MISC0__MT__GDDR3 0x30000000 81*b843c749SSergey Zigachev #define MC_SEQ_MISC0__MT__GDDR4 0x40000000 82*b843c749SSergey Zigachev #define MC_SEQ_MISC0__MT__GDDR5 0x50000000 83*b843c749SSergey Zigachev #define MC_SEQ_MISC0__MT__HBM 0x60000000 84*b843c749SSergey Zigachev #define MC_SEQ_MISC0__MT__DDR3 0xB0000000 85*b843c749SSergey Zigachev 86*b843c749SSergey Zigachev /* 87*b843c749SSergey Zigachev * PM4 88*b843c749SSergey Zigachev */ 89*b843c749SSergey Zigachev #define PACKET_TYPE0 0 90*b843c749SSergey Zigachev #define PACKET_TYPE1 1 91*b843c749SSergey Zigachev #define PACKET_TYPE2 2 92*b843c749SSergey Zigachev #define PACKET_TYPE3 3 93*b843c749SSergey Zigachev 94*b843c749SSergey Zigachev #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 95*b843c749SSergey Zigachev #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 96*b843c749SSergey Zigachev #define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) 97*b843c749SSergey Zigachev #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 98*b843c749SSergey Zigachev #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 99*b843c749SSergey Zigachev ((reg) & 0xFFFF) | \ 100*b843c749SSergey Zigachev ((n) & 0x3FFF) << 16) 101*b843c749SSergey Zigachev #define CP_PACKET2 0x80000000 102*b843c749SSergey Zigachev #define PACKET2_PAD_SHIFT 0 103*b843c749SSergey Zigachev #define PACKET2_PAD_MASK (0x3fffffff << 0) 104*b843c749SSergey Zigachev 105*b843c749SSergey Zigachev #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 106*b843c749SSergey Zigachev 107*b843c749SSergey Zigachev #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 108*b843c749SSergey Zigachev (((op) & 0xFF) << 8) | \ 109*b843c749SSergey Zigachev ((n) & 0x3FFF) << 16) 110*b843c749SSergey Zigachev 111*b843c749SSergey Zigachev #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 112*b843c749SSergey Zigachev 113*b843c749SSergey Zigachev /* Packet 3 types */ 114*b843c749SSergey Zigachev #define PACKET3_NOP 0x10 115*b843c749SSergey Zigachev #define PACKET3_SET_BASE 0x11 116*b843c749SSergey Zigachev #define PACKET3_BASE_INDEX(x) ((x) << 0) 117*b843c749SSergey Zigachev #define CE_PARTITION_BASE 3 118*b843c749SSergey Zigachev #define PACKET3_CLEAR_STATE 0x12 119*b843c749SSergey Zigachev #define PACKET3_INDEX_BUFFER_SIZE 0x13 120*b843c749SSergey Zigachev #define PACKET3_DISPATCH_DIRECT 0x15 121*b843c749SSergey Zigachev #define PACKET3_DISPATCH_INDIRECT 0x16 122*b843c749SSergey Zigachev #define PACKET3_ATOMIC_GDS 0x1D 123*b843c749SSergey Zigachev #define PACKET3_ATOMIC_MEM 0x1E 124*b843c749SSergey Zigachev #define PACKET3_OCCLUSION_QUERY 0x1F 125*b843c749SSergey Zigachev #define PACKET3_SET_PREDICATION 0x20 126*b843c749SSergey Zigachev #define PACKET3_REG_RMW 0x21 127*b843c749SSergey Zigachev #define PACKET3_COND_EXEC 0x22 128*b843c749SSergey Zigachev #define PACKET3_PRED_EXEC 0x23 129*b843c749SSergey Zigachev #define PACKET3_DRAW_INDIRECT 0x24 130*b843c749SSergey Zigachev #define PACKET3_DRAW_INDEX_INDIRECT 0x25 131*b843c749SSergey Zigachev #define PACKET3_INDEX_BASE 0x26 132*b843c749SSergey Zigachev #define PACKET3_DRAW_INDEX_2 0x27 133*b843c749SSergey Zigachev #define PACKET3_CONTEXT_CONTROL 0x28 134*b843c749SSergey Zigachev #define PACKET3_INDEX_TYPE 0x2A 135*b843c749SSergey Zigachev #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 136*b843c749SSergey Zigachev #define PACKET3_DRAW_INDEX_AUTO 0x2D 137*b843c749SSergey Zigachev #define PACKET3_NUM_INSTANCES 0x2F 138*b843c749SSergey Zigachev #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 139*b843c749SSergey Zigachev #define PACKET3_INDIRECT_BUFFER_CONST 0x33 140*b843c749SSergey Zigachev #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 141*b843c749SSergey Zigachev #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 142*b843c749SSergey Zigachev #define PACKET3_DRAW_PREAMBLE 0x36 143*b843c749SSergey Zigachev #define PACKET3_WRITE_DATA 0x37 144*b843c749SSergey Zigachev #define WRITE_DATA_DST_SEL(x) ((x) << 8) 145*b843c749SSergey Zigachev /* 0 - register 146*b843c749SSergey Zigachev * 1 - memory (sync - via GRBM) 147*b843c749SSergey Zigachev * 2 - gl2 148*b843c749SSergey Zigachev * 3 - gds 149*b843c749SSergey Zigachev * 4 - reserved 150*b843c749SSergey Zigachev * 5 - memory (async - direct) 151*b843c749SSergey Zigachev */ 152*b843c749SSergey Zigachev #define WR_ONE_ADDR (1 << 16) 153*b843c749SSergey Zigachev #define WR_CONFIRM (1 << 20) 154*b843c749SSergey Zigachev #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 155*b843c749SSergey Zigachev /* 0 - LRU 156*b843c749SSergey Zigachev * 1 - Stream 157*b843c749SSergey Zigachev */ 158*b843c749SSergey Zigachev #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 159*b843c749SSergey Zigachev /* 0 - me 160*b843c749SSergey Zigachev * 1 - pfp 161*b843c749SSergey Zigachev * 2 - ce 162*b843c749SSergey Zigachev */ 163*b843c749SSergey Zigachev #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 164*b843c749SSergey Zigachev #define PACKET3_MEM_SEMAPHORE 0x39 165*b843c749SSergey Zigachev # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 166*b843c749SSergey Zigachev # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 167*b843c749SSergey Zigachev # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ 168*b843c749SSergey Zigachev # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 169*b843c749SSergey Zigachev # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 170*b843c749SSergey Zigachev #define PACKET3_WAIT_REG_MEM 0x3C 171*b843c749SSergey Zigachev #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 172*b843c749SSergey Zigachev /* 0 - always 173*b843c749SSergey Zigachev * 1 - < 174*b843c749SSergey Zigachev * 2 - <= 175*b843c749SSergey Zigachev * 3 - == 176*b843c749SSergey Zigachev * 4 - != 177*b843c749SSergey Zigachev * 5 - >= 178*b843c749SSergey Zigachev * 6 - > 179*b843c749SSergey Zigachev */ 180*b843c749SSergey Zigachev #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 181*b843c749SSergey Zigachev /* 0 - reg 182*b843c749SSergey Zigachev * 1 - mem 183*b843c749SSergey Zigachev */ 184*b843c749SSergey Zigachev #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 185*b843c749SSergey Zigachev /* 0 - wait_reg_mem 186*b843c749SSergey Zigachev * 1 - wr_wait_wr_reg 187*b843c749SSergey Zigachev */ 188*b843c749SSergey Zigachev #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 189*b843c749SSergey Zigachev /* 0 - me 190*b843c749SSergey Zigachev * 1 - pfp 191*b843c749SSergey Zigachev */ 192*b843c749SSergey Zigachev #define PACKET3_INDIRECT_BUFFER 0x3F 193*b843c749SSergey Zigachev #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) 194*b843c749SSergey Zigachev #define INDIRECT_BUFFER_VALID (1 << 23) 195*b843c749SSergey Zigachev #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 196*b843c749SSergey Zigachev /* 0 - LRU 197*b843c749SSergey Zigachev * 1 - Stream 198*b843c749SSergey Zigachev * 2 - Bypass 199*b843c749SSergey Zigachev */ 200*b843c749SSergey Zigachev #define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) 201*b843c749SSergey Zigachev #define PACKET3_COPY_DATA 0x40 202*b843c749SSergey Zigachev #define PACKET3_PFP_SYNC_ME 0x42 203*b843c749SSergey Zigachev #define PACKET3_SURFACE_SYNC 0x43 204*b843c749SSergey Zigachev # define PACKET3_DEST_BASE_0_ENA (1 << 0) 205*b843c749SSergey Zigachev # define PACKET3_DEST_BASE_1_ENA (1 << 1) 206*b843c749SSergey Zigachev # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 207*b843c749SSergey Zigachev # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 208*b843c749SSergey Zigachev # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 209*b843c749SSergey Zigachev # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 210*b843c749SSergey Zigachev # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 211*b843c749SSergey Zigachev # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 212*b843c749SSergey Zigachev # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 213*b843c749SSergey Zigachev # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 214*b843c749SSergey Zigachev # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 215*b843c749SSergey Zigachev # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) 216*b843c749SSergey Zigachev # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ 217*b843c749SSergey Zigachev # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ 218*b843c749SSergey Zigachev # define PACKET3_DEST_BASE_2_ENA (1 << 19) 219*b843c749SSergey Zigachev # define PACKET3_DEST_BASE_3_ENA (1 << 21) 220*b843c749SSergey Zigachev # define PACKET3_TCL1_ACTION_ENA (1 << 22) 221*b843c749SSergey Zigachev # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ 222*b843c749SSergey Zigachev # define PACKET3_CB_ACTION_ENA (1 << 25) 223*b843c749SSergey Zigachev # define PACKET3_DB_ACTION_ENA (1 << 26) 224*b843c749SSergey Zigachev # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 225*b843c749SSergey Zigachev # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) 226*b843c749SSergey Zigachev # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 227*b843c749SSergey Zigachev #define PACKET3_COND_WRITE 0x45 228*b843c749SSergey Zigachev #define PACKET3_EVENT_WRITE 0x46 229*b843c749SSergey Zigachev #define EVENT_TYPE(x) ((x) << 0) 230*b843c749SSergey Zigachev #define EVENT_INDEX(x) ((x) << 8) 231*b843c749SSergey Zigachev /* 0 - any non-TS event 232*b843c749SSergey Zigachev * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 233*b843c749SSergey Zigachev * 2 - SAMPLE_PIPELINESTAT 234*b843c749SSergey Zigachev * 3 - SAMPLE_STREAMOUTSTAT* 235*b843c749SSergey Zigachev * 4 - *S_PARTIAL_FLUSH 236*b843c749SSergey Zigachev * 5 - EOP events 237*b843c749SSergey Zigachev * 6 - EOS events 238*b843c749SSergey Zigachev */ 239*b843c749SSergey Zigachev #define PACKET3_EVENT_WRITE_EOP 0x47 240*b843c749SSergey Zigachev #define EOP_TCL1_VOL_ACTION_EN (1 << 12) 241*b843c749SSergey Zigachev #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ 242*b843c749SSergey Zigachev #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ 243*b843c749SSergey Zigachev #define EOP_TCL1_ACTION_EN (1 << 16) 244*b843c749SSergey Zigachev #define EOP_TC_ACTION_EN (1 << 17) /* L2 */ 245*b843c749SSergey Zigachev #define EOP_TCL2_VOLATILE (1 << 24) 246*b843c749SSergey Zigachev #define EOP_CACHE_POLICY(x) ((x) << 25) 247*b843c749SSergey Zigachev /* 0 - LRU 248*b843c749SSergey Zigachev * 1 - Stream 249*b843c749SSergey Zigachev * 2 - Bypass 250*b843c749SSergey Zigachev */ 251*b843c749SSergey Zigachev #define DATA_SEL(x) ((x) << 29) 252*b843c749SSergey Zigachev /* 0 - discard 253*b843c749SSergey Zigachev * 1 - send low 32bit data 254*b843c749SSergey Zigachev * 2 - send 64bit data 255*b843c749SSergey Zigachev * 3 - send 64bit GPU counter value 256*b843c749SSergey Zigachev * 4 - send 64bit sys counter value 257*b843c749SSergey Zigachev */ 258*b843c749SSergey Zigachev #define INT_SEL(x) ((x) << 24) 259*b843c749SSergey Zigachev /* 0 - none 260*b843c749SSergey Zigachev * 1 - interrupt only (DATA_SEL = 0) 261*b843c749SSergey Zigachev * 2 - interrupt when data write is confirmed 262*b843c749SSergey Zigachev */ 263*b843c749SSergey Zigachev #define DST_SEL(x) ((x) << 16) 264*b843c749SSergey Zigachev /* 0 - MC 265*b843c749SSergey Zigachev * 1 - TC/L2 266*b843c749SSergey Zigachev */ 267*b843c749SSergey Zigachev #define PACKET3_EVENT_WRITE_EOS 0x48 268*b843c749SSergey Zigachev #define PACKET3_RELEASE_MEM 0x49 269*b843c749SSergey Zigachev #define PACKET3_PREAMBLE_CNTL 0x4A 270*b843c749SSergey Zigachev # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 271*b843c749SSergey Zigachev # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 272*b843c749SSergey Zigachev #define PACKET3_DMA_DATA 0x50 273*b843c749SSergey Zigachev /* 1. header 274*b843c749SSergey Zigachev * 2. CONTROL 275*b843c749SSergey Zigachev * 3. SRC_ADDR_LO or DATA [31:0] 276*b843c749SSergey Zigachev * 4. SRC_ADDR_HI [31:0] 277*b843c749SSergey Zigachev * 5. DST_ADDR_LO [31:0] 278*b843c749SSergey Zigachev * 6. DST_ADDR_HI [7:0] 279*b843c749SSergey Zigachev * 7. COMMAND [30:21] | BYTE_COUNT [20:0] 280*b843c749SSergey Zigachev */ 281*b843c749SSergey Zigachev /* CONTROL */ 282*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) 283*b843c749SSergey Zigachev /* 0 - ME 284*b843c749SSergey Zigachev * 1 - PFP 285*b843c749SSergey Zigachev */ 286*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) 287*b843c749SSergey Zigachev /* 0 - LRU 288*b843c749SSergey Zigachev * 1 - Stream 289*b843c749SSergey Zigachev * 2 - Bypass 290*b843c749SSergey Zigachev */ 291*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15) 292*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 293*b843c749SSergey Zigachev /* 0 - DST_ADDR using DAS 294*b843c749SSergey Zigachev * 1 - GDS 295*b843c749SSergey Zigachev * 3 - DST_ADDR using L2 296*b843c749SSergey Zigachev */ 297*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) 298*b843c749SSergey Zigachev /* 0 - LRU 299*b843c749SSergey Zigachev * 1 - Stream 300*b843c749SSergey Zigachev * 2 - Bypass 301*b843c749SSergey Zigachev */ 302*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27) 303*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 304*b843c749SSergey Zigachev /* 0 - SRC_ADDR using SAS 305*b843c749SSergey Zigachev * 1 - GDS 306*b843c749SSergey Zigachev * 2 - DATA 307*b843c749SSergey Zigachev * 3 - SRC_ADDR using L2 308*b843c749SSergey Zigachev */ 309*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_CP_SYNC (1 << 31) 310*b843c749SSergey Zigachev /* COMMAND */ 311*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_DIS_WC (1 << 21) 312*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22) 313*b843c749SSergey Zigachev /* 0 - none 314*b843c749SSergey Zigachev * 1 - 8 in 16 315*b843c749SSergey Zigachev * 2 - 8 in 32 316*b843c749SSergey Zigachev * 3 - 8 in 64 317*b843c749SSergey Zigachev */ 318*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24) 319*b843c749SSergey Zigachev /* 0 - none 320*b843c749SSergey Zigachev * 1 - 8 in 16 321*b843c749SSergey Zigachev * 2 - 8 in 32 322*b843c749SSergey Zigachev * 3 - 8 in 64 323*b843c749SSergey Zigachev */ 324*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_CMD_SAS (1 << 26) 325*b843c749SSergey Zigachev /* 0 - memory 326*b843c749SSergey Zigachev * 1 - register 327*b843c749SSergey Zigachev */ 328*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_CMD_DAS (1 << 27) 329*b843c749SSergey Zigachev /* 0 - memory 330*b843c749SSergey Zigachev * 1 - register 331*b843c749SSergey Zigachev */ 332*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 333*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 334*b843c749SSergey Zigachev # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 335*b843c749SSergey Zigachev #define PACKET3_AQUIRE_MEM 0x58 336*b843c749SSergey Zigachev #define PACKET3_REWIND 0x59 337*b843c749SSergey Zigachev #define PACKET3_LOAD_UCONFIG_REG 0x5E 338*b843c749SSergey Zigachev #define PACKET3_LOAD_SH_REG 0x5F 339*b843c749SSergey Zigachev #define PACKET3_LOAD_CONFIG_REG 0x60 340*b843c749SSergey Zigachev #define PACKET3_LOAD_CONTEXT_REG 0x61 341*b843c749SSergey Zigachev #define PACKET3_SET_CONFIG_REG 0x68 342*b843c749SSergey Zigachev #define PACKET3_SET_CONFIG_REG_START 0x00002000 343*b843c749SSergey Zigachev #define PACKET3_SET_CONFIG_REG_END 0x00002c00 344*b843c749SSergey Zigachev #define PACKET3_SET_CONTEXT_REG 0x69 345*b843c749SSergey Zigachev #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 346*b843c749SSergey Zigachev #define PACKET3_SET_CONTEXT_REG_END 0x0000a400 347*b843c749SSergey Zigachev #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 348*b843c749SSergey Zigachev #define PACKET3_SET_SH_REG 0x76 349*b843c749SSergey Zigachev #define PACKET3_SET_SH_REG_START 0x00002c00 350*b843c749SSergey Zigachev #define PACKET3_SET_SH_REG_END 0x00003000 351*b843c749SSergey Zigachev #define PACKET3_SET_SH_REG_OFFSET 0x77 352*b843c749SSergey Zigachev #define PACKET3_SET_QUEUE_REG 0x78 353*b843c749SSergey Zigachev #define PACKET3_SET_UCONFIG_REG 0x79 354*b843c749SSergey Zigachev #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 355*b843c749SSergey Zigachev #define PACKET3_SET_UCONFIG_REG_END 0x0000c400 356*b843c749SSergey Zigachev #define PACKET3_SCRATCH_RAM_WRITE 0x7D 357*b843c749SSergey Zigachev #define PACKET3_SCRATCH_RAM_READ 0x7E 358*b843c749SSergey Zigachev #define PACKET3_LOAD_CONST_RAM 0x80 359*b843c749SSergey Zigachev #define PACKET3_WRITE_CONST_RAM 0x81 360*b843c749SSergey Zigachev #define PACKET3_DUMP_CONST_RAM 0x83 361*b843c749SSergey Zigachev #define PACKET3_INCREMENT_CE_COUNTER 0x84 362*b843c749SSergey Zigachev #define PACKET3_INCREMENT_DE_COUNTER 0x85 363*b843c749SSergey Zigachev #define PACKET3_WAIT_ON_CE_COUNTER 0x86 364*b843c749SSergey Zigachev #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 365*b843c749SSergey Zigachev #define PACKET3_SWITCH_BUFFER 0x8B 366*b843c749SSergey Zigachev #define PACKET3_FRAME_CONTROL 0x90 367*b843c749SSergey Zigachev # define FRAME_CMD(x) ((x) << 28) 368*b843c749SSergey Zigachev /* 369*b843c749SSergey Zigachev * x=0: tmz_begin 370*b843c749SSergey Zigachev * x=1: tmz_end 371*b843c749SSergey Zigachev */ 372*b843c749SSergey Zigachev #define PACKET3_SET_RESOURCES 0xA0 373*b843c749SSergey Zigachev /* 1. header 374*b843c749SSergey Zigachev * 2. CONTROL 375*b843c749SSergey Zigachev * 3. QUEUE_MASK_LO [31:0] 376*b843c749SSergey Zigachev * 4. QUEUE_MASK_HI [31:0] 377*b843c749SSergey Zigachev * 5. GWS_MASK_LO [31:0] 378*b843c749SSergey Zigachev * 6. GWS_MASK_HI [31:0] 379*b843c749SSergey Zigachev * 7. OAC_MASK [15:0] 380*b843c749SSergey Zigachev * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0] 381*b843c749SSergey Zigachev */ 382*b843c749SSergey Zigachev # define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0) 383*b843c749SSergey Zigachev # define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16) 384*b843c749SSergey Zigachev # define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29) 385*b843c749SSergey Zigachev #define PACKET3_MAP_QUEUES 0xA2 386*b843c749SSergey Zigachev /* 1. header 387*b843c749SSergey Zigachev * 2. CONTROL 388*b843c749SSergey Zigachev * 3. CONTROL2 389*b843c749SSergey Zigachev * 4. MQD_ADDR_LO [31:0] 390*b843c749SSergey Zigachev * 5. MQD_ADDR_HI [31:0] 391*b843c749SSergey Zigachev * 6. WPTR_ADDR_LO [31:0] 392*b843c749SSergey Zigachev * 7. WPTR_ADDR_HI [31:0] 393*b843c749SSergey Zigachev */ 394*b843c749SSergey Zigachev /* CONTROL */ 395*b843c749SSergey Zigachev # define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4) 396*b843c749SSergey Zigachev # define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8) 397*b843c749SSergey Zigachev # define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21) 398*b843c749SSergey Zigachev # define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24) 399*b843c749SSergey Zigachev # define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26) 400*b843c749SSergey Zigachev # define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29) 401*b843c749SSergey Zigachev /* CONTROL2 */ 402*b843c749SSergey Zigachev # define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1) 403*b843c749SSergey Zigachev # define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2) 404*b843c749SSergey Zigachev # define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 26) 405*b843c749SSergey Zigachev # define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 29) 406*b843c749SSergey Zigachev # define PACKET3_MAP_QUEUES_ME(x) ((x) << 31) 407*b843c749SSergey Zigachev #define PACKET3_UNMAP_QUEUES 0xA3 408*b843c749SSergey Zigachev /* 1. header 409*b843c749SSergey Zigachev * 2. CONTROL 410*b843c749SSergey Zigachev * 3. CONTROL2 411*b843c749SSergey Zigachev * 4. CONTROL3 412*b843c749SSergey Zigachev * 5. CONTROL4 413*b843c749SSergey Zigachev * 6. CONTROL5 414*b843c749SSergey Zigachev */ 415*b843c749SSergey Zigachev /* CONTROL */ 416*b843c749SSergey Zigachev # define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0) 417*b843c749SSergey Zigachev /* 0 - PREEMPT_QUEUES 418*b843c749SSergey Zigachev * 1 - RESET_QUEUES 419*b843c749SSergey Zigachev * 2 - DISABLE_PROCESS_QUEUES 420*b843c749SSergey Zigachev * 3 - PREEMPT_QUEUES_NO_UNMAP 421*b843c749SSergey Zigachev */ 422*b843c749SSergey Zigachev # define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4) 423*b843c749SSergey Zigachev # define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26) 424*b843c749SSergey Zigachev # define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29) 425*b843c749SSergey Zigachev /* CONTROL2a */ 426*b843c749SSergey Zigachev # define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0) 427*b843c749SSergey Zigachev /* CONTROL2b */ 428*b843c749SSergey Zigachev # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2) 429*b843c749SSergey Zigachev /* CONTROL3a */ 430*b843c749SSergey Zigachev # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2) 431*b843c749SSergey Zigachev /* CONTROL3b */ 432*b843c749SSergey Zigachev # define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0) 433*b843c749SSergey Zigachev /* CONTROL4 */ 434*b843c749SSergey Zigachev # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2) 435*b843c749SSergey Zigachev /* CONTROL5 */ 436*b843c749SSergey Zigachev # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2) 437*b843c749SSergey Zigachev #define PACKET3_QUERY_STATUS 0xA4 438*b843c749SSergey Zigachev /* 1. header 439*b843c749SSergey Zigachev * 2. CONTROL 440*b843c749SSergey Zigachev * 3. CONTROL2 441*b843c749SSergey Zigachev * 4. ADDR_LO [31:0] 442*b843c749SSergey Zigachev * 5. ADDR_HI [31:0] 443*b843c749SSergey Zigachev * 6. DATA_LO [31:0] 444*b843c749SSergey Zigachev * 7. DATA_HI [31:0] 445*b843c749SSergey Zigachev */ 446*b843c749SSergey Zigachev /* CONTROL */ 447*b843c749SSergey Zigachev # define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0) 448*b843c749SSergey Zigachev # define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28) 449*b843c749SSergey Zigachev # define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30) 450*b843c749SSergey Zigachev /* CONTROL2a */ 451*b843c749SSergey Zigachev # define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0) 452*b843c749SSergey Zigachev /* CONTROL2b */ 453*b843c749SSergey Zigachev # define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2) 454*b843c749SSergey Zigachev # define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25) 455*b843c749SSergey Zigachev 456*b843c749SSergey Zigachev 457*b843c749SSergey Zigachev #define VCE_CMD_NO_OP 0x00000000 458*b843c749SSergey Zigachev #define VCE_CMD_END 0x00000001 459*b843c749SSergey Zigachev #define VCE_CMD_IB 0x00000002 460*b843c749SSergey Zigachev #define VCE_CMD_FENCE 0x00000003 461*b843c749SSergey Zigachev #define VCE_CMD_TRAP 0x00000004 462*b843c749SSergey Zigachev #define VCE_CMD_IB_AUTO 0x00000005 463*b843c749SSergey Zigachev #define VCE_CMD_SEMAPHORE 0x00000006 464*b843c749SSergey Zigachev 465*b843c749SSergey Zigachev #define VCE_CMD_IB_VM 0x00000102 466*b843c749SSergey Zigachev #define VCE_CMD_WAIT_GE 0x00000106 467*b843c749SSergey Zigachev #define VCE_CMD_UPDATE_PTB 0x00000107 468*b843c749SSergey Zigachev #define VCE_CMD_FLUSH_TLB 0x00000108 469*b843c749SSergey Zigachev 470*b843c749SSergey Zigachev /* HEVC ENC */ 471*b843c749SSergey Zigachev #define HEVC_ENC_CMD_NO_OP 0x00000000 472*b843c749SSergey Zigachev #define HEVC_ENC_CMD_END 0x00000001 473*b843c749SSergey Zigachev #define HEVC_ENC_CMD_FENCE 0x00000003 474*b843c749SSergey Zigachev #define HEVC_ENC_CMD_TRAP 0x00000004 475*b843c749SSergey Zigachev #define HEVC_ENC_CMD_IB_VM 0x00000102 476*b843c749SSergey Zigachev #define HEVC_ENC_CMD_WAIT_GE 0x00000106 477*b843c749SSergey Zigachev #define HEVC_ENC_CMD_UPDATE_PTB 0x00000107 478*b843c749SSergey Zigachev #define HEVC_ENC_CMD_FLUSH_TLB 0x00000108 479*b843c749SSergey Zigachev 480*b843c749SSergey Zigachev /* mmPA_SC_RASTER_CONFIG mask */ 481*b843c749SSergey Zigachev #define RB_MAP_PKR0(x) ((x) << 0) 482*b843c749SSergey Zigachev #define RB_MAP_PKR0_MASK (0x3 << 0) 483*b843c749SSergey Zigachev #define RB_MAP_PKR1(x) ((x) << 2) 484*b843c749SSergey Zigachev #define RB_MAP_PKR1_MASK (0x3 << 2) 485*b843c749SSergey Zigachev #define RB_XSEL2(x) ((x) << 4) 486*b843c749SSergey Zigachev #define RB_XSEL2_MASK (0x3 << 4) 487*b843c749SSergey Zigachev #define RB_XSEL (1 << 6) 488*b843c749SSergey Zigachev #define RB_YSEL (1 << 7) 489*b843c749SSergey Zigachev #define PKR_MAP(x) ((x) << 8) 490*b843c749SSergey Zigachev #define PKR_MAP_MASK (0x3 << 8) 491*b843c749SSergey Zigachev #define PKR_XSEL(x) ((x) << 10) 492*b843c749SSergey Zigachev #define PKR_XSEL_MASK (0x3 << 10) 493*b843c749SSergey Zigachev #define PKR_YSEL(x) ((x) << 12) 494*b843c749SSergey Zigachev #define PKR_YSEL_MASK (0x3 << 12) 495*b843c749SSergey Zigachev #define SC_MAP(x) ((x) << 16) 496*b843c749SSergey Zigachev #define SC_MAP_MASK (0x3 << 16) 497*b843c749SSergey Zigachev #define SC_XSEL(x) ((x) << 18) 498*b843c749SSergey Zigachev #define SC_XSEL_MASK (0x3 << 18) 499*b843c749SSergey Zigachev #define SC_YSEL(x) ((x) << 20) 500*b843c749SSergey Zigachev #define SC_YSEL_MASK (0x3 << 20) 501*b843c749SSergey Zigachev #define SE_MAP(x) ((x) << 24) 502*b843c749SSergey Zigachev #define SE_MAP_MASK (0x3 << 24) 503*b843c749SSergey Zigachev #define SE_XSEL(x) ((x) << 26) 504*b843c749SSergey Zigachev #define SE_XSEL_MASK (0x3 << 26) 505*b843c749SSergey Zigachev #define SE_YSEL(x) ((x) << 28) 506*b843c749SSergey Zigachev #define SE_YSEL_MASK (0x3 << 28) 507*b843c749SSergey Zigachev 508*b843c749SSergey Zigachev /* mmPA_SC_RASTER_CONFIG_1 mask */ 509*b843c749SSergey Zigachev #define SE_PAIR_MAP(x) ((x) << 0) 510*b843c749SSergey Zigachev #define SE_PAIR_MAP_MASK (0x3 << 0) 511*b843c749SSergey Zigachev #define SE_PAIR_XSEL(x) ((x) << 2) 512*b843c749SSergey Zigachev #define SE_PAIR_XSEL_MASK (0x3 << 2) 513*b843c749SSergey Zigachev #define SE_PAIR_YSEL(x) ((x) << 4) 514*b843c749SSergey Zigachev #define SE_PAIR_YSEL_MASK (0x3 << 4) 515*b843c749SSergey Zigachev 516*b843c749SSergey Zigachev #endif 517