1b843c749SSergey Zigachev /* 2b843c749SSergey Zigachev * Copyright 2015 Advanced Micro Devices, Inc. 3b843c749SSergey Zigachev * 4b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10b843c749SSergey Zigachev * 11b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13b843c749SSergey Zigachev * 14b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21b843c749SSergey Zigachev * 22b843c749SSergey Zigachev * Authors: AMD 23b843c749SSergey Zigachev * 24b843c749SSergey Zigachev */ 25b843c749SSergey Zigachev 26b843c749SSergey Zigachev #ifndef __AMDGPU_DM_H__ 27b843c749SSergey Zigachev #define __AMDGPU_DM_H__ 28b843c749SSergey Zigachev 29b843c749SSergey Zigachev #include <drm/drmP.h> 30b843c749SSergey Zigachev #include <drm/drm_atomic.h> 31b843c749SSergey Zigachev 32b843c749SSergey Zigachev /* 33b843c749SSergey Zigachev * This file contains the definition for amdgpu_display_manager 34b843c749SSergey Zigachev * and its API for amdgpu driver's use. 35b843c749SSergey Zigachev * This component provides all the display related functionality 36b843c749SSergey Zigachev * and this is the only component that calls DAL API. 37b843c749SSergey Zigachev * The API contained here intended for amdgpu driver use. 38b843c749SSergey Zigachev * The API that is called directly from KMS framework is located 39b843c749SSergey Zigachev * in amdgpu_dm_kms.h file 40b843c749SSergey Zigachev */ 41b843c749SSergey Zigachev 42b843c749SSergey Zigachev #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 43b843c749SSergey Zigachev /* 44b843c749SSergey Zigachev #include "include/amdgpu_dal_power_if.h" 45b843c749SSergey Zigachev #include "amdgpu_dm_irq.h" 46b843c749SSergey Zigachev */ 47b843c749SSergey Zigachev 48b843c749SSergey Zigachev #include "irq_types.h" 49b843c749SSergey Zigachev #include "signal_types.h" 50b843c749SSergey Zigachev 51b843c749SSergey Zigachev /* Forward declarations */ 52b843c749SSergey Zigachev struct amdgpu_device; 53b843c749SSergey Zigachev struct drm_device; 54b843c749SSergey Zigachev struct amdgpu_dm_irq_handler_data; 55b843c749SSergey Zigachev struct dc; 56b843c749SSergey Zigachev 57b843c749SSergey Zigachev struct amdgpu_dm_prev_state { 58b843c749SSergey Zigachev struct drm_framebuffer *fb; 59b843c749SSergey Zigachev int32_t x; 60b843c749SSergey Zigachev int32_t y; 61b843c749SSergey Zigachev struct drm_display_mode mode; 62b843c749SSergey Zigachev }; 63b843c749SSergey Zigachev 64b843c749SSergey Zigachev struct common_irq_params { 65b843c749SSergey Zigachev struct amdgpu_device *adev; 66b843c749SSergey Zigachev enum dc_irq_source irq_src; 67b843c749SSergey Zigachev }; 68b843c749SSergey Zigachev 69b843c749SSergey Zigachev struct irq_list_head { 70b843c749SSergey Zigachev struct list_head head; 71b843c749SSergey Zigachev /* In case this interrupt needs post-processing, 'work' will be queued*/ 72b843c749SSergey Zigachev struct work_struct work; 73b843c749SSergey Zigachev }; 74b843c749SSergey Zigachev 75b843c749SSergey Zigachev struct dm_comressor_info { 76b843c749SSergey Zigachev void *cpu_addr; 77b843c749SSergey Zigachev struct amdgpu_bo *bo_ptr; 78b843c749SSergey Zigachev uint64_t gpu_addr; 79b843c749SSergey Zigachev }; 80b843c749SSergey Zigachev 81b843c749SSergey Zigachev 82b843c749SSergey Zigachev struct amdgpu_display_manager { 83b843c749SSergey Zigachev struct dal *dal; 84b843c749SSergey Zigachev struct dc *dc; 85b843c749SSergey Zigachev struct cgs_device *cgs_device; 86b843c749SSergey Zigachev 87b843c749SSergey Zigachev struct amdgpu_device *adev; /*AMD base driver*/ 88b843c749SSergey Zigachev struct drm_device *ddev; /*DRM base driver*/ 89b843c749SSergey Zigachev u16 display_indexes_num; 90b843c749SSergey Zigachev 91b843c749SSergey Zigachev struct amdgpu_dm_prev_state prev_state; 92b843c749SSergey Zigachev 93b843c749SSergey Zigachev /* 94b843c749SSergey Zigachev * 'irq_source_handler_table' holds a list of handlers 95b843c749SSergey Zigachev * per (DAL) IRQ source. 96b843c749SSergey Zigachev * 97b843c749SSergey Zigachev * Each IRQ source may need to be handled at different contexts. 98b843c749SSergey Zigachev * By 'context' we mean, for example: 99b843c749SSergey Zigachev * - The ISR context, which is the direct interrupt handler. 100b843c749SSergey Zigachev * - The 'deferred' context - this is the post-processing of the 101b843c749SSergey Zigachev * interrupt, but at a lower priority. 102b843c749SSergey Zigachev * 103b843c749SSergey Zigachev * Note that handlers are called in the same order as they were 104b843c749SSergey Zigachev * registered (FIFO). 105b843c749SSergey Zigachev */ 106b843c749SSergey Zigachev struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 107b843c749SSergey Zigachev struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 108b843c749SSergey Zigachev 109b843c749SSergey Zigachev struct common_irq_params 110b843c749SSergey Zigachev pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 111b843c749SSergey Zigachev 112b843c749SSergey Zigachev struct common_irq_params 113b843c749SSergey Zigachev vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 114b843c749SSergey Zigachev 115b843c749SSergey Zigachev /* this spin lock synchronizes access to 'irq_handler_list_table' */ 116b843c749SSergey Zigachev spinlock_t irq_handler_list_table_lock; 117b843c749SSergey Zigachev 118b843c749SSergey Zigachev struct backlight_device *backlight_dev; 119b843c749SSergey Zigachev 120b843c749SSergey Zigachev const struct dc_link *backlight_link; 121b843c749SSergey Zigachev 122b843c749SSergey Zigachev struct work_struct mst_hotplug_work; 123b843c749SSergey Zigachev 124b843c749SSergey Zigachev struct mod_freesync *freesync_module; 125b843c749SSergey Zigachev 126b843c749SSergey Zigachev /** 127b843c749SSergey Zigachev * Caches device atomic state for suspend/resume 128b843c749SSergey Zigachev */ 129b843c749SSergey Zigachev struct drm_atomic_state *cached_state; 130b843c749SSergey Zigachev 131b843c749SSergey Zigachev struct dm_comressor_info compressor; 132b843c749SSergey Zigachev }; 133b843c749SSergey Zigachev 134b843c749SSergey Zigachev struct amdgpu_dm_connector { 135b843c749SSergey Zigachev 136b843c749SSergey Zigachev struct drm_connector base; 137b843c749SSergey Zigachev uint32_t connector_id; 138b843c749SSergey Zigachev 139b843c749SSergey Zigachev /* we need to mind the EDID between detect 140b843c749SSergey Zigachev and get modes due to analog/digital/tvencoder */ 141b843c749SSergey Zigachev struct edid *edid; 142b843c749SSergey Zigachev 143b843c749SSergey Zigachev /* shared with amdgpu */ 144b843c749SSergey Zigachev struct amdgpu_hpd hpd; 145b843c749SSergey Zigachev 146b843c749SSergey Zigachev /* number of modes generated from EDID at 'dc_sink' */ 147b843c749SSergey Zigachev int num_modes; 148b843c749SSergey Zigachev 149b843c749SSergey Zigachev /* The 'old' sink - before an HPD. 150b843c749SSergey Zigachev * The 'current' sink is in dc_link->sink. */ 151b843c749SSergey Zigachev struct dc_sink *dc_sink; 152b843c749SSergey Zigachev struct dc_link *dc_link; 153b843c749SSergey Zigachev struct dc_sink *dc_em_sink; 154b843c749SSergey Zigachev 155b843c749SSergey Zigachev /* DM only */ 156b843c749SSergey Zigachev struct drm_dp_mst_topology_mgr mst_mgr; 157b843c749SSergey Zigachev struct amdgpu_dm_dp_aux dm_dp_aux; 158b843c749SSergey Zigachev struct drm_dp_mst_port *port; 159b843c749SSergey Zigachev struct amdgpu_dm_connector *mst_port; 160b843c749SSergey Zigachev struct amdgpu_encoder *mst_encoder; 161b843c749SSergey Zigachev 162b843c749SSergey Zigachev /* TODO see if we can merge with ddc_bus or make a dm_connector */ 163b843c749SSergey Zigachev struct amdgpu_i2c_adapter *i2c; 164b843c749SSergey Zigachev 165b843c749SSergey Zigachev /* Monitor range limits */ 166b843c749SSergey Zigachev int min_vfreq ; 167b843c749SSergey Zigachev int max_vfreq ; 168b843c749SSergey Zigachev int pixel_clock_mhz; 169b843c749SSergey Zigachev 170b843c749SSergey Zigachev /*freesync caps*/ 171b843c749SSergey Zigachev struct mod_freesync_caps caps; 172b843c749SSergey Zigachev 173*78973132SSergey Zigachev struct lock hpd_lock; 174b843c749SSergey Zigachev 175b843c749SSergey Zigachev bool fake_enable; 176b843c749SSergey Zigachev }; 177b843c749SSergey Zigachev 178b843c749SSergey Zigachev #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 179b843c749SSergey Zigachev 180b843c749SSergey Zigachev extern const struct amdgpu_ip_block_version dm_ip_block; 181b843c749SSergey Zigachev 182b843c749SSergey Zigachev struct amdgpu_framebuffer; 183b843c749SSergey Zigachev struct amdgpu_display_manager; 184b843c749SSergey Zigachev struct dc_validation_set; 185b843c749SSergey Zigachev struct dc_plane_state; 186b843c749SSergey Zigachev 187b843c749SSergey Zigachev struct dm_plane_state { 188b843c749SSergey Zigachev struct drm_plane_state base; 189b843c749SSergey Zigachev struct dc_plane_state *dc_state; 190b843c749SSergey Zigachev }; 191b843c749SSergey Zigachev 192b843c749SSergey Zigachev struct dm_crtc_state { 193b843c749SSergey Zigachev struct drm_crtc_state base; 194b843c749SSergey Zigachev struct dc_stream_state *stream; 195b843c749SSergey Zigachev 196b843c749SSergey Zigachev int crc_skip_count; 197b843c749SSergey Zigachev bool crc_enabled; 198b843c749SSergey Zigachev }; 199b843c749SSergey Zigachev 200b843c749SSergey Zigachev #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 201b843c749SSergey Zigachev 202b843c749SSergey Zigachev struct dm_atomic_state { 203b843c749SSergey Zigachev struct drm_atomic_state base; 204b843c749SSergey Zigachev 205b843c749SSergey Zigachev struct dc_state *context; 206b843c749SSergey Zigachev }; 207b843c749SSergey Zigachev 208b843c749SSergey Zigachev #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 209b843c749SSergey Zigachev 210b843c749SSergey Zigachev struct dm_connector_state { 211b843c749SSergey Zigachev struct drm_connector_state base; 212b843c749SSergey Zigachev 213b843c749SSergey Zigachev enum amdgpu_rmx_type scaling; 214b843c749SSergey Zigachev uint8_t underscan_vborder; 215b843c749SSergey Zigachev uint8_t underscan_hborder; 216b843c749SSergey Zigachev uint8_t max_bpc; 217b843c749SSergey Zigachev bool underscan_enable; 218b843c749SSergey Zigachev struct mod_freesync_user_enable user_enable; 219b843c749SSergey Zigachev bool freesync_capable; 220b843c749SSergey Zigachev }; 221b843c749SSergey Zigachev 222b843c749SSergey Zigachev #define to_dm_connector_state(x)\ 223b843c749SSergey Zigachev container_of((x), struct dm_connector_state, base) 224b843c749SSergey Zigachev 225b843c749SSergey Zigachev void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 226b843c749SSergey Zigachev struct drm_connector_state * 227b843c749SSergey Zigachev amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 228b843c749SSergey Zigachev int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 229b843c749SSergey Zigachev struct drm_connector_state *state, 230b843c749SSergey Zigachev struct drm_property *property, 231b843c749SSergey Zigachev uint64_t val); 232b843c749SSergey Zigachev 233b843c749SSergey Zigachev int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 234b843c749SSergey Zigachev const struct drm_connector_state *state, 235b843c749SSergey Zigachev struct drm_property *property, 236b843c749SSergey Zigachev uint64_t *val); 237b843c749SSergey Zigachev 238b843c749SSergey Zigachev int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 239b843c749SSergey Zigachev 240b843c749SSergey Zigachev void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 241b843c749SSergey Zigachev struct amdgpu_dm_connector *aconnector, 242b843c749SSergey Zigachev int connector_type, 243b843c749SSergey Zigachev struct dc_link *link, 244b843c749SSergey Zigachev int link_index); 245b843c749SSergey Zigachev 246b843c749SSergey Zigachev enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 247b843c749SSergey Zigachev struct drm_display_mode *mode); 248b843c749SSergey Zigachev 249b843c749SSergey Zigachev void dm_restore_drm_connector_state(struct drm_device *dev, 250b843c749SSergey Zigachev struct drm_connector *connector); 251b843c749SSergey Zigachev 252b843c749SSergey Zigachev void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector, 253b843c749SSergey Zigachev struct edid *edid); 254b843c749SSergey Zigachev 255b843c749SSergey Zigachev void 256b843c749SSergey Zigachev amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector); 257b843c749SSergey Zigachev 258b843c749SSergey Zigachev /* amdgpu_dm_crc.c */ 259b843c749SSergey Zigachev #ifdef CONFIG_DEBUG_FS 260b843c749SSergey Zigachev int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name, 261b843c749SSergey Zigachev size_t *values_cnt); 262b843c749SSergey Zigachev void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc); 263b843c749SSergey Zigachev #else 264b843c749SSergey Zigachev #define amdgpu_dm_crtc_set_crc_source NULL 265b843c749SSergey Zigachev #define amdgpu_dm_crtc_handle_crc_irq(x) 266b843c749SSergey Zigachev #endif 267b843c749SSergey Zigachev 268b843c749SSergey Zigachev #define MAX_COLOR_LUT_ENTRIES 4096 269b843c749SSergey Zigachev /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 270b843c749SSergey Zigachev #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 271b843c749SSergey Zigachev 272b843c749SSergey Zigachev void amdgpu_dm_init_color_mod(void); 273b843c749SSergey Zigachev int amdgpu_dm_set_degamma_lut(struct drm_crtc_state *crtc_state, 274b843c749SSergey Zigachev struct dc_plane_state *dc_plane_state); 275b843c749SSergey Zigachev void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc); 276b843c749SSergey Zigachev int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc); 277b843c749SSergey Zigachev 278b843c749SSergey Zigachev extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 279b843c749SSergey Zigachev 280b843c749SSergey Zigachev #endif /* __AMDGPU_DM_H__ */ 281