1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string.h> 27 #include <linux/acpi.h> 28 #if 0 29 #include <linux/version.h> 30 #endif 31 #include <linux/i2c.h> 32 33 #include <drm/drmP.h> 34 #include <drm/drm_crtc_helper.h> 35 #include <drm/amdgpu_drm.h> 36 #include <drm/drm_edid.h> 37 38 #include "dm_services.h" 39 #include "amdgpu.h" 40 #include "dc.h" 41 #include "amdgpu_dm.h" 42 #include "amdgpu_dm_irq.h" 43 44 #include "dm_helpers.h" 45 46 /* dm_helpers_parse_edid_caps 47 * 48 * Parse edid caps 49 * 50 * @edid: [in] pointer to edid 51 * edid_caps: [in] pointer to edid caps 52 * @return 53 * void 54 * */ 55 enum dc_edid_status dm_helpers_parse_edid_caps( 56 struct dc_context *ctx, 57 const struct dc_edid *edid, 58 struct dc_edid_caps *edid_caps) 59 { 60 struct edid *edid_buf = (struct edid *) edid->raw_edid; 61 struct cea_sad *sads; 62 int sad_count = -1; 63 int sadb_count = -1; 64 int i = 0; 65 int j = 0; 66 uint8_t *sadb = NULL; 67 68 enum dc_edid_status result = EDID_OK; 69 70 if (!edid_caps || !edid) 71 return EDID_BAD_INPUT; 72 73 if (!drm_edid_is_valid(edid_buf)) 74 result = EDID_BAD_CHECKSUM; 75 76 edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] | 77 ((uint16_t) edid_buf->mfg_id[1])<<8; 78 edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] | 79 ((uint16_t) edid_buf->prod_code[1])<<8; 80 edid_caps->serial_number = edid_buf->serial; 81 edid_caps->manufacture_week = edid_buf->mfg_week; 82 edid_caps->manufacture_year = edid_buf->mfg_year; 83 84 /* One of the four detailed_timings stores the monitor name. It's 85 * stored in an array of length 13. */ 86 for (i = 0; i < 4; i++) { 87 if (edid_buf->detailed_timings[i].data.other_data.type == 0xfc) { 88 while (j < 13 && edid_buf->detailed_timings[i].data.other_data.data.str.str[j]) { 89 if (edid_buf->detailed_timings[i].data.other_data.data.str.str[j] == '\n') 90 break; 91 92 edid_caps->display_name[j] = 93 edid_buf->detailed_timings[i].data.other_data.data.str.str[j]; 94 j++; 95 } 96 } 97 } 98 99 edid_caps->edid_hdmi = drm_detect_hdmi_monitor( 100 (struct edid *) edid->raw_edid); 101 102 sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads); 103 if (sad_count <= 0) { 104 DRM_INFO("SADs count is: %d, don't need to read it\n", 105 sad_count); 106 return result; 107 } 108 109 edid_caps->audio_mode_count = sad_count < DC_MAX_AUDIO_DESC_COUNT ? sad_count : DC_MAX_AUDIO_DESC_COUNT; 110 for (i = 0; i < edid_caps->audio_mode_count; ++i) { 111 struct cea_sad *sad = &sads[i]; 112 113 edid_caps->audio_modes[i].format_code = sad->format; 114 edid_caps->audio_modes[i].channel_count = sad->channels + 1; 115 edid_caps->audio_modes[i].sample_rate = sad->freq; 116 edid_caps->audio_modes[i].sample_size = sad->byte2; 117 } 118 119 sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb); 120 121 if (sadb_count < 0) { 122 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count); 123 sadb_count = 0; 124 } 125 126 if (sadb_count) 127 edid_caps->speaker_flags = sadb[0]; 128 else 129 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION; 130 131 kfree(sads); 132 kfree(sadb); 133 134 return result; 135 } 136 137 static void get_payload_table( 138 struct amdgpu_dm_connector *aconnector, 139 struct dp_mst_stream_allocation_table *proposed_table) 140 { 141 int i; 142 struct drm_dp_mst_topology_mgr *mst_mgr = 143 &aconnector->mst_port->mst_mgr; 144 145 mutex_lock(&mst_mgr->payload_lock); 146 147 proposed_table->stream_count = 0; 148 149 /* number of active streams */ 150 for (i = 0; i < mst_mgr->max_payloads; i++) { 151 if (mst_mgr->payloads[i].num_slots == 0) 152 break; /* end of vcp_id table */ 153 154 ASSERT(mst_mgr->payloads[i].payload_state != 155 DP_PAYLOAD_DELETE_LOCAL); 156 157 if (mst_mgr->payloads[i].payload_state == DP_PAYLOAD_LOCAL || 158 mst_mgr->payloads[i].payload_state == 159 DP_PAYLOAD_REMOTE) { 160 161 struct dp_mst_stream_allocation *sa = 162 &proposed_table->stream_allocations[ 163 proposed_table->stream_count]; 164 165 sa->slot_count = mst_mgr->payloads[i].num_slots; 166 sa->vcp_id = mst_mgr->proposed_vcpis[i]->vcpi; 167 proposed_table->stream_count++; 168 } 169 } 170 171 mutex_unlock(&mst_mgr->payload_lock); 172 } 173 174 void dm_helpers_dp_update_branch_info( 175 struct dc_context *ctx, 176 const struct dc_link *link) 177 {} 178 179 /* 180 * Writes payload allocation table in immediate downstream device. 181 */ 182 bool dm_helpers_dp_mst_write_payload_allocation_table( 183 struct dc_context *ctx, 184 const struct dc_stream_state *stream, 185 struct dp_mst_stream_allocation_table *proposed_table, 186 bool enable) 187 { 188 struct amdgpu_dm_connector *aconnector; 189 struct drm_dp_mst_topology_mgr *mst_mgr; 190 struct drm_dp_mst_port *mst_port; 191 int slots = 0; 192 bool ret; 193 int clock; 194 int bpp = 0; 195 int pbn = 0; 196 197 aconnector = stream->sink->priv; 198 199 if (!aconnector || !aconnector->mst_port) 200 return false; 201 202 mst_mgr = &aconnector->mst_port->mst_mgr; 203 204 if (!mst_mgr->mst_state) 205 return false; 206 207 mst_port = aconnector->port; 208 209 if (enable) { 210 clock = stream->timing.pix_clk_khz; 211 212 switch (stream->timing.display_color_depth) { 213 214 case COLOR_DEPTH_666: 215 bpp = 6; 216 break; 217 case COLOR_DEPTH_888: 218 bpp = 8; 219 break; 220 case COLOR_DEPTH_101010: 221 bpp = 10; 222 break; 223 case COLOR_DEPTH_121212: 224 bpp = 12; 225 break; 226 case COLOR_DEPTH_141414: 227 bpp = 14; 228 break; 229 case COLOR_DEPTH_161616: 230 bpp = 16; 231 break; 232 default: 233 ASSERT(bpp != 0); 234 break; 235 } 236 237 bpp = bpp * 3; 238 239 /* TODO need to know link rate */ 240 241 pbn = drm_dp_calc_pbn_mode(clock, bpp); 242 243 slots = drm_dp_find_vcpi_slots(mst_mgr, pbn); 244 ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, slots); 245 246 if (!ret) 247 return false; 248 249 } else { 250 drm_dp_mst_reset_vcpi_slots(mst_mgr, mst_port); 251 } 252 253 /* It's OK for this to fail */ 254 drm_dp_update_payload_part1(mst_mgr); 255 256 /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or 257 * AUX message. The sequence is slot 1-63 allocated sequence for each 258 * stream. AMD ASIC stream slot allocation should follow the same 259 * sequence. copy DRM MST allocation to dc */ 260 261 get_payload_table(aconnector, proposed_table); 262 263 return true; 264 } 265 266 267 /* 268 * Clear payload allocation table before enable MST DP link. 269 */ 270 void dm_helpers_dp_mst_clear_payload_allocation_table( 271 struct dc_context *ctx, 272 const struct dc_link *link) 273 {} 274 275 /* 276 * Polls for ACT (allocation change trigger) handled and sends 277 * ALLOCATE_PAYLOAD message. 278 */ 279 bool dm_helpers_dp_mst_poll_for_allocation_change_trigger( 280 struct dc_context *ctx, 281 const struct dc_stream_state *stream) 282 { 283 struct amdgpu_dm_connector *aconnector; 284 struct drm_dp_mst_topology_mgr *mst_mgr; 285 int ret; 286 287 aconnector = stream->sink->priv; 288 289 if (!aconnector || !aconnector->mst_port) 290 return false; 291 292 mst_mgr = &aconnector->mst_port->mst_mgr; 293 294 if (!mst_mgr->mst_state) 295 return false; 296 297 ret = drm_dp_check_act_status(mst_mgr); 298 299 if (ret) 300 return false; 301 302 return true; 303 } 304 305 bool dm_helpers_dp_mst_send_payload_allocation( 306 struct dc_context *ctx, 307 const struct dc_stream_state *stream, 308 bool enable) 309 { 310 struct amdgpu_dm_connector *aconnector; 311 struct drm_dp_mst_topology_mgr *mst_mgr; 312 struct drm_dp_mst_port *mst_port; 313 314 aconnector = stream->sink->priv; 315 316 if (!aconnector || !aconnector->mst_port) 317 return false; 318 319 mst_port = aconnector->port; 320 321 mst_mgr = &aconnector->mst_port->mst_mgr; 322 323 if (!mst_mgr->mst_state) 324 return false; 325 326 /* It's OK for this to fail */ 327 drm_dp_update_payload_part2(mst_mgr); 328 329 if (!enable) 330 drm_dp_mst_deallocate_vcpi(mst_mgr, mst_port); 331 332 return true; 333 } 334 335 void dm_dtn_log_begin(struct dc_context *ctx) 336 {} 337 338 void dm_dtn_log_append_v(struct dc_context *ctx, 339 const char *pMsg, ...) 340 {} 341 342 void dm_dtn_log_end(struct dc_context *ctx) 343 {} 344 345 bool dm_helpers_dp_mst_start_top_mgr( 346 struct dc_context *ctx, 347 const struct dc_link *link, 348 bool boot) 349 { 350 struct amdgpu_dm_connector *aconnector = link->priv; 351 352 if (!aconnector) { 353 DRM_ERROR("Failed to found connector for link!"); 354 return false; 355 } 356 357 if (boot) { 358 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n", 359 aconnector, aconnector->base.base.id); 360 return true; 361 } 362 363 DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n", 364 aconnector, aconnector->base.base.id); 365 366 return (drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true) == 0); 367 } 368 369 void dm_helpers_dp_mst_stop_top_mgr( 370 struct dc_context *ctx, 371 const struct dc_link *link) 372 { 373 struct amdgpu_dm_connector *aconnector = link->priv; 374 375 if (!aconnector) { 376 DRM_ERROR("Failed to found connector for link!"); 377 return; 378 } 379 380 DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n", 381 aconnector, aconnector->base.base.id); 382 383 if (aconnector->mst_mgr.mst_state == true) 384 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false); 385 } 386 387 bool dm_helpers_dp_read_dpcd( 388 struct dc_context *ctx, 389 const struct dc_link *link, 390 uint32_t address, 391 uint8_t *data, 392 uint32_t size) 393 { 394 395 struct amdgpu_dm_connector *aconnector = link->priv; 396 397 if (!aconnector) { 398 DRM_ERROR("Failed to found connector for link!"); 399 return false; 400 } 401 402 return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address, 403 data, size) > 0; 404 } 405 406 bool dm_helpers_dp_write_dpcd( 407 struct dc_context *ctx, 408 const struct dc_link *link, 409 uint32_t address, 410 const uint8_t *data, 411 uint32_t size) 412 { 413 struct amdgpu_dm_connector *aconnector = link->priv; 414 415 if (!aconnector) { 416 DRM_ERROR("Failed to found connector for link!"); 417 return false; 418 } 419 420 return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux, 421 address, (uint8_t *)data, size) > 0; 422 } 423 424 bool dm_helpers_submit_i2c( 425 struct dc_context *ctx, 426 const struct dc_link *link, 427 struct i2c_command *cmd) 428 { 429 struct amdgpu_dm_connector *aconnector = link->priv; 430 struct i2c_msg *msgs; 431 int i = 0; 432 int num = cmd->number_of_payloads; 433 bool result; 434 435 if (!aconnector) { 436 DRM_ERROR("Failed to found connector for link!"); 437 return false; 438 } 439 440 msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL); 441 442 if (!msgs) 443 return false; 444 445 for (i = 0; i < num; i++) { 446 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD; 447 msgs[i].addr = cmd->payloads[i].address; 448 msgs[i].len = cmd->payloads[i].length; 449 msgs[i].buf = cmd->payloads[i].data; 450 } 451 452 result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num; 453 454 kfree(msgs); 455 456 return result; 457 } 458 459 bool dm_helpers_is_dp_sink_present(struct dc_link *link) 460 { 461 bool dp_sink_present; 462 struct amdgpu_dm_connector *aconnector = link->priv; 463 464 if (!aconnector) { 465 BUG_ON("Failed to found connector for link!"); 466 return true; 467 } 468 469 mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex); 470 dp_sink_present = dc_link_is_dp_sink_present(link); 471 mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex); 472 return dp_sink_present; 473 } 474 475 enum dc_edid_status dm_helpers_read_local_edid( 476 struct dc_context *ctx, 477 struct dc_link *link, 478 struct dc_sink *sink) 479 { 480 struct amdgpu_dm_connector *aconnector = link->priv; 481 struct i2c_adapter *ddc; 482 int retry = 3; 483 enum dc_edid_status edid_status; 484 struct edid *edid; 485 486 if (link->aux_mode) 487 ddc = &aconnector->dm_dp_aux.aux.ddc; 488 else 489 ddc = &aconnector->i2c->base; 490 491 /* some dongles read edid incorrectly the first time, 492 * do check sum and retry to make sure read correct edid. 493 */ 494 do { 495 496 edid = drm_get_edid(&aconnector->base, ddc); 497 498 if (!edid) 499 return EDID_NO_RESPONSE; 500 501 sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1); 502 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length); 503 504 /* We don't need the original edid anymore */ 505 kfree(edid); 506 507 edid_status = dm_helpers_parse_edid_caps( 508 ctx, 509 &sink->dc_edid, 510 &sink->edid_caps); 511 512 } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0); 513 514 if (edid_status != EDID_OK) 515 DRM_ERROR("EDID err: %d, on connector: %s", 516 edid_status, 517 aconnector->base.name); 518 if (link->aux_mode) { 519 union test_request test_request = { {0} }; 520 union test_response test_response = { {0} }; 521 522 dm_helpers_dp_read_dpcd(ctx, 523 link, 524 DP_TEST_REQUEST, 525 &test_request.raw, 526 sizeof(union test_request)); 527 528 if (!test_request.bits.EDID_READ) 529 return edid_status; 530 531 test_response.bits.EDID_CHECKSUM_WRITE = 1; 532 533 dm_helpers_dp_write_dpcd(ctx, 534 link, 535 DP_TEST_EDID_CHECKSUM, 536 &sink->dc_edid.raw_edid[sink->dc_edid.length-1], 537 1); 538 539 dm_helpers_dp_write_dpcd(ctx, 540 link, 541 DP_TEST_RESPONSE, 542 &test_response.raw, 543 sizeof(test_response)); 544 545 } 546 547 return edid_status; 548 } 549 550 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks) 551 { 552 /* TODO: something */ 553 } 554