1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "dcn_calcs.h" 28 #include "dcn_calc_auto.h" 29 #include "dc.h" 30 #include "dal_asic_id.h" 31 32 #include "resource.h" 33 #include "dcn10/dcn10_resource.h" 34 #include "dcn10/dcn10_hubbub.h" 35 36 #include "dcn_calc_math.h" 37 38 39 #define DC_LOGGER \ 40 dc->ctx->logger 41 /* 42 * NOTE: 43 * This file is gcc-parseable HW gospel, coming straight from HW engineers. 44 * 45 * It doesn't adhere to Linux kernel style and sometimes will do things in odd 46 * ways. Unless there is something clearly wrong with it the code should 47 * remain as-is as it provides us with a guarantee from HW that it is correct. 48 */ 49 50 /* Defaults from spreadsheet rev#247 */ 51 const struct dcn_soc_bounding_box dcn10_soc_defaults = { 52 /* latencies */ 53 .sr_exit_time = 17, /*us*/ 54 .sr_enter_plus_exit_time = 19, /*us*/ 55 .urgent_latency = 4, /*us*/ 56 .dram_clock_change_latency = 17, /*us*/ 57 .write_back_latency = 12, /*us*/ 58 .percent_of_ideal_drambw_received_after_urg_latency = 80, /*%*/ 59 60 /* below default clocks derived from STA target base on 61 * slow-slow corner + 10% margin with voltages aligned to FCLK. 62 * 63 * Use these value if fused value doesn't make sense as earlier 64 * part don't have correct value fused */ 65 /* default DCF CLK DPM on RV*/ 66 .dcfclkv_max0p9 = 655, /* MHz, = 3600/5.5 */ 67 .dcfclkv_nom0p8 = 626, /* MHz, = 3600/5.75 */ 68 .dcfclkv_mid0p72 = 600, /* MHz, = 3600/6, bypass */ 69 .dcfclkv_min0p65 = 300, /* MHz, = 3600/12, bypass */ 70 71 /* default DISP CLK voltage state on RV */ 72 .max_dispclk_vmax0p9 = 1108, /* MHz, = 3600/3.25 */ 73 .max_dispclk_vnom0p8 = 1029, /* MHz, = 3600/3.5 */ 74 .max_dispclk_vmid0p72 = 960, /* MHz, = 3600/3.75 */ 75 .max_dispclk_vmin0p65 = 626, /* MHz, = 3600/5.75 */ 76 77 /* default DPP CLK voltage state on RV */ 78 .max_dppclk_vmax0p9 = 720, /* MHz, = 3600/5 */ 79 .max_dppclk_vnom0p8 = 686, /* MHz, = 3600/5.25 */ 80 .max_dppclk_vmid0p72 = 626, /* MHz, = 3600/5.75 */ 81 .max_dppclk_vmin0p65 = 400, /* MHz, = 3600/9 */ 82 83 /* default PHY CLK voltage state on RV */ 84 .phyclkv_max0p9 = 900, /*MHz*/ 85 .phyclkv_nom0p8 = 847, /*MHz*/ 86 .phyclkv_mid0p72 = 800, /*MHz*/ 87 .phyclkv_min0p65 = 600, /*MHz*/ 88 89 /* BW depend on FCLK, MCLK, # of channels */ 90 /* dual channel BW */ 91 .fabric_and_dram_bandwidth_vmax0p9 = 38.4f, /*GB/s*/ 92 .fabric_and_dram_bandwidth_vnom0p8 = 34.133f, /*GB/s*/ 93 .fabric_and_dram_bandwidth_vmid0p72 = 29.866f, /*GB/s*/ 94 .fabric_and_dram_bandwidth_vmin0p65 = 12.8f, /*GB/s*/ 95 /* single channel BW 96 .fabric_and_dram_bandwidth_vmax0p9 = 19.2f, 97 .fabric_and_dram_bandwidth_vnom0p8 = 17.066f, 98 .fabric_and_dram_bandwidth_vmid0p72 = 14.933f, 99 .fabric_and_dram_bandwidth_vmin0p65 = 12.8f, 100 */ 101 102 .number_of_channels = 2, 103 104 .socclk = 208, /*MHz*/ 105 .downspreading = 0.5f, /*%*/ 106 .round_trip_ping_latency_cycles = 128, /*DCFCLK Cycles*/ 107 .urgent_out_of_order_return_per_channel = 256, /*bytes*/ 108 .vmm_page_size = 4096, /*bytes*/ 109 .return_bus_width = 64, /*bytes*/ 110 .max_request_size = 256, /*bytes*/ 111 112 /* Depends on user class (client vs embedded, workstation, etc) */ 113 .percent_disp_bw_limit = 0.3f /*%*/ 114 }; 115 116 const struct dcn_ip_params dcn10_ip_defaults = { 117 .rob_buffer_size_in_kbyte = 64, 118 .det_buffer_size_in_kbyte = 164, 119 .dpp_output_buffer_pixels = 2560, 120 .opp_output_buffer_lines = 1, 121 .pixel_chunk_size_in_kbyte = 8, 122 .pte_enable = dcn_bw_yes, 123 .pte_chunk_size = 2, /*kbytes*/ 124 .meta_chunk_size = 2, /*kbytes*/ 125 .writeback_chunk_size = 2, /*kbytes*/ 126 .odm_capability = dcn_bw_no, 127 .dsc_capability = dcn_bw_no, 128 .line_buffer_size = 589824, /*bit*/ 129 .max_line_buffer_lines = 12, 130 .is_line_buffer_bpp_fixed = dcn_bw_no, 131 .line_buffer_fixed_bpp = dcn_bw_na, 132 .writeback_luma_buffer_size = 12, /*kbytes*/ 133 .writeback_chroma_buffer_size = 8, /*kbytes*/ 134 .max_num_dpp = 4, 135 .max_num_writeback = 2, 136 .max_dchub_topscl_throughput = 4, /*pixels/dppclk*/ 137 .max_pscl_tolb_throughput = 2, /*pixels/dppclk*/ 138 .max_lb_tovscl_throughput = 4, /*pixels/dppclk*/ 139 .max_vscl_tohscl_throughput = 4, /*pixels/dppclk*/ 140 .max_hscl_ratio = 4, 141 .max_vscl_ratio = 4, 142 .max_hscl_taps = 8, 143 .max_vscl_taps = 8, 144 .pte_buffer_size_in_requests = 42, 145 .dispclk_ramping_margin = 1, /*%*/ 146 .under_scan_factor = 1.11f, 147 .max_inter_dcn_tile_repeaters = 8, 148 .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = dcn_bw_no, 149 .bug_forcing_luma_and_chroma_request_to_same_size_fixed = dcn_bw_no, 150 .dcfclk_cstate_latency = 10 /*TODO clone of something else? sr_enter_plus_exit_time?*/ 151 }; 152 153 static enum dcn_bw_defs tl_sw_mode_to_bw_defs(enum swizzle_mode_values sw_mode) 154 { 155 switch (sw_mode) { 156 case DC_SW_LINEAR: 157 return dcn_bw_sw_linear; 158 case DC_SW_4KB_S: 159 return dcn_bw_sw_4_kb_s; 160 case DC_SW_4KB_D: 161 return dcn_bw_sw_4_kb_d; 162 case DC_SW_64KB_S: 163 return dcn_bw_sw_64_kb_s; 164 case DC_SW_64KB_D: 165 return dcn_bw_sw_64_kb_d; 166 case DC_SW_VAR_S: 167 return dcn_bw_sw_var_s; 168 case DC_SW_VAR_D: 169 return dcn_bw_sw_var_d; 170 case DC_SW_64KB_S_T: 171 return dcn_bw_sw_64_kb_s_t; 172 case DC_SW_64KB_D_T: 173 return dcn_bw_sw_64_kb_d_t; 174 case DC_SW_4KB_S_X: 175 return dcn_bw_sw_4_kb_s_x; 176 case DC_SW_4KB_D_X: 177 return dcn_bw_sw_4_kb_d_x; 178 case DC_SW_64KB_S_X: 179 return dcn_bw_sw_64_kb_s_x; 180 case DC_SW_64KB_D_X: 181 return dcn_bw_sw_64_kb_d_x; 182 case DC_SW_VAR_S_X: 183 return dcn_bw_sw_var_s_x; 184 case DC_SW_VAR_D_X: 185 return dcn_bw_sw_var_d_x; 186 case DC_SW_256B_S: 187 case DC_SW_256_D: 188 case DC_SW_256_R: 189 case DC_SW_4KB_R: 190 case DC_SW_64KB_R: 191 case DC_SW_VAR_R: 192 case DC_SW_4KB_R_X: 193 case DC_SW_64KB_R_X: 194 case DC_SW_VAR_R_X: 195 default: 196 BREAK_TO_DEBUGGER(); /*not in formula*/ 197 return dcn_bw_sw_4_kb_s; 198 } 199 } 200 201 static int tl_lb_bpp_to_int(enum lb_pixel_depth depth) 202 { 203 switch (depth) { 204 case LB_PIXEL_DEPTH_18BPP: 205 return 18; 206 case LB_PIXEL_DEPTH_24BPP: 207 return 24; 208 case LB_PIXEL_DEPTH_30BPP: 209 return 30; 210 case LB_PIXEL_DEPTH_36BPP: 211 return 36; 212 default: 213 return 30; 214 } 215 } 216 217 static enum dcn_bw_defs tl_pixel_format_to_bw_defs(enum surface_pixel_format format) 218 { 219 switch (format) { 220 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 221 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 222 return dcn_bw_rgb_sub_16; 223 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 224 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 225 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 226 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 227 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 228 return dcn_bw_rgb_sub_32; 229 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 230 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 231 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 232 return dcn_bw_rgb_sub_64; 233 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 234 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 235 return dcn_bw_yuv420_sub_8; 236 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 237 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 238 return dcn_bw_yuv420_sub_10; 239 default: 240 return dcn_bw_rgb_sub_32; 241 } 242 } 243 244 static void pipe_ctx_to_e2e_pipe_params ( 245 const struct pipe_ctx *pipe, 246 struct _vcs_dpi_display_pipe_params_st *input) 247 { 248 input->src.is_hsplit = false; 249 if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state) 250 input->src.is_hsplit = true; 251 else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state) 252 input->src.is_hsplit = true; 253 254 if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) { 255 /* 256 * this method requires us to always re-calculate watermark when dcc change 257 * between flip. 258 */ 259 input->src.dcc = pipe->plane_state->dcc.enable ? 1 : 0; 260 } else { 261 /* 262 * allow us to disable dcc on the fly without re-calculating WM 263 * 264 * extra overhead for DCC is quite small. for 1080p WM without 265 * DCC is only 0.417us lower (urgent goes from 6.979us to 6.562us) 266 */ 267 unsigned int bpe; 268 269 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs-> 270 dcc_support_pixel_format(pipe->plane_state->format, &bpe) ? 1 : 0; 271 } 272 input->src.dcc_rate = 1; 273 input->src.meta_pitch = pipe->plane_state->dcc.grph.meta_pitch; 274 input->src.source_scan = dm_horz; 275 input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle; 276 277 input->src.viewport_width = pipe->plane_res.scl_data.viewport.width; 278 input->src.viewport_height = pipe->plane_res.scl_data.viewport.height; 279 input->src.data_pitch = pipe->plane_res.scl_data.viewport.width; 280 input->src.data_pitch_c = pipe->plane_res.scl_data.viewport.width; 281 input->src.cur0_src_width = 128; /* TODO: Cursor calcs, not curently stored */ 282 input->src.cur0_bpp = 32; 283 284 switch (pipe->plane_state->tiling_info.gfx9.swizzle) { 285 /* for 4/8/16 high tiles */ 286 case DC_SW_LINEAR: 287 input->src.is_display_sw = 1; 288 input->src.macro_tile_size = dm_4k_tile; 289 break; 290 case DC_SW_4KB_S: 291 case DC_SW_4KB_S_X: 292 input->src.is_display_sw = 0; 293 input->src.macro_tile_size = dm_4k_tile; 294 break; 295 case DC_SW_64KB_S: 296 case DC_SW_64KB_S_X: 297 case DC_SW_64KB_S_T: 298 input->src.is_display_sw = 0; 299 input->src.macro_tile_size = dm_64k_tile; 300 break; 301 case DC_SW_VAR_S: 302 case DC_SW_VAR_S_X: 303 input->src.is_display_sw = 0; 304 input->src.macro_tile_size = dm_256k_tile; 305 break; 306 307 /* For 64bpp 2 high tiles */ 308 case DC_SW_4KB_D: 309 case DC_SW_4KB_D_X: 310 input->src.is_display_sw = 1; 311 input->src.macro_tile_size = dm_4k_tile; 312 break; 313 case DC_SW_64KB_D: 314 case DC_SW_64KB_D_X: 315 case DC_SW_64KB_D_T: 316 input->src.is_display_sw = 1; 317 input->src.macro_tile_size = dm_64k_tile; 318 break; 319 case DC_SW_VAR_D: 320 case DC_SW_VAR_D_X: 321 input->src.is_display_sw = 1; 322 input->src.macro_tile_size = dm_256k_tile; 323 break; 324 325 /* Unsupported swizzle modes for dcn */ 326 case DC_SW_256B_S: 327 default: 328 ASSERT(0); /* Not supported */ 329 break; 330 } 331 332 switch (pipe->plane_state->rotation) { 333 case ROTATION_ANGLE_0: 334 case ROTATION_ANGLE_180: 335 input->src.source_scan = dm_horz; 336 break; 337 case ROTATION_ANGLE_90: 338 case ROTATION_ANGLE_270: 339 input->src.source_scan = dm_vert; 340 break; 341 default: 342 ASSERT(0); /* Not supported */ 343 break; 344 } 345 346 /* TODO: Fix pixel format mappings */ 347 switch (pipe->plane_state->format) { 348 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 349 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 350 input->src.source_format = dm_420_8; 351 input->src.viewport_width_c = input->src.viewport_width / 2; 352 input->src.viewport_height_c = input->src.viewport_height / 2; 353 break; 354 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 355 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 356 input->src.source_format = dm_420_10; 357 input->src.viewport_width_c = input->src.viewport_width / 2; 358 input->src.viewport_height_c = input->src.viewport_height / 2; 359 break; 360 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 361 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 362 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 363 input->src.source_format = dm_444_64; 364 input->src.viewport_width_c = input->src.viewport_width; 365 input->src.viewport_height_c = input->src.viewport_height; 366 break; 367 default: 368 input->src.source_format = dm_444_32; 369 input->src.viewport_width_c = input->src.viewport_width; 370 input->src.viewport_height_c = input->src.viewport_height; 371 break; 372 } 373 374 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps; 375 input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0; 376 input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0; 377 input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0; 378 if (input->scale_ratio_depth.vinit < 1.0) 379 input->scale_ratio_depth.vinit = 1; 380 input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps; 381 input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c; 382 input->scale_taps.htaps_c = pipe->plane_res.scl_data.taps.h_taps_c; 383 input->scale_ratio_depth.hscl_ratio_c = pipe->plane_res.scl_data.ratios.horz_c.value/4294967296.0; 384 input->scale_ratio_depth.vscl_ratio_c = pipe->plane_res.scl_data.ratios.vert_c.value/4294967296.0; 385 input->scale_ratio_depth.vinit_c = pipe->plane_res.scl_data.inits.v_c.value/4294967296.0; 386 if (input->scale_ratio_depth.vinit_c < 1.0) 387 input->scale_ratio_depth.vinit_c = 1; 388 switch (pipe->plane_res.scl_data.lb_params.depth) { 389 case LB_PIXEL_DEPTH_30BPP: 390 input->scale_ratio_depth.lb_depth = 30; break; 391 case LB_PIXEL_DEPTH_36BPP: 392 input->scale_ratio_depth.lb_depth = 36; break; 393 default: 394 input->scale_ratio_depth.lb_depth = 24; break; 395 } 396 397 398 input->dest.vactive = pipe->stream->timing.v_addressable + pipe->stream->timing.v_border_top 399 + pipe->stream->timing.v_border_bottom; 400 401 input->dest.recout_width = pipe->plane_res.scl_data.recout.width; 402 input->dest.recout_height = pipe->plane_res.scl_data.recout.height; 403 404 input->dest.full_recout_width = pipe->plane_res.scl_data.recout.width; 405 input->dest.full_recout_height = pipe->plane_res.scl_data.recout.height; 406 407 input->dest.htotal = pipe->stream->timing.h_total; 408 input->dest.hblank_start = input->dest.htotal - pipe->stream->timing.h_front_porch; 409 input->dest.hblank_end = input->dest.hblank_start 410 - pipe->stream->timing.h_addressable 411 - pipe->stream->timing.h_border_left 412 - pipe->stream->timing.h_border_right; 413 414 input->dest.vtotal = pipe->stream->timing.v_total; 415 input->dest.vblank_start = input->dest.vtotal - pipe->stream->timing.v_front_porch; 416 input->dest.vblank_end = input->dest.vblank_start 417 - pipe->stream->timing.v_addressable 418 - pipe->stream->timing.v_border_bottom 419 - pipe->stream->timing.v_border_top; 420 input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_khz/1000.0; 421 input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start; 422 input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; 423 input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; 424 input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width; 425 426 } 427 428 static void dcn_bw_calc_rq_dlg_ttu( 429 const struct dc *dc, 430 const struct dcn_bw_internal_vars *v, 431 struct pipe_ctx *pipe, 432 int in_idx) 433 { 434 struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml); 435 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &pipe->dlg_regs; 436 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &pipe->ttu_regs; 437 struct _vcs_dpi_display_rq_regs_st *rq_regs = &pipe->rq_regs; 438 struct _vcs_dpi_display_rq_params_st rq_param = {0}; 439 struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param = {0}; 440 struct _vcs_dpi_display_e2e_pipe_params_st input = { { { 0 } } }; 441 float total_active_bw = 0; 442 float total_prefetch_bw = 0; 443 int total_flip_bytes = 0; 444 int i; 445 446 memset(dlg_regs, 0, sizeof(*dlg_regs)); 447 memset(ttu_regs, 0, sizeof(*ttu_regs)); 448 memset(rq_regs, 0, sizeof(*rq_regs)); 449 450 for (i = 0; i < number_of_planes; i++) { 451 total_active_bw += v->read_bandwidth[i]; 452 total_prefetch_bw += v->prefetch_bandwidth[i]; 453 total_flip_bytes += v->total_immediate_flip_bytes[i]; 454 } 455 dlg_sys_param.total_flip_bw = v->return_bw - dcn_bw_max2(total_active_bw, total_prefetch_bw); 456 if (dlg_sys_param.total_flip_bw < 0.0) 457 dlg_sys_param.total_flip_bw = 0; 458 459 dlg_sys_param.t_mclk_wm_us = v->dram_clock_change_watermark; 460 dlg_sys_param.t_sr_wm_us = v->stutter_enter_plus_exit_watermark; 461 dlg_sys_param.t_urg_wm_us = v->urgent_watermark; 462 dlg_sys_param.t_extra_us = v->urgent_extra_latency; 463 dlg_sys_param.deepsleep_dcfclk_mhz = v->dcf_clk_deep_sleep; 464 dlg_sys_param.total_flip_bytes = total_flip_bytes; 465 466 pipe_ctx_to_e2e_pipe_params(pipe, &input.pipe); 467 input.clks_cfg.dcfclk_mhz = v->dcfclk; 468 input.clks_cfg.dispclk_mhz = v->dispclk; 469 input.clks_cfg.dppclk_mhz = v->dppclk; 470 input.clks_cfg.refclk_mhz = dc->res_pool->ref_clock_inKhz / 1000.0; 471 input.clks_cfg.socclk_mhz = v->socclk; 472 input.clks_cfg.voltage = v->voltage_level; 473 // dc->dml.logger = pool->base.logger; 474 input.dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444; 475 input.dout.output_type = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp; 476 //input[in_idx].dout.output_standard; 477 478 /*todo: soc->sr_enter_plus_exit_time??*/ 479 dlg_sys_param.t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep; 480 481 dml1_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src); 482 dml1_extract_rq_regs(dml, rq_regs, rq_param); 483 dml1_rq_dlg_get_dlg_params( 484 dml, 485 dlg_regs, 486 ttu_regs, 487 rq_param.dlg, 488 dlg_sys_param, 489 input, 490 true, 491 true, 492 v->pte_enable == dcn_bw_yes, 493 pipe->plane_state->flip_immediate); 494 } 495 496 static void split_stream_across_pipes( 497 struct resource_context *res_ctx, 498 const struct resource_pool *pool, 499 struct pipe_ctx *primary_pipe, 500 struct pipe_ctx *secondary_pipe) 501 { 502 int pipe_idx = secondary_pipe->pipe_idx; 503 504 if (!primary_pipe->plane_state) 505 return; 506 507 *secondary_pipe = *primary_pipe; 508 509 secondary_pipe->pipe_idx = pipe_idx; 510 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; 511 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; 512 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx]; 513 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; 514 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; 515 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; 516 if (primary_pipe->bottom_pipe) { 517 ASSERT(primary_pipe->bottom_pipe != secondary_pipe); 518 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe; 519 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe; 520 } 521 primary_pipe->bottom_pipe = secondary_pipe; 522 secondary_pipe->top_pipe = primary_pipe; 523 524 resource_build_scaling_params(primary_pipe); 525 resource_build_scaling_params(secondary_pipe); 526 } 527 528 #if 0 529 static void calc_wm_sets_and_perf_params( 530 struct dc_state *context, 531 struct dcn_bw_internal_vars *v) 532 { 533 /* Calculate set A last to keep internal var state consistent for required config */ 534 if (v->voltage_level < 2) { 535 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vnom0p8; 536 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vnom0p8; 537 v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vnom0p8; 538 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v); 539 540 context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = 541 v->stutter_exit_watermark * 1000; 542 context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = 543 v->stutter_enter_plus_exit_watermark * 1000; 544 context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = 545 v->dram_clock_change_watermark * 1000; 546 context->bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000; 547 context->bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000; 548 549 v->dcfclk_per_state[1] = v->dcfclkv_nom0p8; 550 v->dcfclk_per_state[0] = v->dcfclkv_nom0p8; 551 v->dcfclk = v->dcfclkv_nom0p8; 552 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v); 553 554 context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = 555 v->stutter_exit_watermark * 1000; 556 context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = 557 v->stutter_enter_plus_exit_watermark * 1000; 558 context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = 559 v->dram_clock_change_watermark * 1000; 560 context->bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000; 561 context->bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000; 562 } 563 564 if (v->voltage_level < 3) { 565 v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vmax0p9; 566 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmax0p9; 567 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmax0p9; 568 v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vmax0p9; 569 v->dcfclk_per_state[2] = v->dcfclkv_max0p9; 570 v->dcfclk_per_state[1] = v->dcfclkv_max0p9; 571 v->dcfclk_per_state[0] = v->dcfclkv_max0p9; 572 v->dcfclk = v->dcfclkv_max0p9; 573 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v); 574 575 context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = 576 v->stutter_exit_watermark * 1000; 577 context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = 578 v->stutter_enter_plus_exit_watermark * 1000; 579 context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = 580 v->dram_clock_change_watermark * 1000; 581 context->bw.dcn.watermarks.d.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000; 582 context->bw.dcn.watermarks.d.urgent_ns = v->urgent_watermark * 1000; 583 } 584 585 v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8; 586 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72; 587 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65; 588 v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_per_state[v->voltage_level]; 589 v->dcfclk_per_state[2] = v->dcfclkv_nom0p8; 590 v->dcfclk_per_state[1] = v->dcfclkv_mid0p72; 591 v->dcfclk_per_state[0] = v->dcfclkv_min0p65; 592 v->dcfclk = v->dcfclk_per_state[v->voltage_level]; 593 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v); 594 595 context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = 596 v->stutter_exit_watermark * 1000; 597 context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = 598 v->stutter_enter_plus_exit_watermark * 1000; 599 context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 600 v->dram_clock_change_watermark * 1000; 601 context->bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000; 602 context->bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000; 603 if (v->voltage_level >= 2) { 604 context->bw.dcn.watermarks.b = context->bw.dcn.watermarks.a; 605 context->bw.dcn.watermarks.c = context->bw.dcn.watermarks.a; 606 } 607 if (v->voltage_level >= 3) 608 context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a; 609 } 610 #endif 611 612 static bool dcn_bw_apply_registry_override(struct dc *dc) 613 { 614 bool updated = false; 615 616 kernel_fpu_begin(); 617 if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns 618 && dc->debug.sr_exit_time_ns) { 619 updated = true; 620 dc->dcn_soc->sr_exit_time = dc->debug.sr_exit_time_ns / 1000.0; 621 } 622 623 if ((int)(dc->dcn_soc->sr_enter_plus_exit_time * 1000) 624 != dc->debug.sr_enter_plus_exit_time_ns 625 && dc->debug.sr_enter_plus_exit_time_ns) { 626 updated = true; 627 dc->dcn_soc->sr_enter_plus_exit_time = 628 dc->debug.sr_enter_plus_exit_time_ns / 1000.0; 629 } 630 631 if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->debug.urgent_latency_ns 632 && dc->debug.urgent_latency_ns) { 633 updated = true; 634 dc->dcn_soc->urgent_latency = dc->debug.urgent_latency_ns / 1000.0; 635 } 636 637 if ((int)(dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency * 1000) 638 != dc->debug.percent_of_ideal_drambw 639 && dc->debug.percent_of_ideal_drambw) { 640 updated = true; 641 dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency = 642 dc->debug.percent_of_ideal_drambw; 643 } 644 645 if ((int)(dc->dcn_soc->dram_clock_change_latency * 1000) 646 != dc->debug.dram_clock_change_latency_ns 647 && dc->debug.dram_clock_change_latency_ns) { 648 updated = true; 649 dc->dcn_soc->dram_clock_change_latency = 650 dc->debug.dram_clock_change_latency_ns / 1000.0; 651 } 652 kernel_fpu_end(); 653 654 return updated; 655 } 656 657 static void hack_disable_optional_pipe_split(struct dcn_bw_internal_vars *v) 658 { 659 /* 660 * disable optional pipe split by lower dispclk bounding box 661 * at DPM0 662 */ 663 v->max_dispclk[0] = v->max_dppclk_vmin0p65; 664 } 665 666 static void hack_force_pipe_split(struct dcn_bw_internal_vars *v, 667 unsigned int pixel_rate_khz) 668 { 669 float pixel_rate_mhz = pixel_rate_khz / 1000; 670 671 /* 672 * force enabling pipe split by lower dpp clock for DPM0 to just 673 * below the specify pixel_rate, so bw calc would split pipe. 674 */ 675 if (pixel_rate_mhz < v->max_dppclk[0]) 676 v->max_dppclk[0] = pixel_rate_mhz; 677 } 678 679 static void hack_bounding_box(struct dcn_bw_internal_vars *v, 680 struct dc_debug_options *dbg, 681 struct dc_state *context) 682 { 683 if (dbg->pipe_split_policy == MPC_SPLIT_AVOID) 684 hack_disable_optional_pipe_split(v); 685 686 if (dbg->pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP && 687 context->stream_count >= 2) 688 hack_disable_optional_pipe_split(v); 689 690 if (context->stream_count == 1 && 691 dbg->force_single_disp_pipe_split) 692 hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_khz); 693 } 694 695 bool dcn_validate_bandwidth( 696 struct dc *dc, 697 struct dc_state *context) 698 { 699 const struct resource_pool *pool = dc->res_pool; 700 struct dcn_bw_internal_vars *v = &context->dcn_bw_vars; 701 int i, input_idx; 702 int vesa_sync_start, asic_blank_end, asic_blank_start; 703 bool bw_limit_pass; 704 float bw_limit; 705 706 PERFORMANCE_TRACE_START(); 707 if (dcn_bw_apply_registry_override(dc)) 708 dcn_bw_sync_calcs_and_dml(dc); 709 710 memset(v, 0, sizeof(*v)); 711 kernel_fpu_begin(); 712 v->sr_exit_time = dc->dcn_soc->sr_exit_time; 713 v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time; 714 v->urgent_latency = dc->dcn_soc->urgent_latency; 715 v->write_back_latency = dc->dcn_soc->write_back_latency; 716 v->percent_of_ideal_drambw_received_after_urg_latency = 717 dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency; 718 719 v->dcfclkv_min0p65 = dc->dcn_soc->dcfclkv_min0p65; 720 v->dcfclkv_mid0p72 = dc->dcn_soc->dcfclkv_mid0p72; 721 v->dcfclkv_nom0p8 = dc->dcn_soc->dcfclkv_nom0p8; 722 v->dcfclkv_max0p9 = dc->dcn_soc->dcfclkv_max0p9; 723 724 v->max_dispclk_vmin0p65 = dc->dcn_soc->max_dispclk_vmin0p65; 725 v->max_dispclk_vmid0p72 = dc->dcn_soc->max_dispclk_vmid0p72; 726 v->max_dispclk_vnom0p8 = dc->dcn_soc->max_dispclk_vnom0p8; 727 v->max_dispclk_vmax0p9 = dc->dcn_soc->max_dispclk_vmax0p9; 728 729 v->max_dppclk_vmin0p65 = dc->dcn_soc->max_dppclk_vmin0p65; 730 v->max_dppclk_vmid0p72 = dc->dcn_soc->max_dppclk_vmid0p72; 731 v->max_dppclk_vnom0p8 = dc->dcn_soc->max_dppclk_vnom0p8; 732 v->max_dppclk_vmax0p9 = dc->dcn_soc->max_dppclk_vmax0p9; 733 734 v->socclk = dc->dcn_soc->socclk; 735 736 v->fabric_and_dram_bandwidth_vmin0p65 = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65; 737 v->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72; 738 v->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8; 739 v->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9; 740 741 v->phyclkv_min0p65 = dc->dcn_soc->phyclkv_min0p65; 742 v->phyclkv_mid0p72 = dc->dcn_soc->phyclkv_mid0p72; 743 v->phyclkv_nom0p8 = dc->dcn_soc->phyclkv_nom0p8; 744 v->phyclkv_max0p9 = dc->dcn_soc->phyclkv_max0p9; 745 746 v->downspreading = dc->dcn_soc->downspreading; 747 v->round_trip_ping_latency_cycles = dc->dcn_soc->round_trip_ping_latency_cycles; 748 v->urgent_out_of_order_return_per_channel = dc->dcn_soc->urgent_out_of_order_return_per_channel; 749 v->number_of_channels = dc->dcn_soc->number_of_channels; 750 v->vmm_page_size = dc->dcn_soc->vmm_page_size; 751 v->dram_clock_change_latency = dc->dcn_soc->dram_clock_change_latency; 752 v->return_bus_width = dc->dcn_soc->return_bus_width; 753 754 v->rob_buffer_size_in_kbyte = dc->dcn_ip->rob_buffer_size_in_kbyte; 755 v->det_buffer_size_in_kbyte = dc->dcn_ip->det_buffer_size_in_kbyte; 756 v->dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels; 757 v->opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines; 758 v->pixel_chunk_size_in_kbyte = dc->dcn_ip->pixel_chunk_size_in_kbyte; 759 v->pte_enable = dc->dcn_ip->pte_enable; 760 v->pte_chunk_size = dc->dcn_ip->pte_chunk_size; 761 v->meta_chunk_size = dc->dcn_ip->meta_chunk_size; 762 v->writeback_chunk_size = dc->dcn_ip->writeback_chunk_size; 763 v->odm_capability = dc->dcn_ip->odm_capability; 764 v->dsc_capability = dc->dcn_ip->dsc_capability; 765 v->line_buffer_size = dc->dcn_ip->line_buffer_size; 766 v->is_line_buffer_bpp_fixed = dc->dcn_ip->is_line_buffer_bpp_fixed; 767 v->line_buffer_fixed_bpp = dc->dcn_ip->line_buffer_fixed_bpp; 768 v->max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines; 769 v->writeback_luma_buffer_size = dc->dcn_ip->writeback_luma_buffer_size; 770 v->writeback_chroma_buffer_size = dc->dcn_ip->writeback_chroma_buffer_size; 771 v->max_num_dpp = dc->dcn_ip->max_num_dpp; 772 v->max_num_writeback = dc->dcn_ip->max_num_writeback; 773 v->max_dchub_topscl_throughput = dc->dcn_ip->max_dchub_topscl_throughput; 774 v->max_pscl_tolb_throughput = dc->dcn_ip->max_pscl_tolb_throughput; 775 v->max_lb_tovscl_throughput = dc->dcn_ip->max_lb_tovscl_throughput; 776 v->max_vscl_tohscl_throughput = dc->dcn_ip->max_vscl_tohscl_throughput; 777 v->max_hscl_ratio = dc->dcn_ip->max_hscl_ratio; 778 v->max_vscl_ratio = dc->dcn_ip->max_vscl_ratio; 779 v->max_hscl_taps = dc->dcn_ip->max_hscl_taps; 780 v->max_vscl_taps = dc->dcn_ip->max_vscl_taps; 781 v->under_scan_factor = dc->dcn_ip->under_scan_factor; 782 v->pte_buffer_size_in_requests = dc->dcn_ip->pte_buffer_size_in_requests; 783 v->dispclk_ramping_margin = dc->dcn_ip->dispclk_ramping_margin; 784 v->max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters; 785 v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 786 dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one; 787 v->bug_forcing_luma_and_chroma_request_to_same_size_fixed = 788 dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed; 789 790 v->voltage[5] = dcn_bw_no_support; 791 v->voltage[4] = dcn_bw_v_max0p9; 792 v->voltage[3] = dcn_bw_v_max0p9; 793 v->voltage[2] = dcn_bw_v_nom0p8; 794 v->voltage[1] = dcn_bw_v_mid0p72; 795 v->voltage[0] = dcn_bw_v_min0p65; 796 v->fabric_and_dram_bandwidth_per_state[5] = v->fabric_and_dram_bandwidth_vmax0p9; 797 v->fabric_and_dram_bandwidth_per_state[4] = v->fabric_and_dram_bandwidth_vmax0p9; 798 v->fabric_and_dram_bandwidth_per_state[3] = v->fabric_and_dram_bandwidth_vmax0p9; 799 v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8; 800 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72; 801 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65; 802 v->dcfclk_per_state[5] = v->dcfclkv_max0p9; 803 v->dcfclk_per_state[4] = v->dcfclkv_max0p9; 804 v->dcfclk_per_state[3] = v->dcfclkv_max0p9; 805 v->dcfclk_per_state[2] = v->dcfclkv_nom0p8; 806 v->dcfclk_per_state[1] = v->dcfclkv_mid0p72; 807 v->dcfclk_per_state[0] = v->dcfclkv_min0p65; 808 v->max_dispclk[5] = v->max_dispclk_vmax0p9; 809 v->max_dispclk[4] = v->max_dispclk_vmax0p9; 810 v->max_dispclk[3] = v->max_dispclk_vmax0p9; 811 v->max_dispclk[2] = v->max_dispclk_vnom0p8; 812 v->max_dispclk[1] = v->max_dispclk_vmid0p72; 813 v->max_dispclk[0] = v->max_dispclk_vmin0p65; 814 v->max_dppclk[5] = v->max_dppclk_vmax0p9; 815 v->max_dppclk[4] = v->max_dppclk_vmax0p9; 816 v->max_dppclk[3] = v->max_dppclk_vmax0p9; 817 v->max_dppclk[2] = v->max_dppclk_vnom0p8; 818 v->max_dppclk[1] = v->max_dppclk_vmid0p72; 819 v->max_dppclk[0] = v->max_dppclk_vmin0p65; 820 v->phyclk_per_state[5] = v->phyclkv_max0p9; 821 v->phyclk_per_state[4] = v->phyclkv_max0p9; 822 v->phyclk_per_state[3] = v->phyclkv_max0p9; 823 v->phyclk_per_state[2] = v->phyclkv_nom0p8; 824 v->phyclk_per_state[1] = v->phyclkv_mid0p72; 825 v->phyclk_per_state[0] = v->phyclkv_min0p65; 826 v->synchronized_vblank = dcn_bw_no; 827 v->ta_pscalculation = dcn_bw_override; 828 v->allow_different_hratio_vratio = dcn_bw_yes; 829 830 for (i = 0, input_idx = 0; i < pool->pipe_count; i++) { 831 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 832 833 if (!pipe->stream) 834 continue; 835 /* skip all but first of split pipes */ 836 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) 837 continue; 838 839 v->underscan_output[input_idx] = false; /* taken care of in recout already*/ 840 v->interlace_output[input_idx] = false; 841 842 v->htotal[input_idx] = pipe->stream->timing.h_total; 843 v->vtotal[input_idx] = pipe->stream->timing.v_total; 844 v->vactive[input_idx] = pipe->stream->timing.v_addressable + 845 pipe->stream->timing.v_border_top + pipe->stream->timing.v_border_bottom; 846 v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total 847 - v->vactive[input_idx] 848 - pipe->stream->timing.v_front_porch; 849 v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_khz / 1000.0f; 850 851 if (!pipe->plane_state) { 852 v->dcc_enable[input_idx] = dcn_bw_yes; 853 v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32; 854 v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s; 855 v->lb_bit_per_pixel[input_idx] = 30; 856 v->viewport_width[input_idx] = pipe->stream->timing.h_addressable; 857 v->viewport_height[input_idx] = pipe->stream->timing.v_addressable; 858 v->scaler_rec_out_width[input_idx] = pipe->stream->timing.h_addressable; 859 v->scaler_recout_height[input_idx] = pipe->stream->timing.v_addressable; 860 v->override_hta_ps[input_idx] = 1; 861 v->override_vta_ps[input_idx] = 1; 862 v->override_hta_pschroma[input_idx] = 1; 863 v->override_vta_pschroma[input_idx] = 1; 864 v->source_scan[input_idx] = dcn_bw_hor; 865 866 } else { 867 v->viewport_height[input_idx] = pipe->plane_res.scl_data.viewport.height; 868 v->viewport_width[input_idx] = pipe->plane_res.scl_data.viewport.width; 869 v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width; 870 v->scaler_recout_height[input_idx] = pipe->plane_res.scl_data.recout.height; 871 if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) { 872 if (pipe->plane_state->rotation % 2 == 0) { 873 int viewport_end = pipe->plane_res.scl_data.viewport.width 874 + pipe->plane_res.scl_data.viewport.x; 875 int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.width 876 + pipe->bottom_pipe->plane_res.scl_data.viewport.x; 877 878 if (viewport_end > viewport_b_end) 879 v->viewport_width[input_idx] = viewport_end 880 - pipe->bottom_pipe->plane_res.scl_data.viewport.x; 881 else 882 v->viewport_width[input_idx] = viewport_b_end 883 - pipe->plane_res.scl_data.viewport.x; 884 } else { 885 int viewport_end = pipe->plane_res.scl_data.viewport.height 886 + pipe->plane_res.scl_data.viewport.y; 887 int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.height 888 + pipe->bottom_pipe->plane_res.scl_data.viewport.y; 889 890 if (viewport_end > viewport_b_end) 891 v->viewport_height[input_idx] = viewport_end 892 - pipe->bottom_pipe->plane_res.scl_data.viewport.y; 893 else 894 v->viewport_height[input_idx] = viewport_b_end 895 - pipe->plane_res.scl_data.viewport.y; 896 } 897 v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width 898 + pipe->bottom_pipe->plane_res.scl_data.recout.width; 899 } 900 901 if (pipe->plane_state->rotation % 2 == 0) { 902 ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value 903 || v->scaler_rec_out_width[input_idx] == v->viewport_width[input_idx]); 904 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value 905 || v->scaler_recout_height[input_idx] == v->viewport_height[input_idx]); 906 } else { 907 ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value 908 || v->scaler_recout_height[input_idx] == v->viewport_width[input_idx]); 909 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value 910 || v->scaler_rec_out_width[input_idx] == v->viewport_height[input_idx]); 911 } 912 913 if (dc->debug.optimized_watermark) { 914 /* 915 * this method requires us to always re-calculate watermark when dcc change 916 * between flip. 917 */ 918 v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no; 919 } else { 920 /* 921 * allow us to disable dcc on the fly without re-calculating WM 922 * 923 * extra overhead for DCC is quite small. for 1080p WM without 924 * DCC is only 0.417us lower (urgent goes from 6.979us to 6.562us) 925 */ 926 unsigned int bpe; 927 928 v->dcc_enable[input_idx] = dc->res_pool->hubbub->funcs->dcc_support_pixel_format( 929 pipe->plane_state->format, &bpe) ? dcn_bw_yes : dcn_bw_no; 930 } 931 932 v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs( 933 pipe->plane_state->format); 934 v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs( 935 pipe->plane_state->tiling_info.gfx9.swizzle); 936 v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth); 937 v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps; 938 v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps; 939 v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c; 940 v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c; 941 /* 942 * Spreadsheet doesn't handle taps_c is one properly, 943 * need to force Chroma to always be scaled to pass 944 * bandwidth validation. 945 */ 946 if (v->override_hta_pschroma[input_idx] == 1) 947 v->override_hta_pschroma[input_idx] = 2; 948 if (v->override_vta_pschroma[input_idx] == 1) 949 v->override_vta_pschroma[input_idx] = 2; 950 v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor; 951 } 952 if (v->is_line_buffer_bpp_fixed == dcn_bw_yes) 953 v->lb_bit_per_pixel[input_idx] = v->line_buffer_fixed_bpp; 954 v->dcc_rate[input_idx] = 1; /*TODO: Worst case? does this change?*/ 955 v->output_format[input_idx] = pipe->stream->timing.pixel_encoding == 956 PIXEL_ENCODING_YCBCR420 ? dcn_bw_420 : dcn_bw_444; 957 v->output[input_idx] = pipe->stream->sink->sink_signal == 958 SIGNAL_TYPE_HDMI_TYPE_A ? dcn_bw_hdmi : dcn_bw_dp; 959 v->output_deep_color[input_idx] = dcn_bw_encoder_8bpc; 960 if (v->output[input_idx] == dcn_bw_hdmi) { 961 switch (pipe->stream->timing.display_color_depth) { 962 case COLOR_DEPTH_101010: 963 v->output_deep_color[input_idx] = dcn_bw_encoder_10bpc; 964 break; 965 case COLOR_DEPTH_121212: 966 v->output_deep_color[input_idx] = dcn_bw_encoder_12bpc; 967 break; 968 case COLOR_DEPTH_161616: 969 v->output_deep_color[input_idx] = dcn_bw_encoder_16bpc; 970 break; 971 default: 972 break; 973 } 974 } 975 976 input_idx++; 977 } 978 v->number_of_active_planes = input_idx; 979 980 scaler_settings_calculation(v); 981 982 hack_bounding_box(v, &dc->debug, context); 983 984 mode_support_and_system_configuration(v); 985 986 /* Unhack dppclk: dont bother with trying to pipe split if we cannot maintain dpm0 */ 987 if (v->voltage_level != 0 988 && context->stream_count == 1 989 && dc->debug.force_single_disp_pipe_split) { 990 v->max_dppclk[0] = v->max_dppclk_vmin0p65; 991 mode_support_and_system_configuration(v); 992 } 993 994 if (v->voltage_level == 0 && 995 (dc->debug.sr_exit_time_dpm0_ns 996 || dc->debug.sr_enter_plus_exit_time_dpm0_ns)) { 997 998 if (dc->debug.sr_enter_plus_exit_time_dpm0_ns) 999 v->sr_enter_plus_exit_time = 1000 dc->debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f; 1001 if (dc->debug.sr_exit_time_dpm0_ns) 1002 v->sr_exit_time = dc->debug.sr_exit_time_dpm0_ns / 1000.0f; 1003 dc->dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time; 1004 dc->dml.soc.sr_exit_time_us = v->sr_exit_time; 1005 mode_support_and_system_configuration(v); 1006 } 1007 1008 if (v->voltage_level != 5) { 1009 float bw_consumed = v->total_bandwidth_consumed_gbyte_per_second; 1010 if (bw_consumed < v->fabric_and_dram_bandwidth_vmin0p65) 1011 bw_consumed = v->fabric_and_dram_bandwidth_vmin0p65; 1012 else if (bw_consumed < v->fabric_and_dram_bandwidth_vmid0p72) 1013 bw_consumed = v->fabric_and_dram_bandwidth_vmid0p72; 1014 else if (bw_consumed < v->fabric_and_dram_bandwidth_vnom0p8) 1015 bw_consumed = v->fabric_and_dram_bandwidth_vnom0p8; 1016 else 1017 bw_consumed = v->fabric_and_dram_bandwidth_vmax0p9; 1018 1019 if (bw_consumed < v->fabric_and_dram_bandwidth) 1020 if (dc->debug.voltage_align_fclk) 1021 bw_consumed = v->fabric_and_dram_bandwidth; 1022 1023 display_pipe_configuration(v); 1024 /*calc_wm_sets_and_perf_params(context, v);*/ 1025 /* Only 1 set is used by dcn since no noticeable 1026 * performance improvement was measured and due to hw bug DEGVIDCN10-254 1027 */ 1028 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v); 1029 1030 context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = 1031 v->stutter_exit_watermark * 1000; 1032 context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = 1033 v->stutter_enter_plus_exit_watermark * 1000; 1034 context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 1035 v->dram_clock_change_watermark * 1000; 1036 context->bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000; 1037 context->bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000; 1038 context->bw.dcn.watermarks.b = context->bw.dcn.watermarks.a; 1039 context->bw.dcn.watermarks.c = context->bw.dcn.watermarks.a; 1040 context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a; 1041 1042 context->bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 / 1043 (ddr4_dram_factor_single_Channel * v->number_of_channels)); 1044 if (bw_consumed == v->fabric_and_dram_bandwidth_vmin0p65) { 1045 context->bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 / 32); 1046 } 1047 1048 context->bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000); 1049 context->bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000); 1050 1051 context->bw.dcn.clk.dispclk_khz = (int)(v->dispclk * 1000); 1052 if (dc->debug.max_disp_clk == true) 1053 context->bw.dcn.clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000); 1054 1055 if (context->bw.dcn.clk.dispclk_khz < 1056 dc->debug.min_disp_clk_khz) { 1057 context->bw.dcn.clk.dispclk_khz = 1058 dc->debug.min_disp_clk_khz; 1059 } 1060 1061 context->bw.dcn.clk.dppclk_khz = context->bw.dcn.clk.dispclk_khz / v->dispclk_dppclk_ratio; 1062 context->bw.dcn.clk.phyclk_khz = v->phyclk_per_state[v->voltage_level]; 1063 switch (v->voltage_level) { 1064 case 0: 1065 context->bw.dcn.clk.max_supported_dppclk_khz = 1066 (int)(dc->dcn_soc->max_dppclk_vmin0p65 * 1000); 1067 break; 1068 case 1: 1069 context->bw.dcn.clk.max_supported_dppclk_khz = 1070 (int)(dc->dcn_soc->max_dppclk_vmid0p72 * 1000); 1071 break; 1072 case 2: 1073 context->bw.dcn.clk.max_supported_dppclk_khz = 1074 (int)(dc->dcn_soc->max_dppclk_vnom0p8 * 1000); 1075 break; 1076 default: 1077 context->bw.dcn.clk.max_supported_dppclk_khz = 1078 (int)(dc->dcn_soc->max_dppclk_vmax0p9 * 1000); 1079 break; 1080 } 1081 1082 for (i = 0, input_idx = 0; i < pool->pipe_count; i++) { 1083 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1084 1085 /* skip inactive pipe */ 1086 if (!pipe->stream) 1087 continue; 1088 /* skip all but first of split pipes */ 1089 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) 1090 continue; 1091 1092 pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0]; 1093 pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0]; 1094 pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0]; 1095 pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; 1096 1097 pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total; 1098 pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; 1099 vesa_sync_start = pipe->stream->timing.v_addressable + 1100 pipe->stream->timing.v_border_bottom + 1101 pipe->stream->timing.v_front_porch; 1102 1103 asic_blank_end = (pipe->stream->timing.v_total - 1104 vesa_sync_start - 1105 pipe->stream->timing.v_border_top) 1106 * (pipe->stream->timing.flags.INTERLACE ? 1 : 0); 1107 1108 asic_blank_start = asic_blank_end + 1109 (pipe->stream->timing.v_border_top + 1110 pipe->stream->timing.v_addressable + 1111 pipe->stream->timing.v_border_bottom) 1112 * (pipe->stream->timing.flags.INTERLACE ? 1 : 0); 1113 1114 pipe->pipe_dlg_param.vblank_start = asic_blank_start; 1115 pipe->pipe_dlg_param.vblank_end = asic_blank_end; 1116 1117 if (pipe->plane_state) { 1118 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; 1119 1120 pipe->plane_state->update_flags.bits.full_update = 1; 1121 1122 if (v->dpp_per_plane[input_idx] == 2 || 1123 ((pipe->stream->view_format == 1124 VIEW_3D_FORMAT_SIDE_BY_SIDE || 1125 pipe->stream->view_format == 1126 VIEW_3D_FORMAT_TOP_AND_BOTTOM) && 1127 (pipe->stream->timing.timing_3d_format == 1128 TIMING_3D_FORMAT_TOP_AND_BOTTOM || 1129 pipe->stream->timing.timing_3d_format == 1130 TIMING_3D_FORMAT_SIDE_BY_SIDE))) { 1131 if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { 1132 /* update previously split pipe */ 1133 hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0]; 1134 hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0]; 1135 hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0]; 1136 hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; 1137 1138 hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total; 1139 hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; 1140 hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start; 1141 hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end; 1142 } else { 1143 /* pipe not split previously needs split */ 1144 hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, pool); 1145 ASSERT(hsplit_pipe); 1146 split_stream_across_pipes( 1147 &context->res_ctx, pool, 1148 pipe, hsplit_pipe); 1149 } 1150 1151 dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe, input_idx); 1152 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { 1153 /* merge previously split pipe */ 1154 pipe->bottom_pipe = hsplit_pipe->bottom_pipe; 1155 if (hsplit_pipe->bottom_pipe) 1156 hsplit_pipe->bottom_pipe->top_pipe = pipe; 1157 hsplit_pipe->plane_state = NULL; 1158 hsplit_pipe->stream = NULL; 1159 hsplit_pipe->top_pipe = NULL; 1160 hsplit_pipe->bottom_pipe = NULL; 1161 /* Clear plane_res and stream_res */ 1162 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res)); 1163 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res)); 1164 resource_build_scaling_params(pipe); 1165 } 1166 /* for now important to do this after pipe split for building e2e params */ 1167 dcn_bw_calc_rq_dlg_ttu(dc, v, pipe, input_idx); 1168 } 1169 1170 input_idx++; 1171 } 1172 } 1173 1174 if (v->voltage_level == 0) { 1175 1176 dc->dml.soc.sr_enter_plus_exit_time_us = 1177 dc->dcn_soc->sr_enter_plus_exit_time; 1178 dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time; 1179 } 1180 1181 /* 1182 * BW limit is set to prevent display from impacting other system functions 1183 */ 1184 1185 bw_limit = dc->dcn_soc->percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9; 1186 bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit; 1187 1188 kernel_fpu_end(); 1189 1190 PERFORMANCE_TRACE_END(); 1191 1192 if (bw_limit_pass && v->voltage_level != 5) 1193 return true; 1194 else 1195 return false; 1196 } 1197 1198 static unsigned int dcn_find_normalized_clock_vdd_Level( 1199 const struct dc *dc, 1200 enum dm_pp_clock_type clocks_type, 1201 int clocks_in_khz) 1202 { 1203 int vdd_level = dcn_bw_v_min0p65; 1204 1205 if (clocks_in_khz == 0)/*todo some clock not in the considerations*/ 1206 return vdd_level; 1207 1208 switch (clocks_type) { 1209 case DM_PP_CLOCK_TYPE_DISPLAY_CLK: 1210 if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmax0p9*1000) { 1211 vdd_level = dcn_bw_v_max0p91; 1212 BREAK_TO_DEBUGGER(); 1213 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vnom0p8*1000) { 1214 vdd_level = dcn_bw_v_max0p9; 1215 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmid0p72*1000) { 1216 vdd_level = dcn_bw_v_nom0p8; 1217 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmin0p65*1000) { 1218 vdd_level = dcn_bw_v_mid0p72; 1219 } else 1220 vdd_level = dcn_bw_v_min0p65; 1221 break; 1222 case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK: 1223 if (clocks_in_khz > dc->dcn_soc->phyclkv_max0p9*1000) { 1224 vdd_level = dcn_bw_v_max0p91; 1225 BREAK_TO_DEBUGGER(); 1226 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_nom0p8*1000) { 1227 vdd_level = dcn_bw_v_max0p9; 1228 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_mid0p72*1000) { 1229 vdd_level = dcn_bw_v_nom0p8; 1230 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_min0p65*1000) { 1231 vdd_level = dcn_bw_v_mid0p72; 1232 } else 1233 vdd_level = dcn_bw_v_min0p65; 1234 break; 1235 1236 case DM_PP_CLOCK_TYPE_DPPCLK: 1237 if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmax0p9*1000) { 1238 vdd_level = dcn_bw_v_max0p91; 1239 BREAK_TO_DEBUGGER(); 1240 } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vnom0p8*1000) { 1241 vdd_level = dcn_bw_v_max0p9; 1242 } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmid0p72*1000) { 1243 vdd_level = dcn_bw_v_nom0p8; 1244 } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmin0p65*1000) { 1245 vdd_level = dcn_bw_v_mid0p72; 1246 } else 1247 vdd_level = dcn_bw_v_min0p65; 1248 break; 1249 1250 case DM_PP_CLOCK_TYPE_MEMORY_CLK: 1251 { 1252 unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels); 1253 1254 if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9*1000000/factor) { 1255 vdd_level = dcn_bw_v_max0p91; 1256 BREAK_TO_DEBUGGER(); 1257 } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8*1000000/factor) { 1258 vdd_level = dcn_bw_v_max0p9; 1259 } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72*1000000/factor) { 1260 vdd_level = dcn_bw_v_nom0p8; 1261 } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65*1000000/factor) { 1262 vdd_level = dcn_bw_v_mid0p72; 1263 } else 1264 vdd_level = dcn_bw_v_min0p65; 1265 } 1266 break; 1267 1268 case DM_PP_CLOCK_TYPE_DCFCLK: 1269 if (clocks_in_khz > dc->dcn_soc->dcfclkv_max0p9*1000) { 1270 vdd_level = dcn_bw_v_max0p91; 1271 BREAK_TO_DEBUGGER(); 1272 } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_nom0p8*1000) { 1273 vdd_level = dcn_bw_v_max0p9; 1274 } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_mid0p72*1000) { 1275 vdd_level = dcn_bw_v_nom0p8; 1276 } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_min0p65*1000) { 1277 vdd_level = dcn_bw_v_mid0p72; 1278 } else 1279 vdd_level = dcn_bw_v_min0p65; 1280 break; 1281 1282 default: 1283 break; 1284 } 1285 return vdd_level; 1286 } 1287 1288 unsigned int dcn_find_dcfclk_suits_all( 1289 const struct dc *dc, 1290 struct dc_clocks *clocks) 1291 { 1292 unsigned vdd_level, vdd_level_temp; 1293 unsigned dcf_clk; 1294 1295 /*find a common supported voltage level*/ 1296 vdd_level = dcn_find_normalized_clock_vdd_Level( 1297 dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks->dispclk_khz); 1298 vdd_level_temp = dcn_find_normalized_clock_vdd_Level( 1299 dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks->phyclk_khz); 1300 1301 vdd_level = dcn_bw_max(vdd_level, vdd_level_temp); 1302 vdd_level_temp = dcn_find_normalized_clock_vdd_Level( 1303 dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_khz); 1304 vdd_level = dcn_bw_max(vdd_level, vdd_level_temp); 1305 1306 vdd_level_temp = dcn_find_normalized_clock_vdd_Level( 1307 dc, DM_PP_CLOCK_TYPE_MEMORY_CLK, clocks->fclk_khz); 1308 vdd_level = dcn_bw_max(vdd_level, vdd_level_temp); 1309 vdd_level_temp = dcn_find_normalized_clock_vdd_Level( 1310 dc, DM_PP_CLOCK_TYPE_DCFCLK, clocks->dcfclk_khz); 1311 1312 /*find that level conresponding dcfclk*/ 1313 vdd_level = dcn_bw_max(vdd_level, vdd_level_temp); 1314 if (vdd_level == dcn_bw_v_max0p91) { 1315 BREAK_TO_DEBUGGER(); 1316 dcf_clk = dc->dcn_soc->dcfclkv_max0p9*1000; 1317 } else if (vdd_level == dcn_bw_v_max0p9) 1318 dcf_clk = dc->dcn_soc->dcfclkv_max0p9*1000; 1319 else if (vdd_level == dcn_bw_v_nom0p8) 1320 dcf_clk = dc->dcn_soc->dcfclkv_nom0p8*1000; 1321 else if (vdd_level == dcn_bw_v_mid0p72) 1322 dcf_clk = dc->dcn_soc->dcfclkv_mid0p72*1000; 1323 else 1324 dcf_clk = dc->dcn_soc->dcfclkv_min0p65*1000; 1325 1326 DC_LOG_BANDWIDTH_CALCS("\tdcf_clk for voltage = %d\n", dcf_clk); 1327 return dcf_clk; 1328 } 1329 1330 static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks) 1331 { 1332 int i; 1333 1334 if (clks->num_levels == 0) 1335 return false; 1336 1337 for (i = 0; i < clks->num_levels; i++) 1338 /* Ensure that the result is sane */ 1339 if (clks->data[i].clocks_in_khz == 0) 1340 return false; 1341 1342 return true; 1343 } 1344 1345 void dcn_bw_update_from_pplib(struct dc *dc) 1346 { 1347 struct dc_context *ctx = dc->ctx; 1348 struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0}; 1349 bool res; 1350 unsigned vmin0p65_idx, vmid0p72_idx, vnom0p8_idx, vmax0p9_idx; 1351 1352 /* TODO: This is not the proper way to obtain fabric_and_dram_bandwidth, should be min(fclk, memclk) */ 1353 res = dm_pp_get_clock_levels_by_type_with_voltage( 1354 ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks); 1355 1356 kernel_fpu_begin(); 1357 1358 if (res) 1359 res = verify_clock_values(&fclks); 1360 1361 if (res) { 1362 ASSERT(fclks.num_levels); 1363 1364 vmin0p65_idx = 0; 1365 vmid0p72_idx = fclks.num_levels - 1366 (fclks.num_levels > 2 ? 3 : (fclks.num_levels > 1 ? 2 : 1)); 1367 vnom0p8_idx = fclks.num_levels - (fclks.num_levels > 1 ? 2 : 1); 1368 vmax0p9_idx = fclks.num_levels - 1; 1369 1370 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 1371 32 * (fclks.data[vmin0p65_idx].clocks_in_khz / 1000.0) / 1000.0; 1372 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 1373 dc->dcn_soc->number_of_channels * 1374 (fclks.data[vmid0p72_idx].clocks_in_khz / 1000.0) 1375 * ddr4_dram_factor_single_Channel / 1000.0; 1376 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 1377 dc->dcn_soc->number_of_channels * 1378 (fclks.data[vnom0p8_idx].clocks_in_khz / 1000.0) 1379 * ddr4_dram_factor_single_Channel / 1000.0; 1380 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 1381 dc->dcn_soc->number_of_channels * 1382 (fclks.data[vmax0p9_idx].clocks_in_khz / 1000.0) 1383 * ddr4_dram_factor_single_Channel / 1000.0; 1384 } else 1385 BREAK_TO_DEBUGGER(); 1386 1387 kernel_fpu_end(); 1388 1389 res = dm_pp_get_clock_levels_by_type_with_voltage( 1390 ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks); 1391 1392 kernel_fpu_begin(); 1393 1394 if (res) 1395 res = verify_clock_values(&dcfclks); 1396 1397 if (res && dcfclks.num_levels >= 3) { 1398 dc->dcn_soc->dcfclkv_min0p65 = dcfclks.data[0].clocks_in_khz / 1000.0; 1399 dc->dcn_soc->dcfclkv_mid0p72 = dcfclks.data[dcfclks.num_levels - 3].clocks_in_khz / 1000.0; 1400 dc->dcn_soc->dcfclkv_nom0p8 = dcfclks.data[dcfclks.num_levels - 2].clocks_in_khz / 1000.0; 1401 dc->dcn_soc->dcfclkv_max0p9 = dcfclks.data[dcfclks.num_levels - 1].clocks_in_khz / 1000.0; 1402 } else 1403 BREAK_TO_DEBUGGER(); 1404 1405 kernel_fpu_end(); 1406 } 1407 1408 void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc) 1409 { 1410 struct pp_smu_funcs_rv *pp = dc->res_pool->pp_smu; 1411 struct pp_smu_wm_range_sets ranges = {0}; 1412 int min_fclk_khz, min_dcfclk_khz, socclk_khz; 1413 const int overdrive = 5000000; /* 5 GHz to cover Overdrive */ 1414 1415 if (!pp->set_wm_ranges) 1416 return; 1417 1418 kernel_fpu_begin(); 1419 min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32; 1420 min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000; 1421 socclk_khz = dc->dcn_soc->socclk * 1000; 1422 kernel_fpu_end(); 1423 1424 /* Now notify PPLib/SMU about which Watermarks sets they should select 1425 * depending on DPM state they are in. And update BW MGR GFX Engine and 1426 * Memory clock member variables for Watermarks calculations for each 1427 * Watermark Set. Only one watermark set for dcn1 due to hw bug DEGVIDCN10-254. 1428 */ 1429 /* SOCCLK does not affect anytihng but writeback for DCN so for now we dont 1430 * care what the value is, hence min to overdrive level 1431 */ 1432 ranges.num_reader_wm_sets = WM_SET_COUNT; 1433 ranges.num_writer_wm_sets = WM_SET_COUNT; 1434 ranges.reader_wm_sets[0].wm_inst = WM_A; 1435 ranges.reader_wm_sets[0].min_drain_clk_khz = min_dcfclk_khz; 1436 ranges.reader_wm_sets[0].max_drain_clk_khz = overdrive; 1437 ranges.reader_wm_sets[0].min_fill_clk_khz = min_fclk_khz; 1438 ranges.reader_wm_sets[0].max_fill_clk_khz = overdrive; 1439 ranges.writer_wm_sets[0].wm_inst = WM_A; 1440 ranges.writer_wm_sets[0].min_fill_clk_khz = socclk_khz; 1441 ranges.writer_wm_sets[0].max_fill_clk_khz = overdrive; 1442 ranges.writer_wm_sets[0].min_drain_clk_khz = min_fclk_khz; 1443 ranges.writer_wm_sets[0].max_drain_clk_khz = overdrive; 1444 1445 if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) { 1446 ranges.reader_wm_sets[0].wm_inst = WM_A; 1447 ranges.reader_wm_sets[0].min_drain_clk_khz = 300000; 1448 ranges.reader_wm_sets[0].max_drain_clk_khz = 5000000; 1449 ranges.reader_wm_sets[0].min_fill_clk_khz = 800000; 1450 ranges.reader_wm_sets[0].max_fill_clk_khz = 5000000; 1451 ranges.writer_wm_sets[0].wm_inst = WM_A; 1452 ranges.writer_wm_sets[0].min_fill_clk_khz = 200000; 1453 ranges.writer_wm_sets[0].max_fill_clk_khz = 5000000; 1454 ranges.writer_wm_sets[0].min_drain_clk_khz = 800000; 1455 ranges.writer_wm_sets[0].max_drain_clk_khz = 5000000; 1456 } 1457 1458 ranges.reader_wm_sets[1] = ranges.writer_wm_sets[0]; 1459 ranges.reader_wm_sets[1].wm_inst = WM_B; 1460 1461 ranges.reader_wm_sets[2] = ranges.writer_wm_sets[0]; 1462 ranges.reader_wm_sets[2].wm_inst = WM_C; 1463 1464 ranges.reader_wm_sets[3] = ranges.writer_wm_sets[0]; 1465 ranges.reader_wm_sets[3].wm_inst = WM_D; 1466 1467 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 1468 pp->set_wm_ranges(&pp->pp_smu, &ranges); 1469 } 1470 1471 void dcn_bw_sync_calcs_and_dml(struct dc *dc) 1472 { 1473 kernel_fpu_begin(); 1474 DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %f ns\n" 1475 "sr_enter_plus_exit_time: %f ns\n" 1476 "urgent_latency: %f ns\n" 1477 "write_back_latency: %f ns\n" 1478 "percent_of_ideal_drambw_received_after_urg_latency: %f %%\n" 1479 "max_request_size: %d bytes\n" 1480 "dcfclkv_max0p9: %f kHz\n" 1481 "dcfclkv_nom0p8: %f kHz\n" 1482 "dcfclkv_mid0p72: %f kHz\n" 1483 "dcfclkv_min0p65: %f kHz\n" 1484 "max_dispclk_vmax0p9: %f kHz\n" 1485 "max_dispclk_vnom0p8: %f kHz\n" 1486 "max_dispclk_vmid0p72: %f kHz\n" 1487 "max_dispclk_vmin0p65: %f kHz\n" 1488 "max_dppclk_vmax0p9: %f kHz\n" 1489 "max_dppclk_vnom0p8: %f kHz\n" 1490 "max_dppclk_vmid0p72: %f kHz\n" 1491 "max_dppclk_vmin0p65: %f kHz\n" 1492 "socclk: %f kHz\n" 1493 "fabric_and_dram_bandwidth_vmax0p9: %f MB/s\n" 1494 "fabric_and_dram_bandwidth_vnom0p8: %f MB/s\n" 1495 "fabric_and_dram_bandwidth_vmid0p72: %f MB/s\n" 1496 "fabric_and_dram_bandwidth_vmin0p65: %f MB/s\n" 1497 "phyclkv_max0p9: %f kHz\n" 1498 "phyclkv_nom0p8: %f kHz\n" 1499 "phyclkv_mid0p72: %f kHz\n" 1500 "phyclkv_min0p65: %f kHz\n" 1501 "downspreading: %f %%\n" 1502 "round_trip_ping_latency_cycles: %d DCFCLK Cycles\n" 1503 "urgent_out_of_order_return_per_channel: %d Bytes\n" 1504 "number_of_channels: %d\n" 1505 "vmm_page_size: %d Bytes\n" 1506 "dram_clock_change_latency: %f ns\n" 1507 "return_bus_width: %d Bytes\n", 1508 dc->dcn_soc->sr_exit_time * 1000, 1509 dc->dcn_soc->sr_enter_plus_exit_time * 1000, 1510 dc->dcn_soc->urgent_latency * 1000, 1511 dc->dcn_soc->write_back_latency * 1000, 1512 dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency, 1513 dc->dcn_soc->max_request_size, 1514 dc->dcn_soc->dcfclkv_max0p9 * 1000, 1515 dc->dcn_soc->dcfclkv_nom0p8 * 1000, 1516 dc->dcn_soc->dcfclkv_mid0p72 * 1000, 1517 dc->dcn_soc->dcfclkv_min0p65 * 1000, 1518 dc->dcn_soc->max_dispclk_vmax0p9 * 1000, 1519 dc->dcn_soc->max_dispclk_vnom0p8 * 1000, 1520 dc->dcn_soc->max_dispclk_vmid0p72 * 1000, 1521 dc->dcn_soc->max_dispclk_vmin0p65 * 1000, 1522 dc->dcn_soc->max_dppclk_vmax0p9 * 1000, 1523 dc->dcn_soc->max_dppclk_vnom0p8 * 1000, 1524 dc->dcn_soc->max_dppclk_vmid0p72 * 1000, 1525 dc->dcn_soc->max_dppclk_vmin0p65 * 1000, 1526 dc->dcn_soc->socclk * 1000, 1527 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 * 1000, 1528 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 * 1000, 1529 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 * 1000, 1530 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000, 1531 dc->dcn_soc->phyclkv_max0p9 * 1000, 1532 dc->dcn_soc->phyclkv_nom0p8 * 1000, 1533 dc->dcn_soc->phyclkv_mid0p72 * 1000, 1534 dc->dcn_soc->phyclkv_min0p65 * 1000, 1535 dc->dcn_soc->downspreading * 100, 1536 dc->dcn_soc->round_trip_ping_latency_cycles, 1537 dc->dcn_soc->urgent_out_of_order_return_per_channel, 1538 dc->dcn_soc->number_of_channels, 1539 dc->dcn_soc->vmm_page_size, 1540 dc->dcn_soc->dram_clock_change_latency * 1000, 1541 dc->dcn_soc->return_bus_width); 1542 DC_LOG_BANDWIDTH_CALCS("rob_buffer_size_in_kbyte: %f\n" 1543 "det_buffer_size_in_kbyte: %f\n" 1544 "dpp_output_buffer_pixels: %f\n" 1545 "opp_output_buffer_lines: %f\n" 1546 "pixel_chunk_size_in_kbyte: %f\n" 1547 "pte_enable: %d\n" 1548 "pte_chunk_size: %d kbytes\n" 1549 "meta_chunk_size: %d kbytes\n" 1550 "writeback_chunk_size: %d kbytes\n" 1551 "odm_capability: %d\n" 1552 "dsc_capability: %d\n" 1553 "line_buffer_size: %d bits\n" 1554 "max_line_buffer_lines: %d\n" 1555 "is_line_buffer_bpp_fixed: %d\n" 1556 "line_buffer_fixed_bpp: %d\n" 1557 "writeback_luma_buffer_size: %d kbytes\n" 1558 "writeback_chroma_buffer_size: %d kbytes\n" 1559 "max_num_dpp: %d\n" 1560 "max_num_writeback: %d\n" 1561 "max_dchub_topscl_throughput: %d pixels/dppclk\n" 1562 "max_pscl_tolb_throughput: %d pixels/dppclk\n" 1563 "max_lb_tovscl_throughput: %d pixels/dppclk\n" 1564 "max_vscl_tohscl_throughput: %d pixels/dppclk\n" 1565 "max_hscl_ratio: %f\n" 1566 "max_vscl_ratio: %f\n" 1567 "max_hscl_taps: %d\n" 1568 "max_vscl_taps: %d\n" 1569 "pte_buffer_size_in_requests: %d\n" 1570 "dispclk_ramping_margin: %f %%\n" 1571 "under_scan_factor: %f %%\n" 1572 "max_inter_dcn_tile_repeaters: %d\n" 1573 "can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one: %d\n" 1574 "bug_forcing_luma_and_chroma_request_to_same_size_fixed: %d\n" 1575 "dcfclk_cstate_latency: %d\n", 1576 dc->dcn_ip->rob_buffer_size_in_kbyte, 1577 dc->dcn_ip->det_buffer_size_in_kbyte, 1578 dc->dcn_ip->dpp_output_buffer_pixels, 1579 dc->dcn_ip->opp_output_buffer_lines, 1580 dc->dcn_ip->pixel_chunk_size_in_kbyte, 1581 dc->dcn_ip->pte_enable, 1582 dc->dcn_ip->pte_chunk_size, 1583 dc->dcn_ip->meta_chunk_size, 1584 dc->dcn_ip->writeback_chunk_size, 1585 dc->dcn_ip->odm_capability, 1586 dc->dcn_ip->dsc_capability, 1587 dc->dcn_ip->line_buffer_size, 1588 dc->dcn_ip->max_line_buffer_lines, 1589 dc->dcn_ip->is_line_buffer_bpp_fixed, 1590 dc->dcn_ip->line_buffer_fixed_bpp, 1591 dc->dcn_ip->writeback_luma_buffer_size, 1592 dc->dcn_ip->writeback_chroma_buffer_size, 1593 dc->dcn_ip->max_num_dpp, 1594 dc->dcn_ip->max_num_writeback, 1595 dc->dcn_ip->max_dchub_topscl_throughput, 1596 dc->dcn_ip->max_pscl_tolb_throughput, 1597 dc->dcn_ip->max_lb_tovscl_throughput, 1598 dc->dcn_ip->max_vscl_tohscl_throughput, 1599 dc->dcn_ip->max_hscl_ratio, 1600 dc->dcn_ip->max_vscl_ratio, 1601 dc->dcn_ip->max_hscl_taps, 1602 dc->dcn_ip->max_vscl_taps, 1603 dc->dcn_ip->pte_buffer_size_in_requests, 1604 dc->dcn_ip->dispclk_ramping_margin, 1605 dc->dcn_ip->under_scan_factor * 100, 1606 dc->dcn_ip->max_inter_dcn_tile_repeaters, 1607 dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one, 1608 dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed, 1609 dc->dcn_ip->dcfclk_cstate_latency); 1610 1611 dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time; 1612 dc->dml.soc.sr_enter_plus_exit_time_us = dc->dcn_soc->sr_enter_plus_exit_time; 1613 dc->dml.soc.urgent_latency_us = dc->dcn_soc->urgent_latency; 1614 dc->dml.soc.writeback_latency_us = dc->dcn_soc->write_back_latency; 1615 dc->dml.soc.ideal_dram_bw_after_urgent_percent = 1616 dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency; 1617 dc->dml.soc.max_request_size_bytes = dc->dcn_soc->max_request_size; 1618 dc->dml.soc.downspread_percent = dc->dcn_soc->downspreading; 1619 dc->dml.soc.round_trip_ping_latency_dcfclk_cycles = 1620 dc->dcn_soc->round_trip_ping_latency_cycles; 1621 dc->dml.soc.urgent_out_of_order_return_per_channel_bytes = 1622 dc->dcn_soc->urgent_out_of_order_return_per_channel; 1623 dc->dml.soc.num_chans = dc->dcn_soc->number_of_channels; 1624 dc->dml.soc.vmm_page_size_bytes = dc->dcn_soc->vmm_page_size; 1625 dc->dml.soc.dram_clock_change_latency_us = dc->dcn_soc->dram_clock_change_latency; 1626 dc->dml.soc.return_bus_width_bytes = dc->dcn_soc->return_bus_width; 1627 1628 dc->dml.ip.rob_buffer_size_kbytes = dc->dcn_ip->rob_buffer_size_in_kbyte; 1629 dc->dml.ip.det_buffer_size_kbytes = dc->dcn_ip->det_buffer_size_in_kbyte; 1630 dc->dml.ip.dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels; 1631 dc->dml.ip.opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines; 1632 dc->dml.ip.pixel_chunk_size_kbytes = dc->dcn_ip->pixel_chunk_size_in_kbyte; 1633 dc->dml.ip.pte_enable = dc->dcn_ip->pte_enable == dcn_bw_yes; 1634 dc->dml.ip.pte_chunk_size_kbytes = dc->dcn_ip->pte_chunk_size; 1635 dc->dml.ip.meta_chunk_size_kbytes = dc->dcn_ip->meta_chunk_size; 1636 dc->dml.ip.writeback_chunk_size_kbytes = dc->dcn_ip->writeback_chunk_size; 1637 dc->dml.ip.line_buffer_size_bits = dc->dcn_ip->line_buffer_size; 1638 dc->dml.ip.max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines; 1639 dc->dml.ip.IsLineBufferBppFixed = dc->dcn_ip->is_line_buffer_bpp_fixed == dcn_bw_yes; 1640 dc->dml.ip.LineBufferFixedBpp = dc->dcn_ip->line_buffer_fixed_bpp; 1641 dc->dml.ip.writeback_luma_buffer_size_kbytes = dc->dcn_ip->writeback_luma_buffer_size; 1642 dc->dml.ip.writeback_chroma_buffer_size_kbytes = dc->dcn_ip->writeback_chroma_buffer_size; 1643 dc->dml.ip.max_num_dpp = dc->dcn_ip->max_num_dpp; 1644 dc->dml.ip.max_num_wb = dc->dcn_ip->max_num_writeback; 1645 dc->dml.ip.max_dchub_pscl_bw_pix_per_clk = dc->dcn_ip->max_dchub_topscl_throughput; 1646 dc->dml.ip.max_pscl_lb_bw_pix_per_clk = dc->dcn_ip->max_pscl_tolb_throughput; 1647 dc->dml.ip.max_lb_vscl_bw_pix_per_clk = dc->dcn_ip->max_lb_tovscl_throughput; 1648 dc->dml.ip.max_vscl_hscl_bw_pix_per_clk = dc->dcn_ip->max_vscl_tohscl_throughput; 1649 dc->dml.ip.max_hscl_ratio = dc->dcn_ip->max_hscl_ratio; 1650 dc->dml.ip.max_vscl_ratio = dc->dcn_ip->max_vscl_ratio; 1651 dc->dml.ip.max_hscl_taps = dc->dcn_ip->max_hscl_taps; 1652 dc->dml.ip.max_vscl_taps = dc->dcn_ip->max_vscl_taps; 1653 /*pte_buffer_size_in_requests missing in dml*/ 1654 dc->dml.ip.dispclk_ramp_margin_percent = dc->dcn_ip->dispclk_ramping_margin; 1655 dc->dml.ip.underscan_factor = dc->dcn_ip->under_scan_factor; 1656 dc->dml.ip.max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters; 1657 dc->dml.ip.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 1658 dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes; 1659 dc->dml.ip.bug_forcing_LC_req_same_size_fixed = 1660 dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes; 1661 dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip->dcfclk_cstate_latency; 1662 kernel_fpu_end(); 1663 } 1664