1*b843c749SSergey Zigachev /* Copyright 2015 Advanced Micro Devices, Inc. */
2*b843c749SSergey Zigachev #include "dm_services.h"
3*b843c749SSergey Zigachev #include "dc.h"
4*b843c749SSergey Zigachev #include "dc_link_dp.h"
5*b843c749SSergey Zigachev #include "dm_helpers.h"
6*b843c749SSergey Zigachev #include "opp.h"
7*b843c749SSergey Zigachev
8*b843c749SSergey Zigachev #include "inc/core_types.h"
9*b843c749SSergey Zigachev #include "link_hwss.h"
10*b843c749SSergey Zigachev #include "dc_link_ddc.h"
11*b843c749SSergey Zigachev #include "core_status.h"
12*b843c749SSergey Zigachev #include "dpcd_defs.h"
13*b843c749SSergey Zigachev
14*b843c749SSergey Zigachev #include "resource.h"
15*b843c749SSergey Zigachev #define DC_LOGGER \
16*b843c749SSergey Zigachev link->ctx->logger
17*b843c749SSergey Zigachev
18*b843c749SSergey Zigachev /* maximum pre emphasis level allowed for each voltage swing level*/
19*b843c749SSergey Zigachev static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
20*b843c749SSergey Zigachev PRE_EMPHASIS_LEVEL3,
21*b843c749SSergey Zigachev PRE_EMPHASIS_LEVEL2,
22*b843c749SSergey Zigachev PRE_EMPHASIS_LEVEL1,
23*b843c749SSergey Zigachev PRE_EMPHASIS_DISABLED };
24*b843c749SSergey Zigachev
25*b843c749SSergey Zigachev enum {
26*b843c749SSergey Zigachev POST_LT_ADJ_REQ_LIMIT = 6,
27*b843c749SSergey Zigachev POST_LT_ADJ_REQ_TIMEOUT = 200
28*b843c749SSergey Zigachev };
29*b843c749SSergey Zigachev
30*b843c749SSergey Zigachev enum {
31*b843c749SSergey Zigachev LINK_TRAINING_MAX_RETRY_COUNT = 5,
32*b843c749SSergey Zigachev /* to avoid infinite loop where-in the receiver
33*b843c749SSergey Zigachev * switches between different VS
34*b843c749SSergey Zigachev */
35*b843c749SSergey Zigachev LINK_TRAINING_MAX_CR_RETRY = 100
36*b843c749SSergey Zigachev };
37*b843c749SSergey Zigachev
38*b843c749SSergey Zigachev static bool decide_fallback_link_setting(
39*b843c749SSergey Zigachev struct dc_link_settings initial_link_settings,
40*b843c749SSergey Zigachev struct dc_link_settings *current_link_setting,
41*b843c749SSergey Zigachev enum link_training_result training_result);
42*b843c749SSergey Zigachev static struct dc_link_settings get_common_supported_link_settings(
43*b843c749SSergey Zigachev struct dc_link_settings link_setting_a,
44*b843c749SSergey Zigachev struct dc_link_settings link_setting_b);
45*b843c749SSergey Zigachev
wait_for_training_aux_rd_interval(struct dc_link * link,uint32_t default_wait_in_micro_secs)46*b843c749SSergey Zigachev static void wait_for_training_aux_rd_interval(
47*b843c749SSergey Zigachev struct dc_link *link,
48*b843c749SSergey Zigachev uint32_t default_wait_in_micro_secs)
49*b843c749SSergey Zigachev {
50*b843c749SSergey Zigachev union training_aux_rd_interval training_rd_interval;
51*b843c749SSergey Zigachev
52*b843c749SSergey Zigachev /* overwrite the delay if rev > 1.1*/
53*b843c749SSergey Zigachev if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
54*b843c749SSergey Zigachev /* DP 1.2 or later - retrieve delay through
55*b843c749SSergey Zigachev * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
56*b843c749SSergey Zigachev core_link_read_dpcd(
57*b843c749SSergey Zigachev link,
58*b843c749SSergey Zigachev DP_TRAINING_AUX_RD_INTERVAL,
59*b843c749SSergey Zigachev (uint8_t *)&training_rd_interval,
60*b843c749SSergey Zigachev sizeof(training_rd_interval));
61*b843c749SSergey Zigachev
62*b843c749SSergey Zigachev if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
63*b843c749SSergey Zigachev default_wait_in_micro_secs =
64*b843c749SSergey Zigachev training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
65*b843c749SSergey Zigachev }
66*b843c749SSergey Zigachev
67*b843c749SSergey Zigachev udelay(default_wait_in_micro_secs);
68*b843c749SSergey Zigachev
69*b843c749SSergey Zigachev DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
70*b843c749SSergey Zigachev __func__,
71*b843c749SSergey Zigachev default_wait_in_micro_secs);
72*b843c749SSergey Zigachev }
73*b843c749SSergey Zigachev
dpcd_set_training_pattern(struct dc_link * link,union dpcd_training_pattern dpcd_pattern)74*b843c749SSergey Zigachev static void dpcd_set_training_pattern(
75*b843c749SSergey Zigachev struct dc_link *link,
76*b843c749SSergey Zigachev union dpcd_training_pattern dpcd_pattern)
77*b843c749SSergey Zigachev {
78*b843c749SSergey Zigachev core_link_write_dpcd(
79*b843c749SSergey Zigachev link,
80*b843c749SSergey Zigachev DP_TRAINING_PATTERN_SET,
81*b843c749SSergey Zigachev &dpcd_pattern.raw,
82*b843c749SSergey Zigachev 1);
83*b843c749SSergey Zigachev
84*b843c749SSergey Zigachev DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
85*b843c749SSergey Zigachev __func__,
86*b843c749SSergey Zigachev DP_TRAINING_PATTERN_SET,
87*b843c749SSergey Zigachev dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
88*b843c749SSergey Zigachev }
89*b843c749SSergey Zigachev
dpcd_set_link_settings(struct dc_link * link,const struct link_training_settings * lt_settings)90*b843c749SSergey Zigachev static void dpcd_set_link_settings(
91*b843c749SSergey Zigachev struct dc_link *link,
92*b843c749SSergey Zigachev const struct link_training_settings *lt_settings)
93*b843c749SSergey Zigachev {
94*b843c749SSergey Zigachev uint8_t rate = (uint8_t)
95*b843c749SSergey Zigachev (lt_settings->link_settings.link_rate);
96*b843c749SSergey Zigachev
97*b843c749SSergey Zigachev union down_spread_ctrl downspread = { {0} };
98*b843c749SSergey Zigachev union lane_count_set lane_count_set = { {0} };
99*b843c749SSergey Zigachev uint8_t link_set_buffer[2];
100*b843c749SSergey Zigachev
101*b843c749SSergey Zigachev downspread.raw = (uint8_t)
102*b843c749SSergey Zigachev (lt_settings->link_settings.link_spread);
103*b843c749SSergey Zigachev
104*b843c749SSergey Zigachev lane_count_set.bits.LANE_COUNT_SET =
105*b843c749SSergey Zigachev lt_settings->link_settings.lane_count;
106*b843c749SSergey Zigachev
107*b843c749SSergey Zigachev lane_count_set.bits.ENHANCED_FRAMING = 1;
108*b843c749SSergey Zigachev
109*b843c749SSergey Zigachev lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
110*b843c749SSergey Zigachev link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
111*b843c749SSergey Zigachev
112*b843c749SSergey Zigachev link_set_buffer[0] = rate;
113*b843c749SSergey Zigachev link_set_buffer[1] = lane_count_set.raw;
114*b843c749SSergey Zigachev
115*b843c749SSergey Zigachev core_link_write_dpcd(link, DP_LINK_BW_SET,
116*b843c749SSergey Zigachev link_set_buffer, 2);
117*b843c749SSergey Zigachev core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
118*b843c749SSergey Zigachev &downspread.raw, sizeof(downspread));
119*b843c749SSergey Zigachev
120*b843c749SSergey Zigachev DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x\n %x spread = %x\n",
121*b843c749SSergey Zigachev __func__,
122*b843c749SSergey Zigachev DP_LINK_BW_SET,
123*b843c749SSergey Zigachev lt_settings->link_settings.link_rate,
124*b843c749SSergey Zigachev DP_LANE_COUNT_SET,
125*b843c749SSergey Zigachev lt_settings->link_settings.lane_count,
126*b843c749SSergey Zigachev DP_DOWNSPREAD_CTRL,
127*b843c749SSergey Zigachev lt_settings->link_settings.link_spread);
128*b843c749SSergey Zigachev
129*b843c749SSergey Zigachev }
130*b843c749SSergey Zigachev
131*b843c749SSergey Zigachev static enum dpcd_training_patterns
hw_training_pattern_to_dpcd_training_pattern(struct dc_link * link,enum hw_dp_training_pattern pattern)132*b843c749SSergey Zigachev hw_training_pattern_to_dpcd_training_pattern(
133*b843c749SSergey Zigachev struct dc_link *link,
134*b843c749SSergey Zigachev enum hw_dp_training_pattern pattern)
135*b843c749SSergey Zigachev {
136*b843c749SSergey Zigachev enum dpcd_training_patterns dpcd_tr_pattern =
137*b843c749SSergey Zigachev DPCD_TRAINING_PATTERN_VIDEOIDLE;
138*b843c749SSergey Zigachev
139*b843c749SSergey Zigachev switch (pattern) {
140*b843c749SSergey Zigachev case HW_DP_TRAINING_PATTERN_1:
141*b843c749SSergey Zigachev dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
142*b843c749SSergey Zigachev break;
143*b843c749SSergey Zigachev case HW_DP_TRAINING_PATTERN_2:
144*b843c749SSergey Zigachev dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
145*b843c749SSergey Zigachev break;
146*b843c749SSergey Zigachev case HW_DP_TRAINING_PATTERN_3:
147*b843c749SSergey Zigachev dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
148*b843c749SSergey Zigachev break;
149*b843c749SSergey Zigachev case HW_DP_TRAINING_PATTERN_4:
150*b843c749SSergey Zigachev dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
151*b843c749SSergey Zigachev break;
152*b843c749SSergey Zigachev default:
153*b843c749SSergey Zigachev ASSERT(0);
154*b843c749SSergey Zigachev DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
155*b843c749SSergey Zigachev __func__, pattern);
156*b843c749SSergey Zigachev break;
157*b843c749SSergey Zigachev }
158*b843c749SSergey Zigachev
159*b843c749SSergey Zigachev return dpcd_tr_pattern;
160*b843c749SSergey Zigachev
161*b843c749SSergey Zigachev }
162*b843c749SSergey Zigachev
dpcd_set_lt_pattern_and_lane_settings(struct dc_link * link,const struct link_training_settings * lt_settings,enum hw_dp_training_pattern pattern)163*b843c749SSergey Zigachev static void dpcd_set_lt_pattern_and_lane_settings(
164*b843c749SSergey Zigachev struct dc_link *link,
165*b843c749SSergey Zigachev const struct link_training_settings *lt_settings,
166*b843c749SSergey Zigachev enum hw_dp_training_pattern pattern)
167*b843c749SSergey Zigachev {
168*b843c749SSergey Zigachev union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
169*b843c749SSergey Zigachev const uint32_t dpcd_base_lt_offset =
170*b843c749SSergey Zigachev DP_TRAINING_PATTERN_SET;
171*b843c749SSergey Zigachev uint8_t dpcd_lt_buffer[5] = {0};
172*b843c749SSergey Zigachev union dpcd_training_pattern dpcd_pattern = { {0} };
173*b843c749SSergey Zigachev uint32_t lane;
174*b843c749SSergey Zigachev uint32_t size_in_bytes;
175*b843c749SSergey Zigachev bool edp_workaround = false; /* TODO link_prop.INTERNAL */
176*b843c749SSergey Zigachev
177*b843c749SSergey Zigachev /*****************************************************************
178*b843c749SSergey Zigachev * DpcdAddress_TrainingPatternSet
179*b843c749SSergey Zigachev *****************************************************************/
180*b843c749SSergey Zigachev dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
181*b843c749SSergey Zigachev hw_training_pattern_to_dpcd_training_pattern(link, pattern);
182*b843c749SSergey Zigachev
183*b843c749SSergey Zigachev dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - dpcd_base_lt_offset]
184*b843c749SSergey Zigachev = dpcd_pattern.raw;
185*b843c749SSergey Zigachev
186*b843c749SSergey Zigachev DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
187*b843c749SSergey Zigachev __func__,
188*b843c749SSergey Zigachev DP_TRAINING_PATTERN_SET,
189*b843c749SSergey Zigachev dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
190*b843c749SSergey Zigachev
191*b843c749SSergey Zigachev /*****************************************************************
192*b843c749SSergey Zigachev * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
193*b843c749SSergey Zigachev *****************************************************************/
194*b843c749SSergey Zigachev for (lane = 0; lane <
195*b843c749SSergey Zigachev (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
196*b843c749SSergey Zigachev
197*b843c749SSergey Zigachev dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
198*b843c749SSergey Zigachev (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
199*b843c749SSergey Zigachev dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
200*b843c749SSergey Zigachev (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
201*b843c749SSergey Zigachev
202*b843c749SSergey Zigachev dpcd_lane[lane].bits.MAX_SWING_REACHED =
203*b843c749SSergey Zigachev (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
204*b843c749SSergey Zigachev VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
205*b843c749SSergey Zigachev dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
206*b843c749SSergey Zigachev (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
207*b843c749SSergey Zigachev PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
208*b843c749SSergey Zigachev }
209*b843c749SSergey Zigachev
210*b843c749SSergey Zigachev /* concatinate everything into one buffer*/
211*b843c749SSergey Zigachev
212*b843c749SSergey Zigachev size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
213*b843c749SSergey Zigachev
214*b843c749SSergey Zigachev // 0x00103 - 0x00102
215*b843c749SSergey Zigachev memmove(
216*b843c749SSergey Zigachev &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - dpcd_base_lt_offset],
217*b843c749SSergey Zigachev dpcd_lane,
218*b843c749SSergey Zigachev size_in_bytes);
219*b843c749SSergey Zigachev
220*b843c749SSergey Zigachev DC_LOG_HW_LINK_TRAINING("%s:\n %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
221*b843c749SSergey Zigachev __func__,
222*b843c749SSergey Zigachev DP_TRAINING_LANE0_SET,
223*b843c749SSergey Zigachev dpcd_lane[0].bits.VOLTAGE_SWING_SET,
224*b843c749SSergey Zigachev dpcd_lane[0].bits.PRE_EMPHASIS_SET,
225*b843c749SSergey Zigachev dpcd_lane[0].bits.MAX_SWING_REACHED,
226*b843c749SSergey Zigachev dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
227*b843c749SSergey Zigachev
228*b843c749SSergey Zigachev if (edp_workaround) {
229*b843c749SSergey Zigachev /* for eDP write in 2 parts because the 5-byte burst is
230*b843c749SSergey Zigachev * causing issues on some eDP panels (EPR#366724)
231*b843c749SSergey Zigachev */
232*b843c749SSergey Zigachev core_link_write_dpcd(
233*b843c749SSergey Zigachev link,
234*b843c749SSergey Zigachev DP_TRAINING_PATTERN_SET,
235*b843c749SSergey Zigachev &dpcd_pattern.raw,
236*b843c749SSergey Zigachev sizeof(dpcd_pattern.raw));
237*b843c749SSergey Zigachev
238*b843c749SSergey Zigachev core_link_write_dpcd(
239*b843c749SSergey Zigachev link,
240*b843c749SSergey Zigachev DP_TRAINING_LANE0_SET,
241*b843c749SSergey Zigachev (uint8_t *)(dpcd_lane),
242*b843c749SSergey Zigachev size_in_bytes);
243*b843c749SSergey Zigachev
244*b843c749SSergey Zigachev } else
245*b843c749SSergey Zigachev /* write it all in (1 + number-of-lanes)-byte burst*/
246*b843c749SSergey Zigachev core_link_write_dpcd(
247*b843c749SSergey Zigachev link,
248*b843c749SSergey Zigachev dpcd_base_lt_offset,
249*b843c749SSergey Zigachev dpcd_lt_buffer,
250*b843c749SSergey Zigachev size_in_bytes + sizeof(dpcd_pattern.raw));
251*b843c749SSergey Zigachev
252*b843c749SSergey Zigachev link->cur_lane_setting = lt_settings->lane_settings[0];
253*b843c749SSergey Zigachev }
254*b843c749SSergey Zigachev
is_cr_done(enum dc_lane_count ln_count,union lane_status * dpcd_lane_status)255*b843c749SSergey Zigachev static bool is_cr_done(enum dc_lane_count ln_count,
256*b843c749SSergey Zigachev union lane_status *dpcd_lane_status)
257*b843c749SSergey Zigachev {
258*b843c749SSergey Zigachev bool done = true;
259*b843c749SSergey Zigachev uint32_t lane;
260*b843c749SSergey Zigachev /*LANEx_CR_DONE bits All 1's?*/
261*b843c749SSergey Zigachev for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
262*b843c749SSergey Zigachev if (!dpcd_lane_status[lane].bits.CR_DONE_0)
263*b843c749SSergey Zigachev done = false;
264*b843c749SSergey Zigachev }
265*b843c749SSergey Zigachev return done;
266*b843c749SSergey Zigachev
267*b843c749SSergey Zigachev }
268*b843c749SSergey Zigachev
is_ch_eq_done(enum dc_lane_count ln_count,union lane_status * dpcd_lane_status,union lane_align_status_updated * lane_status_updated)269*b843c749SSergey Zigachev static bool is_ch_eq_done(enum dc_lane_count ln_count,
270*b843c749SSergey Zigachev union lane_status *dpcd_lane_status,
271*b843c749SSergey Zigachev union lane_align_status_updated *lane_status_updated)
272*b843c749SSergey Zigachev {
273*b843c749SSergey Zigachev bool done = true;
274*b843c749SSergey Zigachev uint32_t lane;
275*b843c749SSergey Zigachev if (!lane_status_updated->bits.INTERLANE_ALIGN_DONE)
276*b843c749SSergey Zigachev done = false;
277*b843c749SSergey Zigachev else {
278*b843c749SSergey Zigachev for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
279*b843c749SSergey Zigachev if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0 ||
280*b843c749SSergey Zigachev !dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
281*b843c749SSergey Zigachev done = false;
282*b843c749SSergey Zigachev }
283*b843c749SSergey Zigachev }
284*b843c749SSergey Zigachev return done;
285*b843c749SSergey Zigachev
286*b843c749SSergey Zigachev }
287*b843c749SSergey Zigachev
update_drive_settings(struct link_training_settings * dest,struct link_training_settings src)288*b843c749SSergey Zigachev static void update_drive_settings(
289*b843c749SSergey Zigachev struct link_training_settings *dest,
290*b843c749SSergey Zigachev struct link_training_settings src)
291*b843c749SSergey Zigachev {
292*b843c749SSergey Zigachev uint32_t lane;
293*b843c749SSergey Zigachev for (lane = 0; lane < src.link_settings.lane_count; lane++) {
294*b843c749SSergey Zigachev dest->lane_settings[lane].VOLTAGE_SWING =
295*b843c749SSergey Zigachev src.lane_settings[lane].VOLTAGE_SWING;
296*b843c749SSergey Zigachev dest->lane_settings[lane].PRE_EMPHASIS =
297*b843c749SSergey Zigachev src.lane_settings[lane].PRE_EMPHASIS;
298*b843c749SSergey Zigachev dest->lane_settings[lane].POST_CURSOR2 =
299*b843c749SSergey Zigachev src.lane_settings[lane].POST_CURSOR2;
300*b843c749SSergey Zigachev }
301*b843c749SSergey Zigachev }
302*b843c749SSergey Zigachev
get_nibble_at_index(const uint8_t * buf,uint32_t index)303*b843c749SSergey Zigachev static uint8_t get_nibble_at_index(const uint8_t *buf,
304*b843c749SSergey Zigachev uint32_t index)
305*b843c749SSergey Zigachev {
306*b843c749SSergey Zigachev uint8_t nibble;
307*b843c749SSergey Zigachev nibble = buf[index / 2];
308*b843c749SSergey Zigachev
309*b843c749SSergey Zigachev if (index % 2)
310*b843c749SSergey Zigachev nibble >>= 4;
311*b843c749SSergey Zigachev else
312*b843c749SSergey Zigachev nibble &= 0x0F;
313*b843c749SSergey Zigachev
314*b843c749SSergey Zigachev return nibble;
315*b843c749SSergey Zigachev }
316*b843c749SSergey Zigachev
get_max_pre_emphasis_for_voltage_swing(enum dc_voltage_swing voltage)317*b843c749SSergey Zigachev static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
318*b843c749SSergey Zigachev enum dc_voltage_swing voltage)
319*b843c749SSergey Zigachev {
320*b843c749SSergey Zigachev enum dc_pre_emphasis pre_emphasis;
321*b843c749SSergey Zigachev pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
322*b843c749SSergey Zigachev
323*b843c749SSergey Zigachev if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
324*b843c749SSergey Zigachev pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
325*b843c749SSergey Zigachev
326*b843c749SSergey Zigachev return pre_emphasis;
327*b843c749SSergey Zigachev
328*b843c749SSergey Zigachev }
329*b843c749SSergey Zigachev
find_max_drive_settings(const struct link_training_settings * link_training_setting,struct link_training_settings * max_lt_setting)330*b843c749SSergey Zigachev static void find_max_drive_settings(
331*b843c749SSergey Zigachev const struct link_training_settings *link_training_setting,
332*b843c749SSergey Zigachev struct link_training_settings *max_lt_setting)
333*b843c749SSergey Zigachev {
334*b843c749SSergey Zigachev uint32_t lane;
335*b843c749SSergey Zigachev struct dc_lane_settings max_requested;
336*b843c749SSergey Zigachev
337*b843c749SSergey Zigachev max_requested.VOLTAGE_SWING =
338*b843c749SSergey Zigachev link_training_setting->
339*b843c749SSergey Zigachev lane_settings[0].VOLTAGE_SWING;
340*b843c749SSergey Zigachev max_requested.PRE_EMPHASIS =
341*b843c749SSergey Zigachev link_training_setting->
342*b843c749SSergey Zigachev lane_settings[0].PRE_EMPHASIS;
343*b843c749SSergey Zigachev /*max_requested.postCursor2 =
344*b843c749SSergey Zigachev * link_training_setting->laneSettings[0].postCursor2;*/
345*b843c749SSergey Zigachev
346*b843c749SSergey Zigachev /* Determine what the maximum of the requested settings are*/
347*b843c749SSergey Zigachev for (lane = 1; lane < link_training_setting->link_settings.lane_count;
348*b843c749SSergey Zigachev lane++) {
349*b843c749SSergey Zigachev if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
350*b843c749SSergey Zigachev max_requested.VOLTAGE_SWING)
351*b843c749SSergey Zigachev
352*b843c749SSergey Zigachev max_requested.VOLTAGE_SWING =
353*b843c749SSergey Zigachev link_training_setting->
354*b843c749SSergey Zigachev lane_settings[lane].VOLTAGE_SWING;
355*b843c749SSergey Zigachev
356*b843c749SSergey Zigachev if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
357*b843c749SSergey Zigachev max_requested.PRE_EMPHASIS)
358*b843c749SSergey Zigachev max_requested.PRE_EMPHASIS =
359*b843c749SSergey Zigachev link_training_setting->
360*b843c749SSergey Zigachev lane_settings[lane].PRE_EMPHASIS;
361*b843c749SSergey Zigachev
362*b843c749SSergey Zigachev /*
363*b843c749SSergey Zigachev if (link_training_setting->laneSettings[lane].postCursor2 >
364*b843c749SSergey Zigachev max_requested.postCursor2)
365*b843c749SSergey Zigachev {
366*b843c749SSergey Zigachev max_requested.postCursor2 =
367*b843c749SSergey Zigachev link_training_setting->laneSettings[lane].postCursor2;
368*b843c749SSergey Zigachev }
369*b843c749SSergey Zigachev */
370*b843c749SSergey Zigachev }
371*b843c749SSergey Zigachev
372*b843c749SSergey Zigachev /* make sure the requested settings are
373*b843c749SSergey Zigachev * not higher than maximum settings*/
374*b843c749SSergey Zigachev if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
375*b843c749SSergey Zigachev max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
376*b843c749SSergey Zigachev
377*b843c749SSergey Zigachev if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
378*b843c749SSergey Zigachev max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
379*b843c749SSergey Zigachev /*
380*b843c749SSergey Zigachev if (max_requested.postCursor2 > PostCursor2_MaxLevel)
381*b843c749SSergey Zigachev max_requested.postCursor2 = PostCursor2_MaxLevel;
382*b843c749SSergey Zigachev */
383*b843c749SSergey Zigachev
384*b843c749SSergey Zigachev /* make sure the pre-emphasis matches the voltage swing*/
385*b843c749SSergey Zigachev if (max_requested.PRE_EMPHASIS >
386*b843c749SSergey Zigachev get_max_pre_emphasis_for_voltage_swing(
387*b843c749SSergey Zigachev max_requested.VOLTAGE_SWING))
388*b843c749SSergey Zigachev max_requested.PRE_EMPHASIS =
389*b843c749SSergey Zigachev get_max_pre_emphasis_for_voltage_swing(
390*b843c749SSergey Zigachev max_requested.VOLTAGE_SWING);
391*b843c749SSergey Zigachev
392*b843c749SSergey Zigachev /*
393*b843c749SSergey Zigachev * Post Cursor2 levels are completely independent from
394*b843c749SSergey Zigachev * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
395*b843c749SSergey Zigachev * can only be applied to each allowable combination of voltage
396*b843c749SSergey Zigachev * swing and pre-emphasis levels */
397*b843c749SSergey Zigachev /* if ( max_requested.postCursor2 >
398*b843c749SSergey Zigachev * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
399*b843c749SSergey Zigachev * max_requested.postCursor2 =
400*b843c749SSergey Zigachev * getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
401*b843c749SSergey Zigachev */
402*b843c749SSergey Zigachev
403*b843c749SSergey Zigachev max_lt_setting->link_settings.link_rate =
404*b843c749SSergey Zigachev link_training_setting->link_settings.link_rate;
405*b843c749SSergey Zigachev max_lt_setting->link_settings.lane_count =
406*b843c749SSergey Zigachev link_training_setting->link_settings.lane_count;
407*b843c749SSergey Zigachev max_lt_setting->link_settings.link_spread =
408*b843c749SSergey Zigachev link_training_setting->link_settings.link_spread;
409*b843c749SSergey Zigachev
410*b843c749SSergey Zigachev for (lane = 0; lane <
411*b843c749SSergey Zigachev link_training_setting->link_settings.lane_count;
412*b843c749SSergey Zigachev lane++) {
413*b843c749SSergey Zigachev max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
414*b843c749SSergey Zigachev max_requested.VOLTAGE_SWING;
415*b843c749SSergey Zigachev max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
416*b843c749SSergey Zigachev max_requested.PRE_EMPHASIS;
417*b843c749SSergey Zigachev /*max_lt_setting->laneSettings[lane].postCursor2 =
418*b843c749SSergey Zigachev * max_requested.postCursor2;
419*b843c749SSergey Zigachev */
420*b843c749SSergey Zigachev }
421*b843c749SSergey Zigachev
422*b843c749SSergey Zigachev }
423*b843c749SSergey Zigachev
get_lane_status_and_drive_settings(struct dc_link * link,const struct link_training_settings * link_training_setting,union lane_status * ln_status,union lane_align_status_updated * ln_status_updated,struct link_training_settings * req_settings)424*b843c749SSergey Zigachev static void get_lane_status_and_drive_settings(
425*b843c749SSergey Zigachev struct dc_link *link,
426*b843c749SSergey Zigachev const struct link_training_settings *link_training_setting,
427*b843c749SSergey Zigachev union lane_status *ln_status,
428*b843c749SSergey Zigachev union lane_align_status_updated *ln_status_updated,
429*b843c749SSergey Zigachev struct link_training_settings *req_settings)
430*b843c749SSergey Zigachev {
431*b843c749SSergey Zigachev uint8_t dpcd_buf[6] = {0};
432*b843c749SSergey Zigachev union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
433*b843c749SSergey Zigachev struct link_training_settings request_settings = { {0} };
434*b843c749SSergey Zigachev uint32_t lane;
435*b843c749SSergey Zigachev
436*b843c749SSergey Zigachev memset(req_settings, '\0', sizeof(struct link_training_settings));
437*b843c749SSergey Zigachev
438*b843c749SSergey Zigachev core_link_read_dpcd(
439*b843c749SSergey Zigachev link,
440*b843c749SSergey Zigachev DP_LANE0_1_STATUS,
441*b843c749SSergey Zigachev (uint8_t *)(dpcd_buf),
442*b843c749SSergey Zigachev sizeof(dpcd_buf));
443*b843c749SSergey Zigachev
444*b843c749SSergey Zigachev for (lane = 0; lane <
445*b843c749SSergey Zigachev (uint32_t)(link_training_setting->link_settings.lane_count);
446*b843c749SSergey Zigachev lane++) {
447*b843c749SSergey Zigachev
448*b843c749SSergey Zigachev ln_status[lane].raw =
449*b843c749SSergey Zigachev get_nibble_at_index(&dpcd_buf[0], lane);
450*b843c749SSergey Zigachev dpcd_lane_adjust[lane].raw =
451*b843c749SSergey Zigachev get_nibble_at_index(&dpcd_buf[4], lane);
452*b843c749SSergey Zigachev }
453*b843c749SSergey Zigachev
454*b843c749SSergey Zigachev ln_status_updated->raw = dpcd_buf[2];
455*b843c749SSergey Zigachev
456*b843c749SSergey Zigachev DC_LOG_HW_LINK_TRAINING("%s:\n%x Lane01Status = %x\n %x Lane23Status = %x\n ",
457*b843c749SSergey Zigachev __func__,
458*b843c749SSergey Zigachev DP_LANE0_1_STATUS, dpcd_buf[0],
459*b843c749SSergey Zigachev DP_LANE2_3_STATUS, dpcd_buf[1]);
460*b843c749SSergey Zigachev
461*b843c749SSergey Zigachev DC_LOG_HW_LINK_TRAINING("%s:\n %x Lane01AdjustRequest = %x\n %x Lane23AdjustRequest = %x\n",
462*b843c749SSergey Zigachev __func__,
463*b843c749SSergey Zigachev DP_ADJUST_REQUEST_LANE0_1,
464*b843c749SSergey Zigachev dpcd_buf[4],
465*b843c749SSergey Zigachev DP_ADJUST_REQUEST_LANE2_3,
466*b843c749SSergey Zigachev dpcd_buf[5]);
467*b843c749SSergey Zigachev
468*b843c749SSergey Zigachev /*copy to req_settings*/
469*b843c749SSergey Zigachev request_settings.link_settings.lane_count =
470*b843c749SSergey Zigachev link_training_setting->link_settings.lane_count;
471*b843c749SSergey Zigachev request_settings.link_settings.link_rate =
472*b843c749SSergey Zigachev link_training_setting->link_settings.link_rate;
473*b843c749SSergey Zigachev request_settings.link_settings.link_spread =
474*b843c749SSergey Zigachev link_training_setting->link_settings.link_spread;
475*b843c749SSergey Zigachev
476*b843c749SSergey Zigachev for (lane = 0; lane <
477*b843c749SSergey Zigachev (uint32_t)(link_training_setting->link_settings.lane_count);
478*b843c749SSergey Zigachev lane++) {
479*b843c749SSergey Zigachev
480*b843c749SSergey Zigachev request_settings.lane_settings[lane].VOLTAGE_SWING =
481*b843c749SSergey Zigachev (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
482*b843c749SSergey Zigachev VOLTAGE_SWING_LANE);
483*b843c749SSergey Zigachev request_settings.lane_settings[lane].PRE_EMPHASIS =
484*b843c749SSergey Zigachev (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
485*b843c749SSergey Zigachev PRE_EMPHASIS_LANE);
486*b843c749SSergey Zigachev }
487*b843c749SSergey Zigachev
488*b843c749SSergey Zigachev /*Note: for postcursor2, read adjusted
489*b843c749SSergey Zigachev * postcursor2 settings from*/
490*b843c749SSergey Zigachev /*DpcdAddress_AdjustRequestPostCursor2 =
491*b843c749SSergey Zigachev *0x020C (not implemented yet)*/
492*b843c749SSergey Zigachev
493*b843c749SSergey Zigachev /* we find the maximum of the requested settings across all lanes*/
494*b843c749SSergey Zigachev /* and set this maximum for all lanes*/
495*b843c749SSergey Zigachev find_max_drive_settings(&request_settings, req_settings);
496*b843c749SSergey Zigachev
497*b843c749SSergey Zigachev /* if post cursor 2 is needed in the future,
498*b843c749SSergey Zigachev * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
499*b843c749SSergey Zigachev */
500*b843c749SSergey Zigachev
501*b843c749SSergey Zigachev }
502*b843c749SSergey Zigachev
dpcd_set_lane_settings(struct dc_link * link,const struct link_training_settings * link_training_setting)503*b843c749SSergey Zigachev static void dpcd_set_lane_settings(
504*b843c749SSergey Zigachev struct dc_link *link,
505*b843c749SSergey Zigachev const struct link_training_settings *link_training_setting)
506*b843c749SSergey Zigachev {
507*b843c749SSergey Zigachev union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
508*b843c749SSergey Zigachev uint32_t lane;
509*b843c749SSergey Zigachev
510*b843c749SSergey Zigachev for (lane = 0; lane <
511*b843c749SSergey Zigachev (uint32_t)(link_training_setting->
512*b843c749SSergey Zigachev link_settings.lane_count);
513*b843c749SSergey Zigachev lane++) {
514*b843c749SSergey Zigachev dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
515*b843c749SSergey Zigachev (uint8_t)(link_training_setting->
516*b843c749SSergey Zigachev lane_settings[lane].VOLTAGE_SWING);
517*b843c749SSergey Zigachev dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
518*b843c749SSergey Zigachev (uint8_t)(link_training_setting->
519*b843c749SSergey Zigachev lane_settings[lane].PRE_EMPHASIS);
520*b843c749SSergey Zigachev dpcd_lane[lane].bits.MAX_SWING_REACHED =
521*b843c749SSergey Zigachev (link_training_setting->
522*b843c749SSergey Zigachev lane_settings[lane].VOLTAGE_SWING ==
523*b843c749SSergey Zigachev VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
524*b843c749SSergey Zigachev dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
525*b843c749SSergey Zigachev (link_training_setting->
526*b843c749SSergey Zigachev lane_settings[lane].PRE_EMPHASIS ==
527*b843c749SSergey Zigachev PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
528*b843c749SSergey Zigachev }
529*b843c749SSergey Zigachev
530*b843c749SSergey Zigachev core_link_write_dpcd(link,
531*b843c749SSergey Zigachev DP_TRAINING_LANE0_SET,
532*b843c749SSergey Zigachev (uint8_t *)(dpcd_lane),
533*b843c749SSergey Zigachev link_training_setting->link_settings.lane_count);
534*b843c749SSergey Zigachev
535*b843c749SSergey Zigachev /*
536*b843c749SSergey Zigachev if (LTSettings.link.rate == LinkRate_High2)
537*b843c749SSergey Zigachev {
538*b843c749SSergey Zigachev DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
539*b843c749SSergey Zigachev for ( uint32_t lane = 0;
540*b843c749SSergey Zigachev lane < lane_count_DPMax; lane++)
541*b843c749SSergey Zigachev {
542*b843c749SSergey Zigachev dpcd_lane2[lane].bits.post_cursor2_set =
543*b843c749SSergey Zigachev static_cast<unsigned char>(
544*b843c749SSergey Zigachev LTSettings.laneSettings[lane].postCursor2);
545*b843c749SSergey Zigachev dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
546*b843c749SSergey Zigachev }
547*b843c749SSergey Zigachev m_pDpcdAccessSrv->WriteDpcdData(
548*b843c749SSergey Zigachev DpcdAddress_Lane0Set2,
549*b843c749SSergey Zigachev reinterpret_cast<unsigned char*>(dpcd_lane2),
550*b843c749SSergey Zigachev LTSettings.link.lanes);
551*b843c749SSergey Zigachev }
552*b843c749SSergey Zigachev */
553*b843c749SSergey Zigachev
554*b843c749SSergey Zigachev DC_LOG_HW_LINK_TRAINING("%s\n %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
555*b843c749SSergey Zigachev __func__,
556*b843c749SSergey Zigachev DP_TRAINING_LANE0_SET,
557*b843c749SSergey Zigachev dpcd_lane[0].bits.VOLTAGE_SWING_SET,
558*b843c749SSergey Zigachev dpcd_lane[0].bits.PRE_EMPHASIS_SET,
559*b843c749SSergey Zigachev dpcd_lane[0].bits.MAX_SWING_REACHED,
560*b843c749SSergey Zigachev dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
561*b843c749SSergey Zigachev
562*b843c749SSergey Zigachev link->cur_lane_setting = link_training_setting->lane_settings[0];
563*b843c749SSergey Zigachev
564*b843c749SSergey Zigachev }
565*b843c749SSergey Zigachev
is_max_vs_reached(const struct link_training_settings * lt_settings)566*b843c749SSergey Zigachev static bool is_max_vs_reached(
567*b843c749SSergey Zigachev const struct link_training_settings *lt_settings)
568*b843c749SSergey Zigachev {
569*b843c749SSergey Zigachev uint32_t lane;
570*b843c749SSergey Zigachev for (lane = 0; lane <
571*b843c749SSergey Zigachev (uint32_t)(lt_settings->link_settings.lane_count);
572*b843c749SSergey Zigachev lane++) {
573*b843c749SSergey Zigachev if (lt_settings->lane_settings[lane].VOLTAGE_SWING
574*b843c749SSergey Zigachev == VOLTAGE_SWING_MAX_LEVEL)
575*b843c749SSergey Zigachev return true;
576*b843c749SSergey Zigachev }
577*b843c749SSergey Zigachev return false;
578*b843c749SSergey Zigachev
579*b843c749SSergey Zigachev }
580*b843c749SSergey Zigachev
dc_link_dp_set_drive_settings(struct dc_link * link,struct link_training_settings * lt_settings)581*b843c749SSergey Zigachev void dc_link_dp_set_drive_settings(
582*b843c749SSergey Zigachev struct dc_link *link,
583*b843c749SSergey Zigachev struct link_training_settings *lt_settings)
584*b843c749SSergey Zigachev {
585*b843c749SSergey Zigachev /* program ASIC PHY settings*/
586*b843c749SSergey Zigachev dp_set_hw_lane_settings(link, lt_settings);
587*b843c749SSergey Zigachev
588*b843c749SSergey Zigachev /* Notify DP sink the PHY settings from source */
589*b843c749SSergey Zigachev dpcd_set_lane_settings(link, lt_settings);
590*b843c749SSergey Zigachev }
591*b843c749SSergey Zigachev
perform_post_lt_adj_req_sequence(struct dc_link * link,struct link_training_settings * lt_settings)592*b843c749SSergey Zigachev static bool perform_post_lt_adj_req_sequence(
593*b843c749SSergey Zigachev struct dc_link *link,
594*b843c749SSergey Zigachev struct link_training_settings *lt_settings)
595*b843c749SSergey Zigachev {
596*b843c749SSergey Zigachev enum dc_lane_count lane_count =
597*b843c749SSergey Zigachev lt_settings->link_settings.lane_count;
598*b843c749SSergey Zigachev
599*b843c749SSergey Zigachev uint32_t adj_req_count;
600*b843c749SSergey Zigachev uint32_t adj_req_timer;
601*b843c749SSergey Zigachev bool req_drv_setting_changed;
602*b843c749SSergey Zigachev uint32_t lane;
603*b843c749SSergey Zigachev
604*b843c749SSergey Zigachev req_drv_setting_changed = false;
605*b843c749SSergey Zigachev for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
606*b843c749SSergey Zigachev adj_req_count++) {
607*b843c749SSergey Zigachev
608*b843c749SSergey Zigachev req_drv_setting_changed = false;
609*b843c749SSergey Zigachev
610*b843c749SSergey Zigachev for (adj_req_timer = 0;
611*b843c749SSergey Zigachev adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
612*b843c749SSergey Zigachev adj_req_timer++) {
613*b843c749SSergey Zigachev
614*b843c749SSergey Zigachev struct link_training_settings req_settings;
615*b843c749SSergey Zigachev union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
616*b843c749SSergey Zigachev union lane_align_status_updated
617*b843c749SSergey Zigachev dpcd_lane_status_updated;
618*b843c749SSergey Zigachev
619*b843c749SSergey Zigachev get_lane_status_and_drive_settings(
620*b843c749SSergey Zigachev link,
621*b843c749SSergey Zigachev lt_settings,
622*b843c749SSergey Zigachev dpcd_lane_status,
623*b843c749SSergey Zigachev &dpcd_lane_status_updated,
624*b843c749SSergey Zigachev &req_settings);
625*b843c749SSergey Zigachev
626*b843c749SSergey Zigachev if (dpcd_lane_status_updated.bits.
627*b843c749SSergey Zigachev POST_LT_ADJ_REQ_IN_PROGRESS == 0)
628*b843c749SSergey Zigachev return true;
629*b843c749SSergey Zigachev
630*b843c749SSergey Zigachev if (!is_cr_done(lane_count, dpcd_lane_status))
631*b843c749SSergey Zigachev return false;
632*b843c749SSergey Zigachev
633*b843c749SSergey Zigachev if (!is_ch_eq_done(
634*b843c749SSergey Zigachev lane_count,
635*b843c749SSergey Zigachev dpcd_lane_status,
636*b843c749SSergey Zigachev &dpcd_lane_status_updated))
637*b843c749SSergey Zigachev return false;
638*b843c749SSergey Zigachev
639*b843c749SSergey Zigachev for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
640*b843c749SSergey Zigachev
641*b843c749SSergey Zigachev if (lt_settings->
642*b843c749SSergey Zigachev lane_settings[lane].VOLTAGE_SWING !=
643*b843c749SSergey Zigachev req_settings.lane_settings[lane].
644*b843c749SSergey Zigachev VOLTAGE_SWING ||
645*b843c749SSergey Zigachev lt_settings->lane_settings[lane].PRE_EMPHASIS !=
646*b843c749SSergey Zigachev req_settings.lane_settings[lane].PRE_EMPHASIS) {
647*b843c749SSergey Zigachev
648*b843c749SSergey Zigachev req_drv_setting_changed = true;
649*b843c749SSergey Zigachev break;
650*b843c749SSergey Zigachev }
651*b843c749SSergey Zigachev }
652*b843c749SSergey Zigachev
653*b843c749SSergey Zigachev if (req_drv_setting_changed) {
654*b843c749SSergey Zigachev update_drive_settings(
655*b843c749SSergey Zigachev lt_settings, req_settings);
656*b843c749SSergey Zigachev
657*b843c749SSergey Zigachev dc_link_dp_set_drive_settings(link,
658*b843c749SSergey Zigachev lt_settings);
659*b843c749SSergey Zigachev break;
660*b843c749SSergey Zigachev }
661*b843c749SSergey Zigachev
662*b843c749SSergey Zigachev msleep(1);
663*b843c749SSergey Zigachev }
664*b843c749SSergey Zigachev
665*b843c749SSergey Zigachev if (!req_drv_setting_changed) {
666*b843c749SSergey Zigachev DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
667*b843c749SSergey Zigachev __func__);
668*b843c749SSergey Zigachev
669*b843c749SSergey Zigachev ASSERT(0);
670*b843c749SSergey Zigachev return true;
671*b843c749SSergey Zigachev }
672*b843c749SSergey Zigachev }
673*b843c749SSergey Zigachev DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
674*b843c749SSergey Zigachev __func__);
675*b843c749SSergey Zigachev
676*b843c749SSergey Zigachev ASSERT(0);
677*b843c749SSergey Zigachev return true;
678*b843c749SSergey Zigachev
679*b843c749SSergey Zigachev }
680*b843c749SSergey Zigachev
get_supported_tp(struct dc_link * link)681*b843c749SSergey Zigachev static enum hw_dp_training_pattern get_supported_tp(struct dc_link *link)
682*b843c749SSergey Zigachev {
683*b843c749SSergey Zigachev enum hw_dp_training_pattern highest_tp = HW_DP_TRAINING_PATTERN_2;
684*b843c749SSergey Zigachev struct encoder_feature_support *features = &link->link_enc->features;
685*b843c749SSergey Zigachev struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
686*b843c749SSergey Zigachev
687*b843c749SSergey Zigachev if (features->flags.bits.IS_TPS3_CAPABLE)
688*b843c749SSergey Zigachev highest_tp = HW_DP_TRAINING_PATTERN_3;
689*b843c749SSergey Zigachev
690*b843c749SSergey Zigachev if (features->flags.bits.IS_TPS4_CAPABLE)
691*b843c749SSergey Zigachev highest_tp = HW_DP_TRAINING_PATTERN_4;
692*b843c749SSergey Zigachev
693*b843c749SSergey Zigachev if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
694*b843c749SSergey Zigachev highest_tp >= HW_DP_TRAINING_PATTERN_4)
695*b843c749SSergey Zigachev return HW_DP_TRAINING_PATTERN_4;
696*b843c749SSergey Zigachev
697*b843c749SSergey Zigachev if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
698*b843c749SSergey Zigachev highest_tp >= HW_DP_TRAINING_PATTERN_3)
699*b843c749SSergey Zigachev return HW_DP_TRAINING_PATTERN_3;
700*b843c749SSergey Zigachev
701*b843c749SSergey Zigachev return HW_DP_TRAINING_PATTERN_2;
702*b843c749SSergey Zigachev }
703*b843c749SSergey Zigachev
get_cr_failure(enum dc_lane_count ln_count,union lane_status * dpcd_lane_status)704*b843c749SSergey Zigachev static enum link_training_result get_cr_failure(enum dc_lane_count ln_count,
705*b843c749SSergey Zigachev union lane_status *dpcd_lane_status)
706*b843c749SSergey Zigachev {
707*b843c749SSergey Zigachev enum link_training_result result = LINK_TRAINING_SUCCESS;
708*b843c749SSergey Zigachev
709*b843c749SSergey Zigachev if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
710*b843c749SSergey Zigachev result = LINK_TRAINING_CR_FAIL_LANE0;
711*b843c749SSergey Zigachev else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
712*b843c749SSergey Zigachev result = LINK_TRAINING_CR_FAIL_LANE1;
713*b843c749SSergey Zigachev else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
714*b843c749SSergey Zigachev result = LINK_TRAINING_CR_FAIL_LANE23;
715*b843c749SSergey Zigachev else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
716*b843c749SSergey Zigachev result = LINK_TRAINING_CR_FAIL_LANE23;
717*b843c749SSergey Zigachev return result;
718*b843c749SSergey Zigachev }
719*b843c749SSergey Zigachev
perform_channel_equalization_sequence(struct dc_link * link,struct link_training_settings * lt_settings)720*b843c749SSergey Zigachev static enum link_training_result perform_channel_equalization_sequence(
721*b843c749SSergey Zigachev struct dc_link *link,
722*b843c749SSergey Zigachev struct link_training_settings *lt_settings)
723*b843c749SSergey Zigachev {
724*b843c749SSergey Zigachev struct link_training_settings req_settings;
725*b843c749SSergey Zigachev enum hw_dp_training_pattern hw_tr_pattern;
726*b843c749SSergey Zigachev uint32_t retries_ch_eq;
727*b843c749SSergey Zigachev enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
728*b843c749SSergey Zigachev union lane_align_status_updated dpcd_lane_status_updated = { {0} };
729*b843c749SSergey Zigachev union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
730*b843c749SSergey Zigachev
731*b843c749SSergey Zigachev hw_tr_pattern = get_supported_tp(link);
732*b843c749SSergey Zigachev
733*b843c749SSergey Zigachev dp_set_hw_training_pattern(link, hw_tr_pattern);
734*b843c749SSergey Zigachev
735*b843c749SSergey Zigachev for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
736*b843c749SSergey Zigachev retries_ch_eq++) {
737*b843c749SSergey Zigachev
738*b843c749SSergey Zigachev dp_set_hw_lane_settings(link, lt_settings);
739*b843c749SSergey Zigachev
740*b843c749SSergey Zigachev /* 2. update DPCD*/
741*b843c749SSergey Zigachev if (!retries_ch_eq)
742*b843c749SSergey Zigachev /* EPR #361076 - write as a 5-byte burst,
743*b843c749SSergey Zigachev * but only for the 1-st iteration*/
744*b843c749SSergey Zigachev dpcd_set_lt_pattern_and_lane_settings(
745*b843c749SSergey Zigachev link,
746*b843c749SSergey Zigachev lt_settings,
747*b843c749SSergey Zigachev hw_tr_pattern);
748*b843c749SSergey Zigachev else
749*b843c749SSergey Zigachev dpcd_set_lane_settings(link, lt_settings);
750*b843c749SSergey Zigachev
751*b843c749SSergey Zigachev /* 3. wait for receiver to lock-on*/
752*b843c749SSergey Zigachev wait_for_training_aux_rd_interval(link, 400);
753*b843c749SSergey Zigachev
754*b843c749SSergey Zigachev /* 4. Read lane status and requested
755*b843c749SSergey Zigachev * drive settings as set by the sink*/
756*b843c749SSergey Zigachev
757*b843c749SSergey Zigachev get_lane_status_and_drive_settings(
758*b843c749SSergey Zigachev link,
759*b843c749SSergey Zigachev lt_settings,
760*b843c749SSergey Zigachev dpcd_lane_status,
761*b843c749SSergey Zigachev &dpcd_lane_status_updated,
762*b843c749SSergey Zigachev &req_settings);
763*b843c749SSergey Zigachev
764*b843c749SSergey Zigachev /* 5. check CR done*/
765*b843c749SSergey Zigachev if (!is_cr_done(lane_count, dpcd_lane_status))
766*b843c749SSergey Zigachev return LINK_TRAINING_EQ_FAIL_CR;
767*b843c749SSergey Zigachev
768*b843c749SSergey Zigachev /* 6. check CHEQ done*/
769*b843c749SSergey Zigachev if (is_ch_eq_done(lane_count,
770*b843c749SSergey Zigachev dpcd_lane_status,
771*b843c749SSergey Zigachev &dpcd_lane_status_updated))
772*b843c749SSergey Zigachev return LINK_TRAINING_SUCCESS;
773*b843c749SSergey Zigachev
774*b843c749SSergey Zigachev /* 7. update VS/PE/PC2 in lt_settings*/
775*b843c749SSergey Zigachev update_drive_settings(lt_settings, req_settings);
776*b843c749SSergey Zigachev }
777*b843c749SSergey Zigachev
778*b843c749SSergey Zigachev return LINK_TRAINING_EQ_FAIL_EQ;
779*b843c749SSergey Zigachev
780*b843c749SSergey Zigachev }
781*b843c749SSergey Zigachev
perform_clock_recovery_sequence(struct dc_link * link,struct link_training_settings * lt_settings)782*b843c749SSergey Zigachev static enum link_training_result perform_clock_recovery_sequence(
783*b843c749SSergey Zigachev struct dc_link *link,
784*b843c749SSergey Zigachev struct link_training_settings *lt_settings)
785*b843c749SSergey Zigachev {
786*b843c749SSergey Zigachev uint32_t retries_cr;
787*b843c749SSergey Zigachev uint32_t retry_count;
788*b843c749SSergey Zigachev uint32_t lane;
789*b843c749SSergey Zigachev struct link_training_settings req_settings;
790*b843c749SSergey Zigachev enum dc_lane_count lane_count =
791*b843c749SSergey Zigachev lt_settings->link_settings.lane_count;
792*b843c749SSergey Zigachev enum hw_dp_training_pattern hw_tr_pattern = HW_DP_TRAINING_PATTERN_1;
793*b843c749SSergey Zigachev union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
794*b843c749SSergey Zigachev union lane_align_status_updated dpcd_lane_status_updated;
795*b843c749SSergey Zigachev
796*b843c749SSergey Zigachev retries_cr = 0;
797*b843c749SSergey Zigachev retry_count = 0;
798*b843c749SSergey Zigachev /* initial drive setting (VS/PE/PC2)*/
799*b843c749SSergey Zigachev for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
800*b843c749SSergey Zigachev lt_settings->lane_settings[lane].VOLTAGE_SWING =
801*b843c749SSergey Zigachev VOLTAGE_SWING_LEVEL0;
802*b843c749SSergey Zigachev lt_settings->lane_settings[lane].PRE_EMPHASIS =
803*b843c749SSergey Zigachev PRE_EMPHASIS_DISABLED;
804*b843c749SSergey Zigachev lt_settings->lane_settings[lane].POST_CURSOR2 =
805*b843c749SSergey Zigachev POST_CURSOR2_DISABLED;
806*b843c749SSergey Zigachev }
807*b843c749SSergey Zigachev
808*b843c749SSergey Zigachev dp_set_hw_training_pattern(link, hw_tr_pattern);
809*b843c749SSergey Zigachev
810*b843c749SSergey Zigachev /* najeeb - The synaptics MST hub can put the LT in
811*b843c749SSergey Zigachev * infinite loop by switching the VS
812*b843c749SSergey Zigachev */
813*b843c749SSergey Zigachev /* between level 0 and level 1 continuously, here
814*b843c749SSergey Zigachev * we try for CR lock for LinkTrainingMaxCRRetry count*/
815*b843c749SSergey Zigachev while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
816*b843c749SSergey Zigachev (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
817*b843c749SSergey Zigachev
818*b843c749SSergey Zigachev memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
819*b843c749SSergey Zigachev memset(&dpcd_lane_status_updated, '\0',
820*b843c749SSergey Zigachev sizeof(dpcd_lane_status_updated));
821*b843c749SSergey Zigachev
822*b843c749SSergey Zigachev /* 1. call HWSS to set lane settings*/
823*b843c749SSergey Zigachev dp_set_hw_lane_settings(
824*b843c749SSergey Zigachev link,
825*b843c749SSergey Zigachev lt_settings);
826*b843c749SSergey Zigachev
827*b843c749SSergey Zigachev /* 2. update DPCD of the receiver*/
828*b843c749SSergey Zigachev if (!retries_cr)
829*b843c749SSergey Zigachev /* EPR #361076 - write as a 5-byte burst,
830*b843c749SSergey Zigachev * but only for the 1-st iteration.*/
831*b843c749SSergey Zigachev dpcd_set_lt_pattern_and_lane_settings(
832*b843c749SSergey Zigachev link,
833*b843c749SSergey Zigachev lt_settings,
834*b843c749SSergey Zigachev hw_tr_pattern);
835*b843c749SSergey Zigachev else
836*b843c749SSergey Zigachev dpcd_set_lane_settings(
837*b843c749SSergey Zigachev link,
838*b843c749SSergey Zigachev lt_settings);
839*b843c749SSergey Zigachev
840*b843c749SSergey Zigachev /* 3. wait receiver to lock-on*/
841*b843c749SSergey Zigachev wait_for_training_aux_rd_interval(
842*b843c749SSergey Zigachev link,
843*b843c749SSergey Zigachev 100);
844*b843c749SSergey Zigachev
845*b843c749SSergey Zigachev /* 4. Read lane status and requested drive
846*b843c749SSergey Zigachev * settings as set by the sink
847*b843c749SSergey Zigachev */
848*b843c749SSergey Zigachev get_lane_status_and_drive_settings(
849*b843c749SSergey Zigachev link,
850*b843c749SSergey Zigachev lt_settings,
851*b843c749SSergey Zigachev dpcd_lane_status,
852*b843c749SSergey Zigachev &dpcd_lane_status_updated,
853*b843c749SSergey Zigachev &req_settings);
854*b843c749SSergey Zigachev
855*b843c749SSergey Zigachev /* 5. check CR done*/
856*b843c749SSergey Zigachev if (is_cr_done(lane_count, dpcd_lane_status))
857*b843c749SSergey Zigachev return LINK_TRAINING_SUCCESS;
858*b843c749SSergey Zigachev
859*b843c749SSergey Zigachev /* 6. max VS reached*/
860*b843c749SSergey Zigachev if (is_max_vs_reached(lt_settings))
861*b843c749SSergey Zigachev break;
862*b843c749SSergey Zigachev
863*b843c749SSergey Zigachev /* 7. same voltage*/
864*b843c749SSergey Zigachev /* Note: VS same for all lanes,
865*b843c749SSergey Zigachev * so comparing first lane is sufficient*/
866*b843c749SSergey Zigachev if (lt_settings->lane_settings[0].VOLTAGE_SWING ==
867*b843c749SSergey Zigachev req_settings.lane_settings[0].VOLTAGE_SWING)
868*b843c749SSergey Zigachev retries_cr++;
869*b843c749SSergey Zigachev else
870*b843c749SSergey Zigachev retries_cr = 0;
871*b843c749SSergey Zigachev
872*b843c749SSergey Zigachev /* 8. update VS/PE/PC2 in lt_settings*/
873*b843c749SSergey Zigachev update_drive_settings(lt_settings, req_settings);
874*b843c749SSergey Zigachev
875*b843c749SSergey Zigachev retry_count++;
876*b843c749SSergey Zigachev }
877*b843c749SSergey Zigachev
878*b843c749SSergey Zigachev if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
879*b843c749SSergey Zigachev ASSERT(0);
880*b843c749SSergey Zigachev DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
881*b843c749SSergey Zigachev __func__,
882*b843c749SSergey Zigachev LINK_TRAINING_MAX_CR_RETRY);
883*b843c749SSergey Zigachev
884*b843c749SSergey Zigachev }
885*b843c749SSergey Zigachev
886*b843c749SSergey Zigachev return get_cr_failure(lane_count, dpcd_lane_status);
887*b843c749SSergey Zigachev }
888*b843c749SSergey Zigachev
perform_link_training_int(struct dc_link * link,struct link_training_settings * lt_settings,enum link_training_result status)889*b843c749SSergey Zigachev static inline enum link_training_result perform_link_training_int(
890*b843c749SSergey Zigachev struct dc_link *link,
891*b843c749SSergey Zigachev struct link_training_settings *lt_settings,
892*b843c749SSergey Zigachev enum link_training_result status)
893*b843c749SSergey Zigachev {
894*b843c749SSergey Zigachev union lane_count_set lane_count_set = { {0} };
895*b843c749SSergey Zigachev union dpcd_training_pattern dpcd_pattern = { {0} };
896*b843c749SSergey Zigachev
897*b843c749SSergey Zigachev /* 3. set training not in progress*/
898*b843c749SSergey Zigachev dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
899*b843c749SSergey Zigachev dpcd_set_training_pattern(link, dpcd_pattern);
900*b843c749SSergey Zigachev
901*b843c749SSergey Zigachev /* 4. mainlink output idle pattern*/
902*b843c749SSergey Zigachev dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
903*b843c749SSergey Zigachev
904*b843c749SSergey Zigachev /*
905*b843c749SSergey Zigachev * 5. post training adjust if required
906*b843c749SSergey Zigachev * If the upstream DPTX and downstream DPRX both support TPS4,
907*b843c749SSergey Zigachev * TPS4 must be used instead of POST_LT_ADJ_REQ.
908*b843c749SSergey Zigachev */
909*b843c749SSergey Zigachev if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
910*b843c749SSergey Zigachev get_supported_tp(link) == HW_DP_TRAINING_PATTERN_4)
911*b843c749SSergey Zigachev return status;
912*b843c749SSergey Zigachev
913*b843c749SSergey Zigachev if (status == LINK_TRAINING_SUCCESS &&
914*b843c749SSergey Zigachev perform_post_lt_adj_req_sequence(link, lt_settings) == false)
915*b843c749SSergey Zigachev status = LINK_TRAINING_LQA_FAIL;
916*b843c749SSergey Zigachev
917*b843c749SSergey Zigachev lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
918*b843c749SSergey Zigachev lane_count_set.bits.ENHANCED_FRAMING = 1;
919*b843c749SSergey Zigachev lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
920*b843c749SSergey Zigachev
921*b843c749SSergey Zigachev core_link_write_dpcd(
922*b843c749SSergey Zigachev link,
923*b843c749SSergey Zigachev DP_LANE_COUNT_SET,
924*b843c749SSergey Zigachev &lane_count_set.raw,
925*b843c749SSergey Zigachev sizeof(lane_count_set));
926*b843c749SSergey Zigachev
927*b843c749SSergey Zigachev return status;
928*b843c749SSergey Zigachev }
929*b843c749SSergey Zigachev
dc_link_dp_perform_link_training(struct dc_link * link,const struct dc_link_settings * link_setting,bool skip_video_pattern)930*b843c749SSergey Zigachev enum link_training_result dc_link_dp_perform_link_training(
931*b843c749SSergey Zigachev struct dc_link *link,
932*b843c749SSergey Zigachev const struct dc_link_settings *link_setting,
933*b843c749SSergey Zigachev bool skip_video_pattern)
934*b843c749SSergey Zigachev {
935*b843c749SSergey Zigachev enum link_training_result status = LINK_TRAINING_SUCCESS;
936*b843c749SSergey Zigachev
937*b843c749SSergey Zigachev char *link_rate = "Unknown";
938*b843c749SSergey Zigachev char *lt_result = "Unknown";
939*b843c749SSergey Zigachev
940*b843c749SSergey Zigachev struct link_training_settings lt_settings;
941*b843c749SSergey Zigachev
942*b843c749SSergey Zigachev memset(<_settings, '\0', sizeof(lt_settings));
943*b843c749SSergey Zigachev
944*b843c749SSergey Zigachev lt_settings.link_settings.link_rate = link_setting->link_rate;
945*b843c749SSergey Zigachev lt_settings.link_settings.lane_count = link_setting->lane_count;
946*b843c749SSergey Zigachev
947*b843c749SSergey Zigachev /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
948*b843c749SSergey Zigachev
949*b843c749SSergey Zigachev /* TODO hard coded to SS for now
950*b843c749SSergey Zigachev * lt_settings.link_settings.link_spread =
951*b843c749SSergey Zigachev * dal_display_path_is_ss_supported(
952*b843c749SSergey Zigachev * path_mode->display_path) ?
953*b843c749SSergey Zigachev * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
954*b843c749SSergey Zigachev * LINK_SPREAD_DISABLED;
955*b843c749SSergey Zigachev */
956*b843c749SSergey Zigachev if (link->dp_ss_off)
957*b843c749SSergey Zigachev lt_settings.link_settings.link_spread = LINK_SPREAD_DISABLED;
958*b843c749SSergey Zigachev else
959*b843c749SSergey Zigachev lt_settings.link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
960*b843c749SSergey Zigachev
961*b843c749SSergey Zigachev /* 1. set link rate, lane count and spread*/
962*b843c749SSergey Zigachev dpcd_set_link_settings(link, <_settings);
963*b843c749SSergey Zigachev
964*b843c749SSergey Zigachev /* 2. perform link training (set link training done
965*b843c749SSergey Zigachev * to false is done as well)*/
966*b843c749SSergey Zigachev status = perform_clock_recovery_sequence(link, <_settings);
967*b843c749SSergey Zigachev if (status == LINK_TRAINING_SUCCESS) {
968*b843c749SSergey Zigachev status = perform_channel_equalization_sequence(link,
969*b843c749SSergey Zigachev <_settings);
970*b843c749SSergey Zigachev }
971*b843c749SSergey Zigachev
972*b843c749SSergey Zigachev if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
973*b843c749SSergey Zigachev status = perform_link_training_int(link,
974*b843c749SSergey Zigachev <_settings,
975*b843c749SSergey Zigachev status);
976*b843c749SSergey Zigachev }
977*b843c749SSergey Zigachev
978*b843c749SSergey Zigachev /* 6. print status message*/
979*b843c749SSergey Zigachev switch (lt_settings.link_settings.link_rate) {
980*b843c749SSergey Zigachev
981*b843c749SSergey Zigachev case LINK_RATE_LOW:
982*b843c749SSergey Zigachev link_rate = "RBR";
983*b843c749SSergey Zigachev break;
984*b843c749SSergey Zigachev case LINK_RATE_HIGH:
985*b843c749SSergey Zigachev link_rate = "HBR";
986*b843c749SSergey Zigachev break;
987*b843c749SSergey Zigachev case LINK_RATE_HIGH2:
988*b843c749SSergey Zigachev link_rate = "HBR2";
989*b843c749SSergey Zigachev break;
990*b843c749SSergey Zigachev case LINK_RATE_RBR2:
991*b843c749SSergey Zigachev link_rate = "RBR2";
992*b843c749SSergey Zigachev break;
993*b843c749SSergey Zigachev case LINK_RATE_HIGH3:
994*b843c749SSergey Zigachev link_rate = "HBR3";
995*b843c749SSergey Zigachev break;
996*b843c749SSergey Zigachev default:
997*b843c749SSergey Zigachev break;
998*b843c749SSergey Zigachev }
999*b843c749SSergey Zigachev
1000*b843c749SSergey Zigachev switch (status) {
1001*b843c749SSergey Zigachev case LINK_TRAINING_SUCCESS:
1002*b843c749SSergey Zigachev lt_result = "pass";
1003*b843c749SSergey Zigachev break;
1004*b843c749SSergey Zigachev case LINK_TRAINING_CR_FAIL_LANE0:
1005*b843c749SSergey Zigachev lt_result = "CR failed lane0";
1006*b843c749SSergey Zigachev break;
1007*b843c749SSergey Zigachev case LINK_TRAINING_CR_FAIL_LANE1:
1008*b843c749SSergey Zigachev lt_result = "CR failed lane1";
1009*b843c749SSergey Zigachev break;
1010*b843c749SSergey Zigachev case LINK_TRAINING_CR_FAIL_LANE23:
1011*b843c749SSergey Zigachev lt_result = "CR failed lane23";
1012*b843c749SSergey Zigachev break;
1013*b843c749SSergey Zigachev case LINK_TRAINING_EQ_FAIL_CR:
1014*b843c749SSergey Zigachev lt_result = "CR failed in EQ";
1015*b843c749SSergey Zigachev break;
1016*b843c749SSergey Zigachev case LINK_TRAINING_EQ_FAIL_EQ:
1017*b843c749SSergey Zigachev lt_result = "EQ failed";
1018*b843c749SSergey Zigachev break;
1019*b843c749SSergey Zigachev case LINK_TRAINING_LQA_FAIL:
1020*b843c749SSergey Zigachev lt_result = "LQA failed";
1021*b843c749SSergey Zigachev break;
1022*b843c749SSergey Zigachev default:
1023*b843c749SSergey Zigachev break;
1024*b843c749SSergey Zigachev }
1025*b843c749SSergey Zigachev
1026*b843c749SSergey Zigachev /* Connectivity log: link training */
1027*b843c749SSergey Zigachev CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d",
1028*b843c749SSergey Zigachev link_rate,
1029*b843c749SSergey Zigachev lt_settings.link_settings.lane_count,
1030*b843c749SSergey Zigachev lt_result,
1031*b843c749SSergey Zigachev lt_settings.lane_settings[0].VOLTAGE_SWING,
1032*b843c749SSergey Zigachev lt_settings.lane_settings[0].PRE_EMPHASIS);
1033*b843c749SSergey Zigachev
1034*b843c749SSergey Zigachev if (status != LINK_TRAINING_SUCCESS)
1035*b843c749SSergey Zigachev link->ctx->dc->debug_data.ltFailCount++;
1036*b843c749SSergey Zigachev
1037*b843c749SSergey Zigachev return status;
1038*b843c749SSergey Zigachev }
1039*b843c749SSergey Zigachev
1040*b843c749SSergey Zigachev
perform_link_training_with_retries(struct dc_link * link,const struct dc_link_settings * link_setting,bool skip_video_pattern,int attempts)1041*b843c749SSergey Zigachev bool perform_link_training_with_retries(
1042*b843c749SSergey Zigachev struct dc_link *link,
1043*b843c749SSergey Zigachev const struct dc_link_settings *link_setting,
1044*b843c749SSergey Zigachev bool skip_video_pattern,
1045*b843c749SSergey Zigachev int attempts)
1046*b843c749SSergey Zigachev {
1047*b843c749SSergey Zigachev uint8_t j;
1048*b843c749SSergey Zigachev uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1049*b843c749SSergey Zigachev
1050*b843c749SSergey Zigachev for (j = 0; j < attempts; ++j) {
1051*b843c749SSergey Zigachev
1052*b843c749SSergey Zigachev if (dc_link_dp_perform_link_training(
1053*b843c749SSergey Zigachev link,
1054*b843c749SSergey Zigachev link_setting,
1055*b843c749SSergey Zigachev skip_video_pattern) == LINK_TRAINING_SUCCESS)
1056*b843c749SSergey Zigachev return true;
1057*b843c749SSergey Zigachev
1058*b843c749SSergey Zigachev msleep(delay_between_attempts);
1059*b843c749SSergey Zigachev delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1060*b843c749SSergey Zigachev }
1061*b843c749SSergey Zigachev
1062*b843c749SSergey Zigachev return false;
1063*b843c749SSergey Zigachev }
1064*b843c749SSergey Zigachev
get_max_link_cap(struct dc_link * link)1065*b843c749SSergey Zigachev static struct dc_link_settings get_max_link_cap(struct dc_link *link)
1066*b843c749SSergey Zigachev {
1067*b843c749SSergey Zigachev /* Set Default link settings */
1068*b843c749SSergey Zigachev struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,
1069*b843c749SSergey Zigachev LINK_SPREAD_05_DOWNSPREAD_30KHZ};
1070*b843c749SSergey Zigachev
1071*b843c749SSergey Zigachev /* Higher link settings based on feature supported */
1072*b843c749SSergey Zigachev if (link->link_enc->features.flags.bits.IS_HBR2_CAPABLE)
1073*b843c749SSergey Zigachev max_link_cap.link_rate = LINK_RATE_HIGH2;
1074*b843c749SSergey Zigachev
1075*b843c749SSergey Zigachev if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
1076*b843c749SSergey Zigachev max_link_cap.link_rate = LINK_RATE_HIGH3;
1077*b843c749SSergey Zigachev
1078*b843c749SSergey Zigachev /* Lower link settings based on sink's link cap */
1079*b843c749SSergey Zigachev if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
1080*b843c749SSergey Zigachev max_link_cap.lane_count =
1081*b843c749SSergey Zigachev link->reported_link_cap.lane_count;
1082*b843c749SSergey Zigachev if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
1083*b843c749SSergey Zigachev max_link_cap.link_rate =
1084*b843c749SSergey Zigachev link->reported_link_cap.link_rate;
1085*b843c749SSergey Zigachev if (link->reported_link_cap.link_spread <
1086*b843c749SSergey Zigachev max_link_cap.link_spread)
1087*b843c749SSergey Zigachev max_link_cap.link_spread =
1088*b843c749SSergey Zigachev link->reported_link_cap.link_spread;
1089*b843c749SSergey Zigachev return max_link_cap;
1090*b843c749SSergey Zigachev }
1091*b843c749SSergey Zigachev
dp_verify_link_cap(struct dc_link * link,struct dc_link_settings * known_limit_link_setting,int * fail_count)1092*b843c749SSergey Zigachev bool dp_verify_link_cap(
1093*b843c749SSergey Zigachev struct dc_link *link,
1094*b843c749SSergey Zigachev struct dc_link_settings *known_limit_link_setting,
1095*b843c749SSergey Zigachev int *fail_count)
1096*b843c749SSergey Zigachev {
1097*b843c749SSergey Zigachev struct dc_link_settings max_link_cap = {0};
1098*b843c749SSergey Zigachev struct dc_link_settings cur_link_setting = {0};
1099*b843c749SSergey Zigachev struct dc_link_settings *cur = &cur_link_setting;
1100*b843c749SSergey Zigachev struct dc_link_settings initial_link_settings = {0};
1101*b843c749SSergey Zigachev bool success;
1102*b843c749SSergey Zigachev bool skip_link_training;
1103*b843c749SSergey Zigachev bool skip_video_pattern;
1104*b843c749SSergey Zigachev struct clock_source *dp_cs;
1105*b843c749SSergey Zigachev enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
1106*b843c749SSergey Zigachev enum link_training_result status;
1107*b843c749SSergey Zigachev
1108*b843c749SSergey Zigachev if (link->dc->debug.skip_detection_link_training) {
1109*b843c749SSergey Zigachev link->verified_link_cap = *known_limit_link_setting;
1110*b843c749SSergey Zigachev return true;
1111*b843c749SSergey Zigachev }
1112*b843c749SSergey Zigachev
1113*b843c749SSergey Zigachev success = false;
1114*b843c749SSergey Zigachev skip_link_training = false;
1115*b843c749SSergey Zigachev
1116*b843c749SSergey Zigachev max_link_cap = get_max_link_cap(link);
1117*b843c749SSergey Zigachev
1118*b843c749SSergey Zigachev /* TODO implement override and monitor patch later */
1119*b843c749SSergey Zigachev
1120*b843c749SSergey Zigachev /* try to train the link from high to low to
1121*b843c749SSergey Zigachev * find the physical link capability
1122*b843c749SSergey Zigachev */
1123*b843c749SSergey Zigachev /* disable PHY done possible by BIOS, will be done by driver itself */
1124*b843c749SSergey Zigachev dp_disable_link_phy(link, link->connector_signal);
1125*b843c749SSergey Zigachev
1126*b843c749SSergey Zigachev dp_cs = link->dc->res_pool->dp_clock_source;
1127*b843c749SSergey Zigachev
1128*b843c749SSergey Zigachev if (dp_cs)
1129*b843c749SSergey Zigachev dp_cs_id = dp_cs->id;
1130*b843c749SSergey Zigachev else {
1131*b843c749SSergey Zigachev /*
1132*b843c749SSergey Zigachev * dp clock source is not initialized for some reason.
1133*b843c749SSergey Zigachev * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1134*b843c749SSergey Zigachev */
1135*b843c749SSergey Zigachev ASSERT(dp_cs);
1136*b843c749SSergey Zigachev }
1137*b843c749SSergey Zigachev
1138*b843c749SSergey Zigachev /* link training starts with the maximum common settings
1139*b843c749SSergey Zigachev * supported by both sink and ASIC.
1140*b843c749SSergey Zigachev */
1141*b843c749SSergey Zigachev initial_link_settings = get_common_supported_link_settings(
1142*b843c749SSergey Zigachev *known_limit_link_setting,
1143*b843c749SSergey Zigachev max_link_cap);
1144*b843c749SSergey Zigachev cur_link_setting = initial_link_settings;
1145*b843c749SSergey Zigachev do {
1146*b843c749SSergey Zigachev skip_video_pattern = true;
1147*b843c749SSergey Zigachev
1148*b843c749SSergey Zigachev if (cur->link_rate == LINK_RATE_LOW)
1149*b843c749SSergey Zigachev skip_video_pattern = false;
1150*b843c749SSergey Zigachev
1151*b843c749SSergey Zigachev dp_enable_link_phy(
1152*b843c749SSergey Zigachev link,
1153*b843c749SSergey Zigachev link->connector_signal,
1154*b843c749SSergey Zigachev dp_cs_id,
1155*b843c749SSergey Zigachev cur);
1156*b843c749SSergey Zigachev
1157*b843c749SSergey Zigachev
1158*b843c749SSergey Zigachev if (skip_link_training)
1159*b843c749SSergey Zigachev success = true;
1160*b843c749SSergey Zigachev else {
1161*b843c749SSergey Zigachev status = dc_link_dp_perform_link_training(
1162*b843c749SSergey Zigachev link,
1163*b843c749SSergey Zigachev cur,
1164*b843c749SSergey Zigachev skip_video_pattern);
1165*b843c749SSergey Zigachev if (status == LINK_TRAINING_SUCCESS)
1166*b843c749SSergey Zigachev success = true;
1167*b843c749SSergey Zigachev else
1168*b843c749SSergey Zigachev (*fail_count)++;
1169*b843c749SSergey Zigachev }
1170*b843c749SSergey Zigachev
1171*b843c749SSergey Zigachev if (success)
1172*b843c749SSergey Zigachev link->verified_link_cap = *cur;
1173*b843c749SSergey Zigachev
1174*b843c749SSergey Zigachev /* always disable the link before trying another
1175*b843c749SSergey Zigachev * setting or before returning we'll enable it later
1176*b843c749SSergey Zigachev * based on the actual mode we're driving
1177*b843c749SSergey Zigachev */
1178*b843c749SSergey Zigachev dp_disable_link_phy(link, link->connector_signal);
1179*b843c749SSergey Zigachev } while (!success && decide_fallback_link_setting(
1180*b843c749SSergey Zigachev initial_link_settings, cur, status));
1181*b843c749SSergey Zigachev
1182*b843c749SSergey Zigachev /* Link Training failed for all Link Settings
1183*b843c749SSergey Zigachev * (Lane Count is still unknown)
1184*b843c749SSergey Zigachev */
1185*b843c749SSergey Zigachev if (!success) {
1186*b843c749SSergey Zigachev /* If all LT fails for all settings,
1187*b843c749SSergey Zigachev * set verified = failed safe (1 lane low)
1188*b843c749SSergey Zigachev */
1189*b843c749SSergey Zigachev link->verified_link_cap.lane_count = LANE_COUNT_ONE;
1190*b843c749SSergey Zigachev link->verified_link_cap.link_rate = LINK_RATE_LOW;
1191*b843c749SSergey Zigachev
1192*b843c749SSergey Zigachev link->verified_link_cap.link_spread =
1193*b843c749SSergey Zigachev LINK_SPREAD_DISABLED;
1194*b843c749SSergey Zigachev }
1195*b843c749SSergey Zigachev
1196*b843c749SSergey Zigachev
1197*b843c749SSergey Zigachev return success;
1198*b843c749SSergey Zigachev }
1199*b843c749SSergey Zigachev
get_common_supported_link_settings(struct dc_link_settings link_setting_a,struct dc_link_settings link_setting_b)1200*b843c749SSergey Zigachev static struct dc_link_settings get_common_supported_link_settings(
1201*b843c749SSergey Zigachev struct dc_link_settings link_setting_a,
1202*b843c749SSergey Zigachev struct dc_link_settings link_setting_b)
1203*b843c749SSergey Zigachev {
1204*b843c749SSergey Zigachev struct dc_link_settings link_settings = {0};
1205*b843c749SSergey Zigachev
1206*b843c749SSergey Zigachev link_settings.lane_count =
1207*b843c749SSergey Zigachev (link_setting_a.lane_count <=
1208*b843c749SSergey Zigachev link_setting_b.lane_count) ?
1209*b843c749SSergey Zigachev link_setting_a.lane_count :
1210*b843c749SSergey Zigachev link_setting_b.lane_count;
1211*b843c749SSergey Zigachev link_settings.link_rate =
1212*b843c749SSergey Zigachev (link_setting_a.link_rate <=
1213*b843c749SSergey Zigachev link_setting_b.link_rate) ?
1214*b843c749SSergey Zigachev link_setting_a.link_rate :
1215*b843c749SSergey Zigachev link_setting_b.link_rate;
1216*b843c749SSergey Zigachev link_settings.link_spread = LINK_SPREAD_DISABLED;
1217*b843c749SSergey Zigachev
1218*b843c749SSergey Zigachev /* in DP compliance test, DPR-120 may have
1219*b843c749SSergey Zigachev * a random value in its MAX_LINK_BW dpcd field.
1220*b843c749SSergey Zigachev * We map it to the maximum supported link rate that
1221*b843c749SSergey Zigachev * is smaller than MAX_LINK_BW in this case.
1222*b843c749SSergey Zigachev */
1223*b843c749SSergey Zigachev if (link_settings.link_rate > LINK_RATE_HIGH3) {
1224*b843c749SSergey Zigachev link_settings.link_rate = LINK_RATE_HIGH3;
1225*b843c749SSergey Zigachev } else if (link_settings.link_rate < LINK_RATE_HIGH3
1226*b843c749SSergey Zigachev && link_settings.link_rate > LINK_RATE_HIGH2) {
1227*b843c749SSergey Zigachev link_settings.link_rate = LINK_RATE_HIGH2;
1228*b843c749SSergey Zigachev } else if (link_settings.link_rate < LINK_RATE_HIGH2
1229*b843c749SSergey Zigachev && link_settings.link_rate > LINK_RATE_HIGH) {
1230*b843c749SSergey Zigachev link_settings.link_rate = LINK_RATE_HIGH;
1231*b843c749SSergey Zigachev } else if (link_settings.link_rate < LINK_RATE_HIGH
1232*b843c749SSergey Zigachev && link_settings.link_rate > LINK_RATE_LOW) {
1233*b843c749SSergey Zigachev link_settings.link_rate = LINK_RATE_LOW;
1234*b843c749SSergey Zigachev } else if (link_settings.link_rate < LINK_RATE_LOW) {
1235*b843c749SSergey Zigachev link_settings.link_rate = LINK_RATE_UNKNOWN;
1236*b843c749SSergey Zigachev }
1237*b843c749SSergey Zigachev
1238*b843c749SSergey Zigachev return link_settings;
1239*b843c749SSergey Zigachev }
1240*b843c749SSergey Zigachev
reached_minimum_lane_count(enum dc_lane_count lane_count)1241*b843c749SSergey Zigachev static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
1242*b843c749SSergey Zigachev {
1243*b843c749SSergey Zigachev return lane_count <= LANE_COUNT_ONE;
1244*b843c749SSergey Zigachev }
1245*b843c749SSergey Zigachev
reached_minimum_link_rate(enum dc_link_rate link_rate)1246*b843c749SSergey Zigachev static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
1247*b843c749SSergey Zigachev {
1248*b843c749SSergey Zigachev return link_rate <= LINK_RATE_LOW;
1249*b843c749SSergey Zigachev }
1250*b843c749SSergey Zigachev
reduce_lane_count(enum dc_lane_count lane_count)1251*b843c749SSergey Zigachev static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
1252*b843c749SSergey Zigachev {
1253*b843c749SSergey Zigachev switch (lane_count) {
1254*b843c749SSergey Zigachev case LANE_COUNT_FOUR:
1255*b843c749SSergey Zigachev return LANE_COUNT_TWO;
1256*b843c749SSergey Zigachev case LANE_COUNT_TWO:
1257*b843c749SSergey Zigachev return LANE_COUNT_ONE;
1258*b843c749SSergey Zigachev case LANE_COUNT_ONE:
1259*b843c749SSergey Zigachev return LANE_COUNT_UNKNOWN;
1260*b843c749SSergey Zigachev default:
1261*b843c749SSergey Zigachev return LANE_COUNT_UNKNOWN;
1262*b843c749SSergey Zigachev }
1263*b843c749SSergey Zigachev }
1264*b843c749SSergey Zigachev
reduce_link_rate(enum dc_link_rate link_rate)1265*b843c749SSergey Zigachev static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
1266*b843c749SSergey Zigachev {
1267*b843c749SSergey Zigachev switch (link_rate) {
1268*b843c749SSergey Zigachev case LINK_RATE_HIGH3:
1269*b843c749SSergey Zigachev return LINK_RATE_HIGH2;
1270*b843c749SSergey Zigachev case LINK_RATE_HIGH2:
1271*b843c749SSergey Zigachev return LINK_RATE_HIGH;
1272*b843c749SSergey Zigachev case LINK_RATE_HIGH:
1273*b843c749SSergey Zigachev return LINK_RATE_LOW;
1274*b843c749SSergey Zigachev case LINK_RATE_LOW:
1275*b843c749SSergey Zigachev return LINK_RATE_UNKNOWN;
1276*b843c749SSergey Zigachev default:
1277*b843c749SSergey Zigachev return LINK_RATE_UNKNOWN;
1278*b843c749SSergey Zigachev }
1279*b843c749SSergey Zigachev }
1280*b843c749SSergey Zigachev
increase_lane_count(enum dc_lane_count lane_count)1281*b843c749SSergey Zigachev static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
1282*b843c749SSergey Zigachev {
1283*b843c749SSergey Zigachev switch (lane_count) {
1284*b843c749SSergey Zigachev case LANE_COUNT_ONE:
1285*b843c749SSergey Zigachev return LANE_COUNT_TWO;
1286*b843c749SSergey Zigachev case LANE_COUNT_TWO:
1287*b843c749SSergey Zigachev return LANE_COUNT_FOUR;
1288*b843c749SSergey Zigachev default:
1289*b843c749SSergey Zigachev return LANE_COUNT_UNKNOWN;
1290*b843c749SSergey Zigachev }
1291*b843c749SSergey Zigachev }
1292*b843c749SSergey Zigachev
increase_link_rate(enum dc_link_rate link_rate)1293*b843c749SSergey Zigachev static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
1294*b843c749SSergey Zigachev {
1295*b843c749SSergey Zigachev switch (link_rate) {
1296*b843c749SSergey Zigachev case LINK_RATE_LOW:
1297*b843c749SSergey Zigachev return LINK_RATE_HIGH;
1298*b843c749SSergey Zigachev case LINK_RATE_HIGH:
1299*b843c749SSergey Zigachev return LINK_RATE_HIGH2;
1300*b843c749SSergey Zigachev case LINK_RATE_HIGH2:
1301*b843c749SSergey Zigachev return LINK_RATE_HIGH3;
1302*b843c749SSergey Zigachev default:
1303*b843c749SSergey Zigachev return LINK_RATE_UNKNOWN;
1304*b843c749SSergey Zigachev }
1305*b843c749SSergey Zigachev }
1306*b843c749SSergey Zigachev
1307*b843c749SSergey Zigachev /*
1308*b843c749SSergey Zigachev * function: set link rate and lane count fallback based
1309*b843c749SSergey Zigachev * on current link setting and last link training result
1310*b843c749SSergey Zigachev * return value:
1311*b843c749SSergey Zigachev * true - link setting could be set
1312*b843c749SSergey Zigachev * false - has reached minimum setting
1313*b843c749SSergey Zigachev * and no further fallback could be done
1314*b843c749SSergey Zigachev */
decide_fallback_link_setting(struct dc_link_settings initial_link_settings,struct dc_link_settings * current_link_setting,enum link_training_result training_result)1315*b843c749SSergey Zigachev static bool decide_fallback_link_setting(
1316*b843c749SSergey Zigachev struct dc_link_settings initial_link_settings,
1317*b843c749SSergey Zigachev struct dc_link_settings *current_link_setting,
1318*b843c749SSergey Zigachev enum link_training_result training_result)
1319*b843c749SSergey Zigachev {
1320*b843c749SSergey Zigachev if (!current_link_setting)
1321*b843c749SSergey Zigachev return false;
1322*b843c749SSergey Zigachev
1323*b843c749SSergey Zigachev switch (training_result) {
1324*b843c749SSergey Zigachev case LINK_TRAINING_CR_FAIL_LANE0:
1325*b843c749SSergey Zigachev case LINK_TRAINING_CR_FAIL_LANE1:
1326*b843c749SSergey Zigachev case LINK_TRAINING_CR_FAIL_LANE23:
1327*b843c749SSergey Zigachev case LINK_TRAINING_LQA_FAIL:
1328*b843c749SSergey Zigachev {
1329*b843c749SSergey Zigachev if (!reached_minimum_link_rate
1330*b843c749SSergey Zigachev (current_link_setting->link_rate)) {
1331*b843c749SSergey Zigachev current_link_setting->link_rate =
1332*b843c749SSergey Zigachev reduce_link_rate(
1333*b843c749SSergey Zigachev current_link_setting->link_rate);
1334*b843c749SSergey Zigachev } else if (!reached_minimum_lane_count
1335*b843c749SSergey Zigachev (current_link_setting->lane_count)) {
1336*b843c749SSergey Zigachev current_link_setting->link_rate =
1337*b843c749SSergey Zigachev initial_link_settings.link_rate;
1338*b843c749SSergey Zigachev if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
1339*b843c749SSergey Zigachev return false;
1340*b843c749SSergey Zigachev else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
1341*b843c749SSergey Zigachev current_link_setting->lane_count =
1342*b843c749SSergey Zigachev LANE_COUNT_ONE;
1343*b843c749SSergey Zigachev else if (training_result ==
1344*b843c749SSergey Zigachev LINK_TRAINING_CR_FAIL_LANE23)
1345*b843c749SSergey Zigachev current_link_setting->lane_count =
1346*b843c749SSergey Zigachev LANE_COUNT_TWO;
1347*b843c749SSergey Zigachev else
1348*b843c749SSergey Zigachev current_link_setting->lane_count =
1349*b843c749SSergey Zigachev reduce_lane_count(
1350*b843c749SSergey Zigachev current_link_setting->lane_count);
1351*b843c749SSergey Zigachev } else {
1352*b843c749SSergey Zigachev return false;
1353*b843c749SSergey Zigachev }
1354*b843c749SSergey Zigachev break;
1355*b843c749SSergey Zigachev }
1356*b843c749SSergey Zigachev case LINK_TRAINING_EQ_FAIL_EQ:
1357*b843c749SSergey Zigachev {
1358*b843c749SSergey Zigachev if (!reached_minimum_lane_count
1359*b843c749SSergey Zigachev (current_link_setting->lane_count)) {
1360*b843c749SSergey Zigachev current_link_setting->lane_count =
1361*b843c749SSergey Zigachev reduce_lane_count(
1362*b843c749SSergey Zigachev current_link_setting->lane_count);
1363*b843c749SSergey Zigachev } else if (!reached_minimum_link_rate
1364*b843c749SSergey Zigachev (current_link_setting->link_rate)) {
1365*b843c749SSergey Zigachev current_link_setting->link_rate =
1366*b843c749SSergey Zigachev reduce_link_rate(
1367*b843c749SSergey Zigachev current_link_setting->link_rate);
1368*b843c749SSergey Zigachev } else {
1369*b843c749SSergey Zigachev return false;
1370*b843c749SSergey Zigachev }
1371*b843c749SSergey Zigachev break;
1372*b843c749SSergey Zigachev }
1373*b843c749SSergey Zigachev case LINK_TRAINING_EQ_FAIL_CR:
1374*b843c749SSergey Zigachev {
1375*b843c749SSergey Zigachev if (!reached_minimum_link_rate
1376*b843c749SSergey Zigachev (current_link_setting->link_rate)) {
1377*b843c749SSergey Zigachev current_link_setting->link_rate =
1378*b843c749SSergey Zigachev reduce_link_rate(
1379*b843c749SSergey Zigachev current_link_setting->link_rate);
1380*b843c749SSergey Zigachev } else {
1381*b843c749SSergey Zigachev return false;
1382*b843c749SSergey Zigachev }
1383*b843c749SSergey Zigachev break;
1384*b843c749SSergey Zigachev }
1385*b843c749SSergey Zigachev default:
1386*b843c749SSergey Zigachev return false;
1387*b843c749SSergey Zigachev }
1388*b843c749SSergey Zigachev return true;
1389*b843c749SSergey Zigachev }
1390*b843c749SSergey Zigachev
bandwidth_in_kbps_from_timing(const struct dc_crtc_timing * timing)1391*b843c749SSergey Zigachev static uint32_t bandwidth_in_kbps_from_timing(
1392*b843c749SSergey Zigachev const struct dc_crtc_timing *timing)
1393*b843c749SSergey Zigachev {
1394*b843c749SSergey Zigachev uint32_t bits_per_channel = 0;
1395*b843c749SSergey Zigachev uint32_t kbps;
1396*b843c749SSergey Zigachev
1397*b843c749SSergey Zigachev switch (timing->display_color_depth) {
1398*b843c749SSergey Zigachev case COLOR_DEPTH_666:
1399*b843c749SSergey Zigachev bits_per_channel = 6;
1400*b843c749SSergey Zigachev break;
1401*b843c749SSergey Zigachev case COLOR_DEPTH_888:
1402*b843c749SSergey Zigachev bits_per_channel = 8;
1403*b843c749SSergey Zigachev break;
1404*b843c749SSergey Zigachev case COLOR_DEPTH_101010:
1405*b843c749SSergey Zigachev bits_per_channel = 10;
1406*b843c749SSergey Zigachev break;
1407*b843c749SSergey Zigachev case COLOR_DEPTH_121212:
1408*b843c749SSergey Zigachev bits_per_channel = 12;
1409*b843c749SSergey Zigachev break;
1410*b843c749SSergey Zigachev case COLOR_DEPTH_141414:
1411*b843c749SSergey Zigachev bits_per_channel = 14;
1412*b843c749SSergey Zigachev break;
1413*b843c749SSergey Zigachev case COLOR_DEPTH_161616:
1414*b843c749SSergey Zigachev bits_per_channel = 16;
1415*b843c749SSergey Zigachev break;
1416*b843c749SSergey Zigachev default:
1417*b843c749SSergey Zigachev break;
1418*b843c749SSergey Zigachev }
1419*b843c749SSergey Zigachev
1420*b843c749SSergey Zigachev ASSERT(bits_per_channel != 0);
1421*b843c749SSergey Zigachev
1422*b843c749SSergey Zigachev kbps = timing->pix_clk_khz;
1423*b843c749SSergey Zigachev kbps *= bits_per_channel;
1424*b843c749SSergey Zigachev
1425*b843c749SSergey Zigachev if (timing->flags.Y_ONLY != 1) {
1426*b843c749SSergey Zigachev /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
1427*b843c749SSergey Zigachev kbps *= 3;
1428*b843c749SSergey Zigachev if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
1429*b843c749SSergey Zigachev kbps /= 2;
1430*b843c749SSergey Zigachev else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
1431*b843c749SSergey Zigachev kbps = kbps * 2 / 3;
1432*b843c749SSergey Zigachev }
1433*b843c749SSergey Zigachev
1434*b843c749SSergey Zigachev return kbps;
1435*b843c749SSergey Zigachev
1436*b843c749SSergey Zigachev }
1437*b843c749SSergey Zigachev
bandwidth_in_kbps_from_link_settings(const struct dc_link_settings * link_setting)1438*b843c749SSergey Zigachev static uint32_t bandwidth_in_kbps_from_link_settings(
1439*b843c749SSergey Zigachev const struct dc_link_settings *link_setting)
1440*b843c749SSergey Zigachev {
1441*b843c749SSergey Zigachev uint32_t link_rate_in_kbps = link_setting->link_rate *
1442*b843c749SSergey Zigachev LINK_RATE_REF_FREQ_IN_KHZ;
1443*b843c749SSergey Zigachev
1444*b843c749SSergey Zigachev uint32_t lane_count = link_setting->lane_count;
1445*b843c749SSergey Zigachev uint32_t kbps = link_rate_in_kbps;
1446*b843c749SSergey Zigachev
1447*b843c749SSergey Zigachev kbps *= lane_count;
1448*b843c749SSergey Zigachev kbps *= 8; /* 8 bits per byte*/
1449*b843c749SSergey Zigachev
1450*b843c749SSergey Zigachev return kbps;
1451*b843c749SSergey Zigachev
1452*b843c749SSergey Zigachev }
1453*b843c749SSergey Zigachev
dp_validate_mode_timing(struct dc_link * link,const struct dc_crtc_timing * timing)1454*b843c749SSergey Zigachev bool dp_validate_mode_timing(
1455*b843c749SSergey Zigachev struct dc_link *link,
1456*b843c749SSergey Zigachev const struct dc_crtc_timing *timing)
1457*b843c749SSergey Zigachev {
1458*b843c749SSergey Zigachev uint32_t req_bw;
1459*b843c749SSergey Zigachev uint32_t max_bw;
1460*b843c749SSergey Zigachev
1461*b843c749SSergey Zigachev const struct dc_link_settings *link_setting;
1462*b843c749SSergey Zigachev
1463*b843c749SSergey Zigachev /*always DP fail safe mode*/
1464*b843c749SSergey Zigachev if (timing->pix_clk_khz == (uint32_t) 25175 &&
1465*b843c749SSergey Zigachev timing->h_addressable == (uint32_t) 640 &&
1466*b843c749SSergey Zigachev timing->v_addressable == (uint32_t) 480)
1467*b843c749SSergey Zigachev return true;
1468*b843c749SSergey Zigachev
1469*b843c749SSergey Zigachev /* We always use verified link settings */
1470*b843c749SSergey Zigachev link_setting = &link->verified_link_cap;
1471*b843c749SSergey Zigachev
1472*b843c749SSergey Zigachev /* TODO: DYNAMIC_VALIDATION needs to be implemented */
1473*b843c749SSergey Zigachev /*if (flags.DYNAMIC_VALIDATION == 1 &&
1474*b843c749SSergey Zigachev link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
1475*b843c749SSergey Zigachev link_setting = &link->verified_link_cap;
1476*b843c749SSergey Zigachev */
1477*b843c749SSergey Zigachev
1478*b843c749SSergey Zigachev req_bw = bandwidth_in_kbps_from_timing(timing);
1479*b843c749SSergey Zigachev max_bw = bandwidth_in_kbps_from_link_settings(link_setting);
1480*b843c749SSergey Zigachev
1481*b843c749SSergey Zigachev if (req_bw <= max_bw) {
1482*b843c749SSergey Zigachev /* remember the biggest mode here, during
1483*b843c749SSergey Zigachev * initial link training (to get
1484*b843c749SSergey Zigachev * verified_link_cap), LS sends event about
1485*b843c749SSergey Zigachev * cannot train at reported cap to upper
1486*b843c749SSergey Zigachev * layer and upper layer will re-enumerate modes.
1487*b843c749SSergey Zigachev * this is not necessary if the lower
1488*b843c749SSergey Zigachev * verified_link_cap is enough to drive
1489*b843c749SSergey Zigachev * all the modes */
1490*b843c749SSergey Zigachev
1491*b843c749SSergey Zigachev /* TODO: DYNAMIC_VALIDATION needs to be implemented */
1492*b843c749SSergey Zigachev /* if (flags.DYNAMIC_VALIDATION == 1)
1493*b843c749SSergey Zigachev dpsst->max_req_bw_for_verified_linkcap = dal_max(
1494*b843c749SSergey Zigachev dpsst->max_req_bw_for_verified_linkcap, req_bw); */
1495*b843c749SSergey Zigachev return true;
1496*b843c749SSergey Zigachev } else
1497*b843c749SSergey Zigachev return false;
1498*b843c749SSergey Zigachev }
1499*b843c749SSergey Zigachev
decide_link_settings(struct dc_stream_state * stream,struct dc_link_settings * link_setting)1500*b843c749SSergey Zigachev void decide_link_settings(struct dc_stream_state *stream,
1501*b843c749SSergey Zigachev struct dc_link_settings *link_setting)
1502*b843c749SSergey Zigachev {
1503*b843c749SSergey Zigachev
1504*b843c749SSergey Zigachev struct dc_link_settings initial_link_setting = {
1505*b843c749SSergey Zigachev LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED};
1506*b843c749SSergey Zigachev struct dc_link_settings current_link_setting =
1507*b843c749SSergey Zigachev initial_link_setting;
1508*b843c749SSergey Zigachev struct dc_link *link;
1509*b843c749SSergey Zigachev uint32_t req_bw;
1510*b843c749SSergey Zigachev uint32_t link_bw;
1511*b843c749SSergey Zigachev
1512*b843c749SSergey Zigachev req_bw = bandwidth_in_kbps_from_timing(&stream->timing);
1513*b843c749SSergey Zigachev
1514*b843c749SSergey Zigachev link = stream->sink->link;
1515*b843c749SSergey Zigachev
1516*b843c749SSergey Zigachev /* if preferred is specified through AMDDP, use it, if it's enough
1517*b843c749SSergey Zigachev * to drive the mode
1518*b843c749SSergey Zigachev */
1519*b843c749SSergey Zigachev if (link->preferred_link_setting.lane_count !=
1520*b843c749SSergey Zigachev LANE_COUNT_UNKNOWN &&
1521*b843c749SSergey Zigachev link->preferred_link_setting.link_rate !=
1522*b843c749SSergey Zigachev LINK_RATE_UNKNOWN) {
1523*b843c749SSergey Zigachev *link_setting = link->preferred_link_setting;
1524*b843c749SSergey Zigachev return;
1525*b843c749SSergey Zigachev }
1526*b843c749SSergey Zigachev
1527*b843c749SSergey Zigachev /* MST doesn't perform link training for now
1528*b843c749SSergey Zigachev * TODO: add MST specific link training routine
1529*b843c749SSergey Zigachev */
1530*b843c749SSergey Zigachev if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1531*b843c749SSergey Zigachev *link_setting = link->verified_link_cap;
1532*b843c749SSergey Zigachev return;
1533*b843c749SSergey Zigachev }
1534*b843c749SSergey Zigachev
1535*b843c749SSergey Zigachev /* EDP use the link cap setting */
1536*b843c749SSergey Zigachev if (stream->sink->sink_signal == SIGNAL_TYPE_EDP) {
1537*b843c749SSergey Zigachev *link_setting = link->verified_link_cap;
1538*b843c749SSergey Zigachev return;
1539*b843c749SSergey Zigachev }
1540*b843c749SSergey Zigachev
1541*b843c749SSergey Zigachev /* search for the minimum link setting that:
1542*b843c749SSergey Zigachev * 1. is supported according to the link training result
1543*b843c749SSergey Zigachev * 2. could support the b/w requested by the timing
1544*b843c749SSergey Zigachev */
1545*b843c749SSergey Zigachev while (current_link_setting.link_rate <=
1546*b843c749SSergey Zigachev link->verified_link_cap.link_rate) {
1547*b843c749SSergey Zigachev link_bw = bandwidth_in_kbps_from_link_settings(
1548*b843c749SSergey Zigachev ¤t_link_setting);
1549*b843c749SSergey Zigachev if (req_bw <= link_bw) {
1550*b843c749SSergey Zigachev *link_setting = current_link_setting;
1551*b843c749SSergey Zigachev return;
1552*b843c749SSergey Zigachev }
1553*b843c749SSergey Zigachev
1554*b843c749SSergey Zigachev if (current_link_setting.lane_count <
1555*b843c749SSergey Zigachev link->verified_link_cap.lane_count) {
1556*b843c749SSergey Zigachev current_link_setting.lane_count =
1557*b843c749SSergey Zigachev increase_lane_count(
1558*b843c749SSergey Zigachev current_link_setting.lane_count);
1559*b843c749SSergey Zigachev } else {
1560*b843c749SSergey Zigachev current_link_setting.link_rate =
1561*b843c749SSergey Zigachev increase_link_rate(
1562*b843c749SSergey Zigachev current_link_setting.link_rate);
1563*b843c749SSergey Zigachev current_link_setting.lane_count =
1564*b843c749SSergey Zigachev initial_link_setting.lane_count;
1565*b843c749SSergey Zigachev }
1566*b843c749SSergey Zigachev }
1567*b843c749SSergey Zigachev
1568*b843c749SSergey Zigachev BREAK_TO_DEBUGGER();
1569*b843c749SSergey Zigachev ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
1570*b843c749SSergey Zigachev
1571*b843c749SSergey Zigachev *link_setting = link->verified_link_cap;
1572*b843c749SSergey Zigachev }
1573*b843c749SSergey Zigachev
1574*b843c749SSergey Zigachev /*************************Short Pulse IRQ***************************/
1575*b843c749SSergey Zigachev
hpd_rx_irq_check_link_loss_status(struct dc_link * link,union hpd_irq_data * hpd_irq_dpcd_data)1576*b843c749SSergey Zigachev static bool hpd_rx_irq_check_link_loss_status(
1577*b843c749SSergey Zigachev struct dc_link *link,
1578*b843c749SSergey Zigachev union hpd_irq_data *hpd_irq_dpcd_data)
1579*b843c749SSergey Zigachev {
1580*b843c749SSergey Zigachev uint8_t irq_reg_rx_power_state = 0;
1581*b843c749SSergey Zigachev enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
1582*b843c749SSergey Zigachev union lane_status lane_status;
1583*b843c749SSergey Zigachev uint32_t lane;
1584*b843c749SSergey Zigachev bool sink_status_changed;
1585*b843c749SSergey Zigachev bool return_code;
1586*b843c749SSergey Zigachev
1587*b843c749SSergey Zigachev sink_status_changed = false;
1588*b843c749SSergey Zigachev return_code = false;
1589*b843c749SSergey Zigachev
1590*b843c749SSergey Zigachev if (link->cur_link_settings.lane_count == 0)
1591*b843c749SSergey Zigachev return return_code;
1592*b843c749SSergey Zigachev
1593*b843c749SSergey Zigachev /*1. Check that Link Status changed, before re-training.*/
1594*b843c749SSergey Zigachev
1595*b843c749SSergey Zigachev /*parse lane status*/
1596*b843c749SSergey Zigachev for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1597*b843c749SSergey Zigachev /* check status of lanes 0,1
1598*b843c749SSergey Zigachev * changed DpcdAddress_Lane01Status (0x202)
1599*b843c749SSergey Zigachev */
1600*b843c749SSergey Zigachev lane_status.raw = get_nibble_at_index(
1601*b843c749SSergey Zigachev &hpd_irq_dpcd_data->bytes.lane01_status.raw,
1602*b843c749SSergey Zigachev lane);
1603*b843c749SSergey Zigachev
1604*b843c749SSergey Zigachev if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1605*b843c749SSergey Zigachev !lane_status.bits.CR_DONE_0 ||
1606*b843c749SSergey Zigachev !lane_status.bits.SYMBOL_LOCKED_0) {
1607*b843c749SSergey Zigachev /* if one of the channel equalization, clock
1608*b843c749SSergey Zigachev * recovery or symbol lock is dropped
1609*b843c749SSergey Zigachev * consider it as (link has been
1610*b843c749SSergey Zigachev * dropped) dp sink status has changed
1611*b843c749SSergey Zigachev */
1612*b843c749SSergey Zigachev sink_status_changed = true;
1613*b843c749SSergey Zigachev break;
1614*b843c749SSergey Zigachev }
1615*b843c749SSergey Zigachev }
1616*b843c749SSergey Zigachev
1617*b843c749SSergey Zigachev /* Check interlane align.*/
1618*b843c749SSergey Zigachev if (sink_status_changed ||
1619*b843c749SSergey Zigachev !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
1620*b843c749SSergey Zigachev
1621*b843c749SSergey Zigachev DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
1622*b843c749SSergey Zigachev
1623*b843c749SSergey Zigachev return_code = true;
1624*b843c749SSergey Zigachev
1625*b843c749SSergey Zigachev /*2. Check that we can handle interrupt: Not in FS DOS,
1626*b843c749SSergey Zigachev * Not in "Display Timeout" state, Link is trained.
1627*b843c749SSergey Zigachev */
1628*b843c749SSergey Zigachev dpcd_result = core_link_read_dpcd(link,
1629*b843c749SSergey Zigachev DP_SET_POWER,
1630*b843c749SSergey Zigachev &irq_reg_rx_power_state,
1631*b843c749SSergey Zigachev sizeof(irq_reg_rx_power_state));
1632*b843c749SSergey Zigachev
1633*b843c749SSergey Zigachev if (dpcd_result != DC_OK) {
1634*b843c749SSergey Zigachev DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
1635*b843c749SSergey Zigachev __func__);
1636*b843c749SSergey Zigachev } else {
1637*b843c749SSergey Zigachev if (irq_reg_rx_power_state != DP_SET_POWER_D0)
1638*b843c749SSergey Zigachev return_code = false;
1639*b843c749SSergey Zigachev }
1640*b843c749SSergey Zigachev }
1641*b843c749SSergey Zigachev
1642*b843c749SSergey Zigachev return return_code;
1643*b843c749SSergey Zigachev }
1644*b843c749SSergey Zigachev
read_hpd_rx_irq_data(struct dc_link * link,union hpd_irq_data * irq_data)1645*b843c749SSergey Zigachev static enum dc_status read_hpd_rx_irq_data(
1646*b843c749SSergey Zigachev struct dc_link *link,
1647*b843c749SSergey Zigachev union hpd_irq_data *irq_data)
1648*b843c749SSergey Zigachev {
1649*b843c749SSergey Zigachev static enum dc_status retval;
1650*b843c749SSergey Zigachev
1651*b843c749SSergey Zigachev /* The HW reads 16 bytes from 200h on HPD,
1652*b843c749SSergey Zigachev * but if we get an AUX_DEFER, the HW cannot retry
1653*b843c749SSergey Zigachev * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
1654*b843c749SSergey Zigachev * fail, so we now explicitly read 6 bytes which is
1655*b843c749SSergey Zigachev * the req from the above mentioned test cases.
1656*b843c749SSergey Zigachev *
1657*b843c749SSergey Zigachev * For DP 1.4 we need to read those from 2002h range.
1658*b843c749SSergey Zigachev */
1659*b843c749SSergey Zigachev if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
1660*b843c749SSergey Zigachev retval = core_link_read_dpcd(
1661*b843c749SSergey Zigachev link,
1662*b843c749SSergey Zigachev DP_SINK_COUNT,
1663*b843c749SSergey Zigachev irq_data->raw,
1664*b843c749SSergey Zigachev sizeof(union hpd_irq_data));
1665*b843c749SSergey Zigachev else {
1666*b843c749SSergey Zigachev /* Read 14 bytes in a single read and then copy only the required fields.
1667*b843c749SSergey Zigachev * This is more efficient than doing it in two separate AUX reads. */
1668*b843c749SSergey Zigachev
1669*b843c749SSergey Zigachev uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
1670*b843c749SSergey Zigachev
1671*b843c749SSergey Zigachev retval = core_link_read_dpcd(
1672*b843c749SSergey Zigachev link,
1673*b843c749SSergey Zigachev DP_SINK_COUNT_ESI,
1674*b843c749SSergey Zigachev tmp,
1675*b843c749SSergey Zigachev sizeof(tmp));
1676*b843c749SSergey Zigachev
1677*b843c749SSergey Zigachev if (retval != DC_OK)
1678*b843c749SSergey Zigachev return retval;
1679*b843c749SSergey Zigachev
1680*b843c749SSergey Zigachev irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
1681*b843c749SSergey Zigachev irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
1682*b843c749SSergey Zigachev irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
1683*b843c749SSergey Zigachev irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
1684*b843c749SSergey Zigachev irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
1685*b843c749SSergey Zigachev irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
1686*b843c749SSergey Zigachev }
1687*b843c749SSergey Zigachev
1688*b843c749SSergey Zigachev return retval;
1689*b843c749SSergey Zigachev }
1690*b843c749SSergey Zigachev
allow_hpd_rx_irq(const struct dc_link * link)1691*b843c749SSergey Zigachev static bool allow_hpd_rx_irq(const struct dc_link *link)
1692*b843c749SSergey Zigachev {
1693*b843c749SSergey Zigachev /*
1694*b843c749SSergey Zigachev * Don't handle RX IRQ unless one of following is met:
1695*b843c749SSergey Zigachev * 1) The link is established (cur_link_settings != unknown)
1696*b843c749SSergey Zigachev * 2) We kicked off MST detection
1697*b843c749SSergey Zigachev * 3) We know we're dealing with an active dongle
1698*b843c749SSergey Zigachev */
1699*b843c749SSergey Zigachev
1700*b843c749SSergey Zigachev if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1701*b843c749SSergey Zigachev (link->type == dc_connection_mst_branch) ||
1702*b843c749SSergey Zigachev is_dp_active_dongle(link))
1703*b843c749SSergey Zigachev return true;
1704*b843c749SSergey Zigachev
1705*b843c749SSergey Zigachev return false;
1706*b843c749SSergey Zigachev }
1707*b843c749SSergey Zigachev
handle_hpd_irq_psr_sink(const struct dc_link * link)1708*b843c749SSergey Zigachev static bool handle_hpd_irq_psr_sink(const struct dc_link *link)
1709*b843c749SSergey Zigachev {
1710*b843c749SSergey Zigachev union dpcd_psr_configuration psr_configuration;
1711*b843c749SSergey Zigachev
1712*b843c749SSergey Zigachev if (!link->psr_enabled)
1713*b843c749SSergey Zigachev return false;
1714*b843c749SSergey Zigachev
1715*b843c749SSergey Zigachev dm_helpers_dp_read_dpcd(
1716*b843c749SSergey Zigachev link->ctx,
1717*b843c749SSergey Zigachev link,
1718*b843c749SSergey Zigachev 368,/*DpcdAddress_PSR_Enable_Cfg*/
1719*b843c749SSergey Zigachev &psr_configuration.raw,
1720*b843c749SSergey Zigachev sizeof(psr_configuration.raw));
1721*b843c749SSergey Zigachev
1722*b843c749SSergey Zigachev
1723*b843c749SSergey Zigachev if (psr_configuration.bits.ENABLE) {
1724*b843c749SSergey Zigachev unsigned char dpcdbuf[3] = {0};
1725*b843c749SSergey Zigachev union psr_error_status psr_error_status;
1726*b843c749SSergey Zigachev union psr_sink_psr_status psr_sink_psr_status;
1727*b843c749SSergey Zigachev
1728*b843c749SSergey Zigachev dm_helpers_dp_read_dpcd(
1729*b843c749SSergey Zigachev link->ctx,
1730*b843c749SSergey Zigachev link,
1731*b843c749SSergey Zigachev 0x2006, /*DpcdAddress_PSR_Error_Status*/
1732*b843c749SSergey Zigachev (unsigned char *) dpcdbuf,
1733*b843c749SSergey Zigachev sizeof(dpcdbuf));
1734*b843c749SSergey Zigachev
1735*b843c749SSergey Zigachev /*DPCD 2006h ERROR STATUS*/
1736*b843c749SSergey Zigachev psr_error_status.raw = dpcdbuf[0];
1737*b843c749SSergey Zigachev /*DPCD 2008h SINK PANEL SELF REFRESH STATUS*/
1738*b843c749SSergey Zigachev psr_sink_psr_status.raw = dpcdbuf[2];
1739*b843c749SSergey Zigachev
1740*b843c749SSergey Zigachev if (psr_error_status.bits.LINK_CRC_ERROR ||
1741*b843c749SSergey Zigachev psr_error_status.bits.RFB_STORAGE_ERROR) {
1742*b843c749SSergey Zigachev /* Acknowledge and clear error bits */
1743*b843c749SSergey Zigachev dm_helpers_dp_write_dpcd(
1744*b843c749SSergey Zigachev link->ctx,
1745*b843c749SSergey Zigachev link,
1746*b843c749SSergey Zigachev 8198,/*DpcdAddress_PSR_Error_Status*/
1747*b843c749SSergey Zigachev &psr_error_status.raw,
1748*b843c749SSergey Zigachev sizeof(psr_error_status.raw));
1749*b843c749SSergey Zigachev
1750*b843c749SSergey Zigachev /* PSR error, disable and re-enable PSR */
1751*b843c749SSergey Zigachev dc_link_set_psr_enable(link, false, true);
1752*b843c749SSergey Zigachev dc_link_set_psr_enable(link, true, true);
1753*b843c749SSergey Zigachev
1754*b843c749SSergey Zigachev return true;
1755*b843c749SSergey Zigachev } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
1756*b843c749SSergey Zigachev PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
1757*b843c749SSergey Zigachev /* No error is detect, PSR is active.
1758*b843c749SSergey Zigachev * We should return with IRQ_HPD handled without
1759*b843c749SSergey Zigachev * checking for loss of sync since PSR would have
1760*b843c749SSergey Zigachev * powered down main link.
1761*b843c749SSergey Zigachev */
1762*b843c749SSergey Zigachev return true;
1763*b843c749SSergey Zigachev }
1764*b843c749SSergey Zigachev }
1765*b843c749SSergey Zigachev return false;
1766*b843c749SSergey Zigachev }
1767*b843c749SSergey Zigachev
dp_test_send_link_training(struct dc_link * link)1768*b843c749SSergey Zigachev static void dp_test_send_link_training(struct dc_link *link)
1769*b843c749SSergey Zigachev {
1770*b843c749SSergey Zigachev struct dc_link_settings link_settings = {0};
1771*b843c749SSergey Zigachev
1772*b843c749SSergey Zigachev core_link_read_dpcd(
1773*b843c749SSergey Zigachev link,
1774*b843c749SSergey Zigachev DP_TEST_LANE_COUNT,
1775*b843c749SSergey Zigachev (unsigned char *)(&link_settings.lane_count),
1776*b843c749SSergey Zigachev 1);
1777*b843c749SSergey Zigachev core_link_read_dpcd(
1778*b843c749SSergey Zigachev link,
1779*b843c749SSergey Zigachev DP_TEST_LINK_RATE,
1780*b843c749SSergey Zigachev (unsigned char *)(&link_settings.link_rate),
1781*b843c749SSergey Zigachev 1);
1782*b843c749SSergey Zigachev
1783*b843c749SSergey Zigachev /* Set preferred link settings */
1784*b843c749SSergey Zigachev link->verified_link_cap.lane_count = link_settings.lane_count;
1785*b843c749SSergey Zigachev link->verified_link_cap.link_rate = link_settings.link_rate;
1786*b843c749SSergey Zigachev
1787*b843c749SSergey Zigachev dp_retrain_link_dp_test(link, &link_settings, false);
1788*b843c749SSergey Zigachev }
1789*b843c749SSergey Zigachev
1790*b843c749SSergey Zigachev /* TODO Raven hbr2 compliance eye output is unstable
1791*b843c749SSergey Zigachev * (toggling on and off) with debugger break
1792*b843c749SSergey Zigachev * This caueses intermittent PHY automation failure
1793*b843c749SSergey Zigachev * Need to look into the root cause */
dp_test_send_phy_test_pattern(struct dc_link * link)1794*b843c749SSergey Zigachev static void dp_test_send_phy_test_pattern(struct dc_link *link)
1795*b843c749SSergey Zigachev {
1796*b843c749SSergey Zigachev union phy_test_pattern dpcd_test_pattern;
1797*b843c749SSergey Zigachev union lane_adjust dpcd_lane_adjustment[2];
1798*b843c749SSergey Zigachev unsigned char dpcd_post_cursor_2_adjustment = 0;
1799*b843c749SSergey Zigachev unsigned char test_80_bit_pattern[
1800*b843c749SSergey Zigachev (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
1801*b843c749SSergey Zigachev DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
1802*b843c749SSergey Zigachev enum dp_test_pattern test_pattern;
1803*b843c749SSergey Zigachev struct dc_link_training_settings link_settings;
1804*b843c749SSergey Zigachev union lane_adjust dpcd_lane_adjust;
1805*b843c749SSergey Zigachev unsigned int lane;
1806*b843c749SSergey Zigachev struct link_training_settings link_training_settings;
1807*b843c749SSergey Zigachev int i = 0;
1808*b843c749SSergey Zigachev
1809*b843c749SSergey Zigachev dpcd_test_pattern.raw = 0;
1810*b843c749SSergey Zigachev memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
1811*b843c749SSergey Zigachev memset(&link_settings, 0, sizeof(link_settings));
1812*b843c749SSergey Zigachev
1813*b843c749SSergey Zigachev /* get phy test pattern and pattern parameters from DP receiver */
1814*b843c749SSergey Zigachev core_link_read_dpcd(
1815*b843c749SSergey Zigachev link,
1816*b843c749SSergey Zigachev DP_TEST_PHY_PATTERN,
1817*b843c749SSergey Zigachev &dpcd_test_pattern.raw,
1818*b843c749SSergey Zigachev sizeof(dpcd_test_pattern));
1819*b843c749SSergey Zigachev core_link_read_dpcd(
1820*b843c749SSergey Zigachev link,
1821*b843c749SSergey Zigachev DP_ADJUST_REQUEST_LANE0_1,
1822*b843c749SSergey Zigachev &dpcd_lane_adjustment[0].raw,
1823*b843c749SSergey Zigachev sizeof(dpcd_lane_adjustment));
1824*b843c749SSergey Zigachev
1825*b843c749SSergey Zigachev /*get post cursor 2 parameters
1826*b843c749SSergey Zigachev * For DP 1.1a or eariler, this DPCD register's value is 0
1827*b843c749SSergey Zigachev * For DP 1.2 or later:
1828*b843c749SSergey Zigachev * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
1829*b843c749SSergey Zigachev * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
1830*b843c749SSergey Zigachev */
1831*b843c749SSergey Zigachev core_link_read_dpcd(
1832*b843c749SSergey Zigachev link,
1833*b843c749SSergey Zigachev DP_ADJUST_REQUEST_POST_CURSOR2,
1834*b843c749SSergey Zigachev &dpcd_post_cursor_2_adjustment,
1835*b843c749SSergey Zigachev sizeof(dpcd_post_cursor_2_adjustment));
1836*b843c749SSergey Zigachev
1837*b843c749SSergey Zigachev /* translate request */
1838*b843c749SSergey Zigachev switch (dpcd_test_pattern.bits.PATTERN) {
1839*b843c749SSergey Zigachev case PHY_TEST_PATTERN_D10_2:
1840*b843c749SSergey Zigachev test_pattern = DP_TEST_PATTERN_D102;
1841*b843c749SSergey Zigachev break;
1842*b843c749SSergey Zigachev case PHY_TEST_PATTERN_SYMBOL_ERROR:
1843*b843c749SSergey Zigachev test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
1844*b843c749SSergey Zigachev break;
1845*b843c749SSergey Zigachev case PHY_TEST_PATTERN_PRBS7:
1846*b843c749SSergey Zigachev test_pattern = DP_TEST_PATTERN_PRBS7;
1847*b843c749SSergey Zigachev break;
1848*b843c749SSergey Zigachev case PHY_TEST_PATTERN_80BIT_CUSTOM:
1849*b843c749SSergey Zigachev test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
1850*b843c749SSergey Zigachev break;
1851*b843c749SSergey Zigachev case PHY_TEST_PATTERN_CP2520_1:
1852*b843c749SSergey Zigachev /* CP2520 pattern is unstable, temporarily use TPS4 instead */
1853*b843c749SSergey Zigachev test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
1854*b843c749SSergey Zigachev DP_TEST_PATTERN_TRAINING_PATTERN4 :
1855*b843c749SSergey Zigachev DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
1856*b843c749SSergey Zigachev break;
1857*b843c749SSergey Zigachev case PHY_TEST_PATTERN_CP2520_2:
1858*b843c749SSergey Zigachev /* CP2520 pattern is unstable, temporarily use TPS4 instead */
1859*b843c749SSergey Zigachev test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
1860*b843c749SSergey Zigachev DP_TEST_PATTERN_TRAINING_PATTERN4 :
1861*b843c749SSergey Zigachev DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
1862*b843c749SSergey Zigachev break;
1863*b843c749SSergey Zigachev case PHY_TEST_PATTERN_CP2520_3:
1864*b843c749SSergey Zigachev test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
1865*b843c749SSergey Zigachev break;
1866*b843c749SSergey Zigachev default:
1867*b843c749SSergey Zigachev test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
1868*b843c749SSergey Zigachev break;
1869*b843c749SSergey Zigachev }
1870*b843c749SSergey Zigachev
1871*b843c749SSergey Zigachev if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM)
1872*b843c749SSergey Zigachev core_link_read_dpcd(
1873*b843c749SSergey Zigachev link,
1874*b843c749SSergey Zigachev DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
1875*b843c749SSergey Zigachev test_80_bit_pattern,
1876*b843c749SSergey Zigachev sizeof(test_80_bit_pattern));
1877*b843c749SSergey Zigachev
1878*b843c749SSergey Zigachev /* prepare link training settings */
1879*b843c749SSergey Zigachev link_settings.link = link->cur_link_settings;
1880*b843c749SSergey Zigachev
1881*b843c749SSergey Zigachev for (lane = 0; lane <
1882*b843c749SSergey Zigachev (unsigned int)(link->cur_link_settings.lane_count);
1883*b843c749SSergey Zigachev lane++) {
1884*b843c749SSergey Zigachev dpcd_lane_adjust.raw =
1885*b843c749SSergey Zigachev get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
1886*b843c749SSergey Zigachev link_settings.lane_settings[lane].VOLTAGE_SWING =
1887*b843c749SSergey Zigachev (enum dc_voltage_swing)
1888*b843c749SSergey Zigachev (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
1889*b843c749SSergey Zigachev link_settings.lane_settings[lane].PRE_EMPHASIS =
1890*b843c749SSergey Zigachev (enum dc_pre_emphasis)
1891*b843c749SSergey Zigachev (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
1892*b843c749SSergey Zigachev link_settings.lane_settings[lane].POST_CURSOR2 =
1893*b843c749SSergey Zigachev (enum dc_post_cursor2)
1894*b843c749SSergey Zigachev ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
1895*b843c749SSergey Zigachev }
1896*b843c749SSergey Zigachev
1897*b843c749SSergey Zigachev for (i = 0; i < 4; i++)
1898*b843c749SSergey Zigachev link_training_settings.lane_settings[i] =
1899*b843c749SSergey Zigachev link_settings.lane_settings[i];
1900*b843c749SSergey Zigachev link_training_settings.link_settings = link_settings.link;
1901*b843c749SSergey Zigachev link_training_settings.allow_invalid_msa_timing_param = false;
1902*b843c749SSergey Zigachev /*Usage: Measure DP physical lane signal
1903*b843c749SSergey Zigachev * by DP SI test equipment automatically.
1904*b843c749SSergey Zigachev * PHY test pattern request is generated by equipment via HPD interrupt.
1905*b843c749SSergey Zigachev * HPD needs to be active all the time. HPD should be active
1906*b843c749SSergey Zigachev * all the time. Do not touch it.
1907*b843c749SSergey Zigachev * forward request to DS
1908*b843c749SSergey Zigachev */
1909*b843c749SSergey Zigachev dc_link_dp_set_test_pattern(
1910*b843c749SSergey Zigachev link,
1911*b843c749SSergey Zigachev test_pattern,
1912*b843c749SSergey Zigachev &link_training_settings,
1913*b843c749SSergey Zigachev test_80_bit_pattern,
1914*b843c749SSergey Zigachev (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
1915*b843c749SSergey Zigachev DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1);
1916*b843c749SSergey Zigachev }
1917*b843c749SSergey Zigachev
dp_test_send_link_test_pattern(struct dc_link * link)1918*b843c749SSergey Zigachev static void dp_test_send_link_test_pattern(struct dc_link *link)
1919*b843c749SSergey Zigachev {
1920*b843c749SSergey Zigachev union link_test_pattern dpcd_test_pattern;
1921*b843c749SSergey Zigachev union test_misc dpcd_test_params;
1922*b843c749SSergey Zigachev enum dp_test_pattern test_pattern;
1923*b843c749SSergey Zigachev
1924*b843c749SSergey Zigachev memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
1925*b843c749SSergey Zigachev memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
1926*b843c749SSergey Zigachev
1927*b843c749SSergey Zigachev /* get link test pattern and pattern parameters */
1928*b843c749SSergey Zigachev core_link_read_dpcd(
1929*b843c749SSergey Zigachev link,
1930*b843c749SSergey Zigachev DP_TEST_PATTERN,
1931*b843c749SSergey Zigachev &dpcd_test_pattern.raw,
1932*b843c749SSergey Zigachev sizeof(dpcd_test_pattern));
1933*b843c749SSergey Zigachev core_link_read_dpcd(
1934*b843c749SSergey Zigachev link,
1935*b843c749SSergey Zigachev DP_TEST_MISC0,
1936*b843c749SSergey Zigachev &dpcd_test_params.raw,
1937*b843c749SSergey Zigachev sizeof(dpcd_test_params));
1938*b843c749SSergey Zigachev
1939*b843c749SSergey Zigachev switch (dpcd_test_pattern.bits.PATTERN) {
1940*b843c749SSergey Zigachev case LINK_TEST_PATTERN_COLOR_RAMP:
1941*b843c749SSergey Zigachev test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
1942*b843c749SSergey Zigachev break;
1943*b843c749SSergey Zigachev case LINK_TEST_PATTERN_VERTICAL_BARS:
1944*b843c749SSergey Zigachev test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
1945*b843c749SSergey Zigachev break; /* black and white */
1946*b843c749SSergey Zigachev case LINK_TEST_PATTERN_COLOR_SQUARES:
1947*b843c749SSergey Zigachev test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
1948*b843c749SSergey Zigachev TEST_DYN_RANGE_VESA ?
1949*b843c749SSergey Zigachev DP_TEST_PATTERN_COLOR_SQUARES :
1950*b843c749SSergey Zigachev DP_TEST_PATTERN_COLOR_SQUARES_CEA);
1951*b843c749SSergey Zigachev break;
1952*b843c749SSergey Zigachev default:
1953*b843c749SSergey Zigachev test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
1954*b843c749SSergey Zigachev break;
1955*b843c749SSergey Zigachev }
1956*b843c749SSergey Zigachev
1957*b843c749SSergey Zigachev dc_link_dp_set_test_pattern(
1958*b843c749SSergey Zigachev link,
1959*b843c749SSergey Zigachev test_pattern,
1960*b843c749SSergey Zigachev NULL,
1961*b843c749SSergey Zigachev NULL,
1962*b843c749SSergey Zigachev 0);
1963*b843c749SSergey Zigachev }
1964*b843c749SSergey Zigachev
handle_automated_test(struct dc_link * link)1965*b843c749SSergey Zigachev static void handle_automated_test(struct dc_link *link)
1966*b843c749SSergey Zigachev {
1967*b843c749SSergey Zigachev union test_request test_request;
1968*b843c749SSergey Zigachev union test_response test_response;
1969*b843c749SSergey Zigachev
1970*b843c749SSergey Zigachev memset(&test_request, 0, sizeof(test_request));
1971*b843c749SSergey Zigachev memset(&test_response, 0, sizeof(test_response));
1972*b843c749SSergey Zigachev
1973*b843c749SSergey Zigachev core_link_read_dpcd(
1974*b843c749SSergey Zigachev link,
1975*b843c749SSergey Zigachev DP_TEST_REQUEST,
1976*b843c749SSergey Zigachev &test_request.raw,
1977*b843c749SSergey Zigachev sizeof(union test_request));
1978*b843c749SSergey Zigachev if (test_request.bits.LINK_TRAINING) {
1979*b843c749SSergey Zigachev /* ACK first to let DP RX test box monitor LT sequence */
1980*b843c749SSergey Zigachev test_response.bits.ACK = 1;
1981*b843c749SSergey Zigachev core_link_write_dpcd(
1982*b843c749SSergey Zigachev link,
1983*b843c749SSergey Zigachev DP_TEST_RESPONSE,
1984*b843c749SSergey Zigachev &test_response.raw,
1985*b843c749SSergey Zigachev sizeof(test_response));
1986*b843c749SSergey Zigachev dp_test_send_link_training(link);
1987*b843c749SSergey Zigachev /* no acknowledge request is needed again */
1988*b843c749SSergey Zigachev test_response.bits.ACK = 0;
1989*b843c749SSergey Zigachev }
1990*b843c749SSergey Zigachev if (test_request.bits.LINK_TEST_PATTRN) {
1991*b843c749SSergey Zigachev dp_test_send_link_test_pattern(link);
1992*b843c749SSergey Zigachev test_response.bits.ACK = 1;
1993*b843c749SSergey Zigachev }
1994*b843c749SSergey Zigachev if (test_request.bits.PHY_TEST_PATTERN) {
1995*b843c749SSergey Zigachev dp_test_send_phy_test_pattern(link);
1996*b843c749SSergey Zigachev test_response.bits.ACK = 1;
1997*b843c749SSergey Zigachev }
1998*b843c749SSergey Zigachev if (!test_request.raw)
1999*b843c749SSergey Zigachev /* no requests, revert all test signals
2000*b843c749SSergey Zigachev * TODO: revert all test signals
2001*b843c749SSergey Zigachev */
2002*b843c749SSergey Zigachev test_response.bits.ACK = 1;
2003*b843c749SSergey Zigachev /* send request acknowledgment */
2004*b843c749SSergey Zigachev if (test_response.bits.ACK)
2005*b843c749SSergey Zigachev core_link_write_dpcd(
2006*b843c749SSergey Zigachev link,
2007*b843c749SSergey Zigachev DP_TEST_RESPONSE,
2008*b843c749SSergey Zigachev &test_response.raw,
2009*b843c749SSergey Zigachev sizeof(test_response));
2010*b843c749SSergey Zigachev }
2011*b843c749SSergey Zigachev
dc_link_handle_hpd_rx_irq(struct dc_link * link,union hpd_irq_data * out_hpd_irq_dpcd_data,bool * out_link_loss)2012*b843c749SSergey Zigachev bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
2013*b843c749SSergey Zigachev {
2014*b843c749SSergey Zigachev union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
2015*b843c749SSergey Zigachev union device_service_irq device_service_clear = { { 0 } };
2016*b843c749SSergey Zigachev enum dc_status result;
2017*b843c749SSergey Zigachev
2018*b843c749SSergey Zigachev bool status = false;
2019*b843c749SSergey Zigachev
2020*b843c749SSergey Zigachev if (out_link_loss)
2021*b843c749SSergey Zigachev *out_link_loss = false;
2022*b843c749SSergey Zigachev /* For use cases related to down stream connection status change,
2023*b843c749SSergey Zigachev * PSR and device auto test, refer to function handle_sst_hpd_irq
2024*b843c749SSergey Zigachev * in DAL2.1*/
2025*b843c749SSergey Zigachev
2026*b843c749SSergey Zigachev DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
2027*b843c749SSergey Zigachev __func__, link->link_index);
2028*b843c749SSergey Zigachev
2029*b843c749SSergey Zigachev
2030*b843c749SSergey Zigachev /* All the "handle_hpd_irq_xxx()" methods
2031*b843c749SSergey Zigachev * should be called only after
2032*b843c749SSergey Zigachev * dal_dpsst_ls_read_hpd_irq_data
2033*b843c749SSergey Zigachev * Order of calls is important too
2034*b843c749SSergey Zigachev */
2035*b843c749SSergey Zigachev result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
2036*b843c749SSergey Zigachev if (out_hpd_irq_dpcd_data)
2037*b843c749SSergey Zigachev *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
2038*b843c749SSergey Zigachev
2039*b843c749SSergey Zigachev if (result != DC_OK) {
2040*b843c749SSergey Zigachev DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
2041*b843c749SSergey Zigachev __func__);
2042*b843c749SSergey Zigachev return false;
2043*b843c749SSergey Zigachev }
2044*b843c749SSergey Zigachev
2045*b843c749SSergey Zigachev if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
2046*b843c749SSergey Zigachev device_service_clear.bits.AUTOMATED_TEST = 1;
2047*b843c749SSergey Zigachev core_link_write_dpcd(
2048*b843c749SSergey Zigachev link,
2049*b843c749SSergey Zigachev DP_DEVICE_SERVICE_IRQ_VECTOR,
2050*b843c749SSergey Zigachev &device_service_clear.raw,
2051*b843c749SSergey Zigachev sizeof(device_service_clear.raw));
2052*b843c749SSergey Zigachev device_service_clear.raw = 0;
2053*b843c749SSergey Zigachev handle_automated_test(link);
2054*b843c749SSergey Zigachev return false;
2055*b843c749SSergey Zigachev }
2056*b843c749SSergey Zigachev
2057*b843c749SSergey Zigachev if (!allow_hpd_rx_irq(link)) {
2058*b843c749SSergey Zigachev DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
2059*b843c749SSergey Zigachev __func__, link->link_index);
2060*b843c749SSergey Zigachev return false;
2061*b843c749SSergey Zigachev }
2062*b843c749SSergey Zigachev
2063*b843c749SSergey Zigachev if (handle_hpd_irq_psr_sink(link))
2064*b843c749SSergey Zigachev /* PSR-related error was detected and handled */
2065*b843c749SSergey Zigachev return true;
2066*b843c749SSergey Zigachev
2067*b843c749SSergey Zigachev /* If PSR-related error handled, Main link may be off,
2068*b843c749SSergey Zigachev * so do not handle as a normal sink status change interrupt.
2069*b843c749SSergey Zigachev */
2070*b843c749SSergey Zigachev
2071*b843c749SSergey Zigachev if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
2072*b843c749SSergey Zigachev return true;
2073*b843c749SSergey Zigachev
2074*b843c749SSergey Zigachev /* check if we have MST msg and return since we poll for it */
2075*b843c749SSergey Zigachev if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
2076*b843c749SSergey Zigachev return false;
2077*b843c749SSergey Zigachev
2078*b843c749SSergey Zigachev /* For now we only handle 'Downstream port status' case.
2079*b843c749SSergey Zigachev * If we got sink count changed it means
2080*b843c749SSergey Zigachev * Downstream port status changed,
2081*b843c749SSergey Zigachev * then DM should call DC to do the detection. */
2082*b843c749SSergey Zigachev if (hpd_rx_irq_check_link_loss_status(
2083*b843c749SSergey Zigachev link,
2084*b843c749SSergey Zigachev &hpd_irq_dpcd_data)) {
2085*b843c749SSergey Zigachev /* Connectivity log: link loss */
2086*b843c749SSergey Zigachev CONN_DATA_LINK_LOSS(link,
2087*b843c749SSergey Zigachev hpd_irq_dpcd_data.raw,
2088*b843c749SSergey Zigachev sizeof(hpd_irq_dpcd_data),
2089*b843c749SSergey Zigachev "Status: ");
2090*b843c749SSergey Zigachev
2091*b843c749SSergey Zigachev perform_link_training_with_retries(link,
2092*b843c749SSergey Zigachev &link->cur_link_settings,
2093*b843c749SSergey Zigachev true, LINK_TRAINING_ATTEMPTS);
2094*b843c749SSergey Zigachev
2095*b843c749SSergey Zigachev status = false;
2096*b843c749SSergey Zigachev if (out_link_loss)
2097*b843c749SSergey Zigachev *out_link_loss = true;
2098*b843c749SSergey Zigachev }
2099*b843c749SSergey Zigachev
2100*b843c749SSergey Zigachev if (link->type == dc_connection_active_dongle &&
2101*b843c749SSergey Zigachev hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
2102*b843c749SSergey Zigachev != link->dpcd_sink_count)
2103*b843c749SSergey Zigachev status = true;
2104*b843c749SSergey Zigachev
2105*b843c749SSergey Zigachev /* reasons for HPD RX:
2106*b843c749SSergey Zigachev * 1. Link Loss - ie Re-train the Link
2107*b843c749SSergey Zigachev * 2. MST sideband message
2108*b843c749SSergey Zigachev * 3. Automated Test - ie. Internal Commit
2109*b843c749SSergey Zigachev * 4. CP (copy protection) - (not interesting for DM???)
2110*b843c749SSergey Zigachev * 5. DRR
2111*b843c749SSergey Zigachev * 6. Downstream Port status changed
2112*b843c749SSergey Zigachev * -ie. Detect - this the only one
2113*b843c749SSergey Zigachev * which is interesting for DM because
2114*b843c749SSergey Zigachev * it must call dc_link_detect.
2115*b843c749SSergey Zigachev */
2116*b843c749SSergey Zigachev return status;
2117*b843c749SSergey Zigachev }
2118*b843c749SSergey Zigachev
2119*b843c749SSergey Zigachev /*query dpcd for version and mst cap addresses*/
is_mst_supported(struct dc_link * link)2120*b843c749SSergey Zigachev bool is_mst_supported(struct dc_link *link)
2121*b843c749SSergey Zigachev {
2122*b843c749SSergey Zigachev bool mst = false;
2123*b843c749SSergey Zigachev enum dc_status st = DC_OK;
2124*b843c749SSergey Zigachev union dpcd_rev rev;
2125*b843c749SSergey Zigachev union mstm_cap cap;
2126*b843c749SSergey Zigachev
2127*b843c749SSergey Zigachev rev.raw = 0;
2128*b843c749SSergey Zigachev cap.raw = 0;
2129*b843c749SSergey Zigachev
2130*b843c749SSergey Zigachev st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
2131*b843c749SSergey Zigachev sizeof(rev));
2132*b843c749SSergey Zigachev
2133*b843c749SSergey Zigachev if (st == DC_OK && rev.raw >= DPCD_REV_12) {
2134*b843c749SSergey Zigachev
2135*b843c749SSergey Zigachev st = core_link_read_dpcd(link, DP_MSTM_CAP,
2136*b843c749SSergey Zigachev &cap.raw, sizeof(cap));
2137*b843c749SSergey Zigachev if (st == DC_OK && cap.bits.MST_CAP == 1)
2138*b843c749SSergey Zigachev mst = true;
2139*b843c749SSergey Zigachev }
2140*b843c749SSergey Zigachev return mst;
2141*b843c749SSergey Zigachev
2142*b843c749SSergey Zigachev }
2143*b843c749SSergey Zigachev
is_dp_active_dongle(const struct dc_link * link)2144*b843c749SSergey Zigachev bool is_dp_active_dongle(const struct dc_link *link)
2145*b843c749SSergey Zigachev {
2146*b843c749SSergey Zigachev enum display_dongle_type dongle_type = link->dpcd_caps.dongle_type;
2147*b843c749SSergey Zigachev
2148*b843c749SSergey Zigachev return (dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) ||
2149*b843c749SSergey Zigachev (dongle_type == DISPLAY_DONGLE_DP_DVI_CONVERTER) ||
2150*b843c749SSergey Zigachev (dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER);
2151*b843c749SSergey Zigachev }
2152*b843c749SSergey Zigachev
translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)2153*b843c749SSergey Zigachev static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
2154*b843c749SSergey Zigachev {
2155*b843c749SSergey Zigachev switch (bpc) {
2156*b843c749SSergey Zigachev case DOWN_STREAM_MAX_8BPC:
2157*b843c749SSergey Zigachev return 8;
2158*b843c749SSergey Zigachev case DOWN_STREAM_MAX_10BPC:
2159*b843c749SSergey Zigachev return 10;
2160*b843c749SSergey Zigachev case DOWN_STREAM_MAX_12BPC:
2161*b843c749SSergey Zigachev return 12;
2162*b843c749SSergey Zigachev case DOWN_STREAM_MAX_16BPC:
2163*b843c749SSergey Zigachev return 16;
2164*b843c749SSergey Zigachev default:
2165*b843c749SSergey Zigachev break;
2166*b843c749SSergey Zigachev }
2167*b843c749SSergey Zigachev
2168*b843c749SSergey Zigachev return -1;
2169*b843c749SSergey Zigachev }
2170*b843c749SSergey Zigachev
get_active_converter_info(uint8_t data,struct dc_link * link)2171*b843c749SSergey Zigachev static void get_active_converter_info(
2172*b843c749SSergey Zigachev uint8_t data, struct dc_link *link)
2173*b843c749SSergey Zigachev {
2174*b843c749SSergey Zigachev union dp_downstream_port_present ds_port = { .byte = data };
2175*b843c749SSergey Zigachev memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
2176*b843c749SSergey Zigachev
2177*b843c749SSergey Zigachev /* decode converter info*/
2178*b843c749SSergey Zigachev if (!ds_port.fields.PORT_PRESENT) {
2179*b843c749SSergey Zigachev link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
2180*b843c749SSergey Zigachev ddc_service_set_dongle_type(link->ddc,
2181*b843c749SSergey Zigachev link->dpcd_caps.dongle_type);
2182*b843c749SSergey Zigachev return;
2183*b843c749SSergey Zigachev }
2184*b843c749SSergey Zigachev
2185*b843c749SSergey Zigachev switch (ds_port.fields.PORT_TYPE) {
2186*b843c749SSergey Zigachev case DOWNSTREAM_VGA:
2187*b843c749SSergey Zigachev link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
2188*b843c749SSergey Zigachev break;
2189*b843c749SSergey Zigachev case DOWNSTREAM_DVI_HDMI:
2190*b843c749SSergey Zigachev /* At this point we don't know is it DVI or HDMI,
2191*b843c749SSergey Zigachev * assume DVI.*/
2192*b843c749SSergey Zigachev link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
2193*b843c749SSergey Zigachev break;
2194*b843c749SSergey Zigachev default:
2195*b843c749SSergey Zigachev link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
2196*b843c749SSergey Zigachev break;
2197*b843c749SSergey Zigachev }
2198*b843c749SSergey Zigachev
2199*b843c749SSergey Zigachev if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
2200*b843c749SSergey Zigachev uint8_t det_caps[4];
2201*b843c749SSergey Zigachev union dwnstream_port_caps_byte0 *port_caps =
2202*b843c749SSergey Zigachev (union dwnstream_port_caps_byte0 *)det_caps;
2203*b843c749SSergey Zigachev core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
2204*b843c749SSergey Zigachev det_caps, sizeof(det_caps));
2205*b843c749SSergey Zigachev
2206*b843c749SSergey Zigachev switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
2207*b843c749SSergey Zigachev case DOWN_STREAM_DETAILED_VGA:
2208*b843c749SSergey Zigachev link->dpcd_caps.dongle_type =
2209*b843c749SSergey Zigachev DISPLAY_DONGLE_DP_VGA_CONVERTER;
2210*b843c749SSergey Zigachev break;
2211*b843c749SSergey Zigachev case DOWN_STREAM_DETAILED_DVI:
2212*b843c749SSergey Zigachev link->dpcd_caps.dongle_type =
2213*b843c749SSergey Zigachev DISPLAY_DONGLE_DP_DVI_CONVERTER;
2214*b843c749SSergey Zigachev break;
2215*b843c749SSergey Zigachev case DOWN_STREAM_DETAILED_HDMI:
2216*b843c749SSergey Zigachev link->dpcd_caps.dongle_type =
2217*b843c749SSergey Zigachev DISPLAY_DONGLE_DP_HDMI_CONVERTER;
2218*b843c749SSergey Zigachev
2219*b843c749SSergey Zigachev link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
2220*b843c749SSergey Zigachev if (ds_port.fields.DETAILED_CAPS) {
2221*b843c749SSergey Zigachev
2222*b843c749SSergey Zigachev union dwnstream_port_caps_byte3_hdmi
2223*b843c749SSergey Zigachev hdmi_caps = {.raw = det_caps[3] };
2224*b843c749SSergey Zigachev union dwnstream_port_caps_byte2
2225*b843c749SSergey Zigachev hdmi_color_caps = {.raw = det_caps[2] };
2226*b843c749SSergey Zigachev link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk =
2227*b843c749SSergey Zigachev det_caps[1] * 25000;
2228*b843c749SSergey Zigachev
2229*b843c749SSergey Zigachev link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
2230*b843c749SSergey Zigachev hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
2231*b843c749SSergey Zigachev link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
2232*b843c749SSergey Zigachev hdmi_caps.bits.YCrCr422_PASS_THROUGH;
2233*b843c749SSergey Zigachev link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
2234*b843c749SSergey Zigachev hdmi_caps.bits.YCrCr420_PASS_THROUGH;
2235*b843c749SSergey Zigachev link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
2236*b843c749SSergey Zigachev hdmi_caps.bits.YCrCr422_CONVERSION;
2237*b843c749SSergey Zigachev link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
2238*b843c749SSergey Zigachev hdmi_caps.bits.YCrCr420_CONVERSION;
2239*b843c749SSergey Zigachev
2240*b843c749SSergey Zigachev link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
2241*b843c749SSergey Zigachev translate_dpcd_max_bpc(
2242*b843c749SSergey Zigachev hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
2243*b843c749SSergey Zigachev
2244*b843c749SSergey Zigachev if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk != 0)
2245*b843c749SSergey Zigachev link->dpcd_caps.dongle_caps.extendedCapValid = true;
2246*b843c749SSergey Zigachev }
2247*b843c749SSergey Zigachev
2248*b843c749SSergey Zigachev break;
2249*b843c749SSergey Zigachev }
2250*b843c749SSergey Zigachev }
2251*b843c749SSergey Zigachev
2252*b843c749SSergey Zigachev ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
2253*b843c749SSergey Zigachev
2254*b843c749SSergey Zigachev {
2255*b843c749SSergey Zigachev struct dp_device_vendor_id dp_id;
2256*b843c749SSergey Zigachev
2257*b843c749SSergey Zigachev /* read IEEE branch device id */
2258*b843c749SSergey Zigachev core_link_read_dpcd(
2259*b843c749SSergey Zigachev link,
2260*b843c749SSergey Zigachev DP_BRANCH_OUI,
2261*b843c749SSergey Zigachev (uint8_t *)&dp_id,
2262*b843c749SSergey Zigachev sizeof(dp_id));
2263*b843c749SSergey Zigachev
2264*b843c749SSergey Zigachev link->dpcd_caps.branch_dev_id =
2265*b843c749SSergey Zigachev (dp_id.ieee_oui[0] << 16) +
2266*b843c749SSergey Zigachev (dp_id.ieee_oui[1] << 8) +
2267*b843c749SSergey Zigachev dp_id.ieee_oui[2];
2268*b843c749SSergey Zigachev
2269*b843c749SSergey Zigachev memmove(
2270*b843c749SSergey Zigachev link->dpcd_caps.branch_dev_name,
2271*b843c749SSergey Zigachev dp_id.ieee_device_id,
2272*b843c749SSergey Zigachev sizeof(dp_id.ieee_device_id));
2273*b843c749SSergey Zigachev }
2274*b843c749SSergey Zigachev
2275*b843c749SSergey Zigachev {
2276*b843c749SSergey Zigachev struct dp_sink_hw_fw_revision dp_hw_fw_revision;
2277*b843c749SSergey Zigachev
2278*b843c749SSergey Zigachev core_link_read_dpcd(
2279*b843c749SSergey Zigachev link,
2280*b843c749SSergey Zigachev DP_BRANCH_REVISION_START,
2281*b843c749SSergey Zigachev (uint8_t *)&dp_hw_fw_revision,
2282*b843c749SSergey Zigachev sizeof(dp_hw_fw_revision));
2283*b843c749SSergey Zigachev
2284*b843c749SSergey Zigachev link->dpcd_caps.branch_hw_revision =
2285*b843c749SSergey Zigachev dp_hw_fw_revision.ieee_hw_rev;
2286*b843c749SSergey Zigachev
2287*b843c749SSergey Zigachev memmove(
2288*b843c749SSergey Zigachev link->dpcd_caps.branch_fw_revision,
2289*b843c749SSergey Zigachev dp_hw_fw_revision.ieee_fw_rev,
2290*b843c749SSergey Zigachev sizeof(dp_hw_fw_revision.ieee_fw_rev));
2291*b843c749SSergey Zigachev }
2292*b843c749SSergey Zigachev }
2293*b843c749SSergey Zigachev
dp_wa_power_up_0010FA(struct dc_link * link,uint8_t * dpcd_data,int length)2294*b843c749SSergey Zigachev static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
2295*b843c749SSergey Zigachev int length)
2296*b843c749SSergey Zigachev {
2297*b843c749SSergey Zigachev int retry = 0;
2298*b843c749SSergey Zigachev union dp_downstream_port_present ds_port = { 0 };
2299*b843c749SSergey Zigachev
2300*b843c749SSergey Zigachev if (!link->dpcd_caps.dpcd_rev.raw) {
2301*b843c749SSergey Zigachev do {
2302*b843c749SSergey Zigachev dp_receiver_power_ctrl(link, true);
2303*b843c749SSergey Zigachev core_link_read_dpcd(link, DP_DPCD_REV,
2304*b843c749SSergey Zigachev dpcd_data, length);
2305*b843c749SSergey Zigachev link->dpcd_caps.dpcd_rev.raw = dpcd_data[
2306*b843c749SSergey Zigachev DP_DPCD_REV -
2307*b843c749SSergey Zigachev DP_DPCD_REV];
2308*b843c749SSergey Zigachev } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
2309*b843c749SSergey Zigachev }
2310*b843c749SSergey Zigachev
2311*b843c749SSergey Zigachev ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
2312*b843c749SSergey Zigachev DP_DPCD_REV];
2313*b843c749SSergey Zigachev
2314*b843c749SSergey Zigachev if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
2315*b843c749SSergey Zigachev switch (link->dpcd_caps.branch_dev_id) {
2316*b843c749SSergey Zigachev /* Some active dongles (DP-VGA, DP-DLDVI converters) power down
2317*b843c749SSergey Zigachev * all internal circuits including AUX communication preventing
2318*b843c749SSergey Zigachev * reading DPCD table and EDID (spec violation).
2319*b843c749SSergey Zigachev * Encoder will skip DP RX power down on disable_output to
2320*b843c749SSergey Zigachev * keep receiver powered all the time.*/
2321*b843c749SSergey Zigachev case DP_BRANCH_DEVICE_ID_1:
2322*b843c749SSergey Zigachev case DP_BRANCH_DEVICE_ID_4:
2323*b843c749SSergey Zigachev link->wa_flags.dp_keep_receiver_powered = true;
2324*b843c749SSergey Zigachev break;
2325*b843c749SSergey Zigachev
2326*b843c749SSergey Zigachev /* TODO: May need work around for other dongles. */
2327*b843c749SSergey Zigachev default:
2328*b843c749SSergey Zigachev link->wa_flags.dp_keep_receiver_powered = false;
2329*b843c749SSergey Zigachev break;
2330*b843c749SSergey Zigachev }
2331*b843c749SSergey Zigachev } else
2332*b843c749SSergey Zigachev link->wa_flags.dp_keep_receiver_powered = false;
2333*b843c749SSergey Zigachev }
2334*b843c749SSergey Zigachev
retrieve_link_cap(struct dc_link * link)2335*b843c749SSergey Zigachev static bool retrieve_link_cap(struct dc_link *link)
2336*b843c749SSergey Zigachev {
2337*b843c749SSergey Zigachev uint8_t dpcd_data[DP_ADAPTER_CAP - DP_DPCD_REV + 1];
2338*b843c749SSergey Zigachev
2339*b843c749SSergey Zigachev struct dp_device_vendor_id sink_id;
2340*b843c749SSergey Zigachev union down_stream_port_count down_strm_port_count;
2341*b843c749SSergey Zigachev union edp_configuration_cap edp_config_cap;
2342*b843c749SSergey Zigachev union dp_downstream_port_present ds_port = { 0 };
2343*b843c749SSergey Zigachev enum dc_status status = DC_ERROR_UNEXPECTED;
2344*b843c749SSergey Zigachev uint32_t read_dpcd_retry_cnt = 3;
2345*b843c749SSergey Zigachev int i;
2346*b843c749SSergey Zigachev struct dp_sink_hw_fw_revision dp_hw_fw_revision;
2347*b843c749SSergey Zigachev
2348*b843c749SSergey Zigachev memset(dpcd_data, '\0', sizeof(dpcd_data));
2349*b843c749SSergey Zigachev memset(&down_strm_port_count,
2350*b843c749SSergey Zigachev '\0', sizeof(union down_stream_port_count));
2351*b843c749SSergey Zigachev memset(&edp_config_cap, '\0',
2352*b843c749SSergey Zigachev sizeof(union edp_configuration_cap));
2353*b843c749SSergey Zigachev
2354*b843c749SSergey Zigachev for (i = 0; i < read_dpcd_retry_cnt; i++) {
2355*b843c749SSergey Zigachev status = core_link_read_dpcd(
2356*b843c749SSergey Zigachev link,
2357*b843c749SSergey Zigachev DP_DPCD_REV,
2358*b843c749SSergey Zigachev dpcd_data,
2359*b843c749SSergey Zigachev sizeof(dpcd_data));
2360*b843c749SSergey Zigachev if (status == DC_OK)
2361*b843c749SSergey Zigachev break;
2362*b843c749SSergey Zigachev }
2363*b843c749SSergey Zigachev
2364*b843c749SSergey Zigachev if (status != DC_OK) {
2365*b843c749SSergey Zigachev dm_error("%s: Read dpcd data failed.\n", __func__);
2366*b843c749SSergey Zigachev return false;
2367*b843c749SSergey Zigachev }
2368*b843c749SSergey Zigachev
2369*b843c749SSergey Zigachev {
2370*b843c749SSergey Zigachev union training_aux_rd_interval aux_rd_interval;
2371*b843c749SSergey Zigachev
2372*b843c749SSergey Zigachev aux_rd_interval.raw =
2373*b843c749SSergey Zigachev dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
2374*b843c749SSergey Zigachev
2375*b843c749SSergey Zigachev if (aux_rd_interval.bits.EXT_RECIEVER_CAP_FIELD_PRESENT == 1) {
2376*b843c749SSergey Zigachev core_link_read_dpcd(
2377*b843c749SSergey Zigachev link,
2378*b843c749SSergey Zigachev DP_DP13_DPCD_REV,
2379*b843c749SSergey Zigachev dpcd_data,
2380*b843c749SSergey Zigachev sizeof(dpcd_data));
2381*b843c749SSergey Zigachev }
2382*b843c749SSergey Zigachev }
2383*b843c749SSergey Zigachev
2384*b843c749SSergey Zigachev link->dpcd_caps.dpcd_rev.raw =
2385*b843c749SSergey Zigachev dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
2386*b843c749SSergey Zigachev
2387*b843c749SSergey Zigachev ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
2388*b843c749SSergey Zigachev DP_DPCD_REV];
2389*b843c749SSergey Zigachev
2390*b843c749SSergey Zigachev get_active_converter_info(ds_port.byte, link);
2391*b843c749SSergey Zigachev
2392*b843c749SSergey Zigachev dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
2393*b843c749SSergey Zigachev
2394*b843c749SSergey Zigachev link->dpcd_caps.allow_invalid_MSA_timing_param =
2395*b843c749SSergey Zigachev down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
2396*b843c749SSergey Zigachev
2397*b843c749SSergey Zigachev link->dpcd_caps.max_ln_count.raw = dpcd_data[
2398*b843c749SSergey Zigachev DP_MAX_LANE_COUNT - DP_DPCD_REV];
2399*b843c749SSergey Zigachev
2400*b843c749SSergey Zigachev link->dpcd_caps.max_down_spread.raw = dpcd_data[
2401*b843c749SSergey Zigachev DP_MAX_DOWNSPREAD - DP_DPCD_REV];
2402*b843c749SSergey Zigachev
2403*b843c749SSergey Zigachev link->reported_link_cap.lane_count =
2404*b843c749SSergey Zigachev link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
2405*b843c749SSergey Zigachev link->reported_link_cap.link_rate = dpcd_data[
2406*b843c749SSergey Zigachev DP_MAX_LINK_RATE - DP_DPCD_REV];
2407*b843c749SSergey Zigachev link->reported_link_cap.link_spread =
2408*b843c749SSergey Zigachev link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
2409*b843c749SSergey Zigachev LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
2410*b843c749SSergey Zigachev
2411*b843c749SSergey Zigachev edp_config_cap.raw = dpcd_data[
2412*b843c749SSergey Zigachev DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
2413*b843c749SSergey Zigachev link->dpcd_caps.panel_mode_edp =
2414*b843c749SSergey Zigachev edp_config_cap.bits.ALT_SCRAMBLER_RESET;
2415*b843c749SSergey Zigachev link->dpcd_caps.dpcd_display_control_capable =
2416*b843c749SSergey Zigachev edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
2417*b843c749SSergey Zigachev
2418*b843c749SSergey Zigachev link->test_pattern_enabled = false;
2419*b843c749SSergey Zigachev link->compliance_test_state.raw = 0;
2420*b843c749SSergey Zigachev
2421*b843c749SSergey Zigachev /* read sink count */
2422*b843c749SSergey Zigachev core_link_read_dpcd(link,
2423*b843c749SSergey Zigachev DP_SINK_COUNT,
2424*b843c749SSergey Zigachev &link->dpcd_caps.sink_count.raw,
2425*b843c749SSergey Zigachev sizeof(link->dpcd_caps.sink_count.raw));
2426*b843c749SSergey Zigachev
2427*b843c749SSergey Zigachev /* read sink ieee oui */
2428*b843c749SSergey Zigachev core_link_read_dpcd(link,
2429*b843c749SSergey Zigachev DP_SINK_OUI,
2430*b843c749SSergey Zigachev (uint8_t *)(&sink_id),
2431*b843c749SSergey Zigachev sizeof(sink_id));
2432*b843c749SSergey Zigachev
2433*b843c749SSergey Zigachev link->dpcd_caps.sink_dev_id =
2434*b843c749SSergey Zigachev (sink_id.ieee_oui[0] << 16) +
2435*b843c749SSergey Zigachev (sink_id.ieee_oui[1] << 8) +
2436*b843c749SSergey Zigachev (sink_id.ieee_oui[2]);
2437*b843c749SSergey Zigachev
2438*b843c749SSergey Zigachev memmove(
2439*b843c749SSergey Zigachev link->dpcd_caps.sink_dev_id_str,
2440*b843c749SSergey Zigachev sink_id.ieee_device_id,
2441*b843c749SSergey Zigachev sizeof(sink_id.ieee_device_id));
2442*b843c749SSergey Zigachev
2443*b843c749SSergey Zigachev /* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */
2444*b843c749SSergey Zigachev {
2445*b843c749SSergey Zigachev uint8_t str_mbp_2017[] = { 101, 68, 21, 101, 98, 97 };
2446*b843c749SSergey Zigachev
2447*b843c749SSergey Zigachev if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
2448*b843c749SSergey Zigachev !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2017,
2449*b843c749SSergey Zigachev sizeof(str_mbp_2017))) {
2450*b843c749SSergey Zigachev link->reported_link_cap.link_rate = 0x0c;
2451*b843c749SSergey Zigachev }
2452*b843c749SSergey Zigachev }
2453*b843c749SSergey Zigachev
2454*b843c749SSergey Zigachev core_link_read_dpcd(
2455*b843c749SSergey Zigachev link,
2456*b843c749SSergey Zigachev DP_SINK_HW_REVISION_START,
2457*b843c749SSergey Zigachev (uint8_t *)&dp_hw_fw_revision,
2458*b843c749SSergey Zigachev sizeof(dp_hw_fw_revision));
2459*b843c749SSergey Zigachev
2460*b843c749SSergey Zigachev link->dpcd_caps.sink_hw_revision =
2461*b843c749SSergey Zigachev dp_hw_fw_revision.ieee_hw_rev;
2462*b843c749SSergey Zigachev
2463*b843c749SSergey Zigachev memmove(
2464*b843c749SSergey Zigachev link->dpcd_caps.sink_fw_revision,
2465*b843c749SSergey Zigachev dp_hw_fw_revision.ieee_fw_rev,
2466*b843c749SSergey Zigachev sizeof(dp_hw_fw_revision.ieee_fw_rev));
2467*b843c749SSergey Zigachev
2468*b843c749SSergey Zigachev /* Connectivity log: detection */
2469*b843c749SSergey Zigachev CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
2470*b843c749SSergey Zigachev
2471*b843c749SSergey Zigachev return true;
2472*b843c749SSergey Zigachev }
2473*b843c749SSergey Zigachev
detect_dp_sink_caps(struct dc_link * link)2474*b843c749SSergey Zigachev bool detect_dp_sink_caps(struct dc_link *link)
2475*b843c749SSergey Zigachev {
2476*b843c749SSergey Zigachev return retrieve_link_cap(link);
2477*b843c749SSergey Zigachev
2478*b843c749SSergey Zigachev /* dc init_hw has power encoder using default
2479*b843c749SSergey Zigachev * signal for connector. For native DP, no
2480*b843c749SSergey Zigachev * need to power up encoder again. If not native
2481*b843c749SSergey Zigachev * DP, hw_init may need check signal or power up
2482*b843c749SSergey Zigachev * encoder here.
2483*b843c749SSergey Zigachev */
2484*b843c749SSergey Zigachev /* TODO save sink caps in link->sink */
2485*b843c749SSergey Zigachev }
2486*b843c749SSergey Zigachev
detect_edp_sink_caps(struct dc_link * link)2487*b843c749SSergey Zigachev void detect_edp_sink_caps(struct dc_link *link)
2488*b843c749SSergey Zigachev {
2489*b843c749SSergey Zigachev retrieve_link_cap(link);
2490*b843c749SSergey Zigachev
2491*b843c749SSergey Zigachev if (link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)
2492*b843c749SSergey Zigachev link->reported_link_cap.link_rate = LINK_RATE_HIGH2;
2493*b843c749SSergey Zigachev
2494*b843c749SSergey Zigachev link->verified_link_cap = link->reported_link_cap;
2495*b843c749SSergey Zigachev }
2496*b843c749SSergey Zigachev
dc_link_dp_enable_hpd(const struct dc_link * link)2497*b843c749SSergey Zigachev void dc_link_dp_enable_hpd(const struct dc_link *link)
2498*b843c749SSergey Zigachev {
2499*b843c749SSergey Zigachev struct link_encoder *encoder = link->link_enc;
2500*b843c749SSergey Zigachev
2501*b843c749SSergey Zigachev if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
2502*b843c749SSergey Zigachev encoder->funcs->enable_hpd(encoder);
2503*b843c749SSergey Zigachev }
2504*b843c749SSergey Zigachev
dc_link_dp_disable_hpd(const struct dc_link * link)2505*b843c749SSergey Zigachev void dc_link_dp_disable_hpd(const struct dc_link *link)
2506*b843c749SSergey Zigachev {
2507*b843c749SSergey Zigachev struct link_encoder *encoder = link->link_enc;
2508*b843c749SSergey Zigachev
2509*b843c749SSergey Zigachev if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
2510*b843c749SSergey Zigachev encoder->funcs->disable_hpd(encoder);
2511*b843c749SSergey Zigachev }
2512*b843c749SSergey Zigachev
is_dp_phy_pattern(enum dp_test_pattern test_pattern)2513*b843c749SSergey Zigachev static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
2514*b843c749SSergey Zigachev {
2515*b843c749SSergey Zigachev if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
2516*b843c749SSergey Zigachev test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
2517*b843c749SSergey Zigachev test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
2518*b843c749SSergey Zigachev return true;
2519*b843c749SSergey Zigachev else
2520*b843c749SSergey Zigachev return false;
2521*b843c749SSergey Zigachev }
2522*b843c749SSergey Zigachev
set_crtc_test_pattern(struct dc_link * link,struct pipe_ctx * pipe_ctx,enum dp_test_pattern test_pattern)2523*b843c749SSergey Zigachev static void set_crtc_test_pattern(struct dc_link *link,
2524*b843c749SSergey Zigachev struct pipe_ctx *pipe_ctx,
2525*b843c749SSergey Zigachev enum dp_test_pattern test_pattern)
2526*b843c749SSergey Zigachev {
2527*b843c749SSergey Zigachev enum controller_dp_test_pattern controller_test_pattern;
2528*b843c749SSergey Zigachev enum dc_color_depth color_depth = pipe_ctx->
2529*b843c749SSergey Zigachev stream->timing.display_color_depth;
2530*b843c749SSergey Zigachev struct bit_depth_reduction_params params;
2531*b843c749SSergey Zigachev
2532*b843c749SSergey Zigachev memset(¶ms, 0, sizeof(params));
2533*b843c749SSergey Zigachev
2534*b843c749SSergey Zigachev switch (test_pattern) {
2535*b843c749SSergey Zigachev case DP_TEST_PATTERN_COLOR_SQUARES:
2536*b843c749SSergey Zigachev controller_test_pattern =
2537*b843c749SSergey Zigachev CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
2538*b843c749SSergey Zigachev break;
2539*b843c749SSergey Zigachev case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
2540*b843c749SSergey Zigachev controller_test_pattern =
2541*b843c749SSergey Zigachev CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
2542*b843c749SSergey Zigachev break;
2543*b843c749SSergey Zigachev case DP_TEST_PATTERN_VERTICAL_BARS:
2544*b843c749SSergey Zigachev controller_test_pattern =
2545*b843c749SSergey Zigachev CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
2546*b843c749SSergey Zigachev break;
2547*b843c749SSergey Zigachev case DP_TEST_PATTERN_HORIZONTAL_BARS:
2548*b843c749SSergey Zigachev controller_test_pattern =
2549*b843c749SSergey Zigachev CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
2550*b843c749SSergey Zigachev break;
2551*b843c749SSergey Zigachev case DP_TEST_PATTERN_COLOR_RAMP:
2552*b843c749SSergey Zigachev controller_test_pattern =
2553*b843c749SSergey Zigachev CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
2554*b843c749SSergey Zigachev break;
2555*b843c749SSergey Zigachev default:
2556*b843c749SSergey Zigachev controller_test_pattern =
2557*b843c749SSergey Zigachev CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
2558*b843c749SSergey Zigachev break;
2559*b843c749SSergey Zigachev }
2560*b843c749SSergey Zigachev
2561*b843c749SSergey Zigachev switch (test_pattern) {
2562*b843c749SSergey Zigachev case DP_TEST_PATTERN_COLOR_SQUARES:
2563*b843c749SSergey Zigachev case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
2564*b843c749SSergey Zigachev case DP_TEST_PATTERN_VERTICAL_BARS:
2565*b843c749SSergey Zigachev case DP_TEST_PATTERN_HORIZONTAL_BARS:
2566*b843c749SSergey Zigachev case DP_TEST_PATTERN_COLOR_RAMP:
2567*b843c749SSergey Zigachev {
2568*b843c749SSergey Zigachev /* disable bit depth reduction */
2569*b843c749SSergey Zigachev pipe_ctx->stream->bit_depth_params = params;
2570*b843c749SSergey Zigachev pipe_ctx->stream_res.opp->funcs->
2571*b843c749SSergey Zigachev opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, ¶ms);
2572*b843c749SSergey Zigachev if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
2573*b843c749SSergey Zigachev pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
2574*b843c749SSergey Zigachev controller_test_pattern, color_depth);
2575*b843c749SSergey Zigachev }
2576*b843c749SSergey Zigachev break;
2577*b843c749SSergey Zigachev case DP_TEST_PATTERN_VIDEO_MODE:
2578*b843c749SSergey Zigachev {
2579*b843c749SSergey Zigachev /* restore bitdepth reduction */
2580*b843c749SSergey Zigachev resource_build_bit_depth_reduction_params(pipe_ctx->stream,
2581*b843c749SSergey Zigachev ¶ms);
2582*b843c749SSergey Zigachev pipe_ctx->stream->bit_depth_params = params;
2583*b843c749SSergey Zigachev pipe_ctx->stream_res.opp->funcs->
2584*b843c749SSergey Zigachev opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, ¶ms);
2585*b843c749SSergey Zigachev if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
2586*b843c749SSergey Zigachev pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
2587*b843c749SSergey Zigachev CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2588*b843c749SSergey Zigachev color_depth);
2589*b843c749SSergey Zigachev }
2590*b843c749SSergey Zigachev break;
2591*b843c749SSergey Zigachev
2592*b843c749SSergey Zigachev default:
2593*b843c749SSergey Zigachev break;
2594*b843c749SSergey Zigachev }
2595*b843c749SSergey Zigachev }
2596*b843c749SSergey Zigachev
dc_link_dp_set_test_pattern(struct dc_link * link,enum dp_test_pattern test_pattern,const struct link_training_settings * p_link_settings,const unsigned char * p_custom_pattern,unsigned int cust_pattern_size)2597*b843c749SSergey Zigachev bool dc_link_dp_set_test_pattern(
2598*b843c749SSergey Zigachev struct dc_link *link,
2599*b843c749SSergey Zigachev enum dp_test_pattern test_pattern,
2600*b843c749SSergey Zigachev const struct link_training_settings *p_link_settings,
2601*b843c749SSergey Zigachev const unsigned char *p_custom_pattern,
2602*b843c749SSergey Zigachev unsigned int cust_pattern_size)
2603*b843c749SSergey Zigachev {
2604*b843c749SSergey Zigachev struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2605*b843c749SSergey Zigachev struct pipe_ctx *pipe_ctx = &pipes[0];
2606*b843c749SSergey Zigachev unsigned int lane;
2607*b843c749SSergey Zigachev unsigned int i;
2608*b843c749SSergey Zigachev unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
2609*b843c749SSergey Zigachev union dpcd_training_pattern training_pattern;
2610*b843c749SSergey Zigachev enum dpcd_phy_test_patterns pattern;
2611*b843c749SSergey Zigachev
2612*b843c749SSergey Zigachev memset(&training_pattern, 0, sizeof(training_pattern));
2613*b843c749SSergey Zigachev
2614*b843c749SSergey Zigachev for (i = 0; i < MAX_PIPES; i++) {
2615*b843c749SSergey Zigachev if (pipes[i].stream->sink->link == link) {
2616*b843c749SSergey Zigachev pipe_ctx = &pipes[i];
2617*b843c749SSergey Zigachev break;
2618*b843c749SSergey Zigachev }
2619*b843c749SSergey Zigachev }
2620*b843c749SSergey Zigachev
2621*b843c749SSergey Zigachev /* Reset CRTC Test Pattern if it is currently running and request
2622*b843c749SSergey Zigachev * is VideoMode Reset DP Phy Test Pattern if it is currently running
2623*b843c749SSergey Zigachev * and request is VideoMode
2624*b843c749SSergey Zigachev */
2625*b843c749SSergey Zigachev if (link->test_pattern_enabled && test_pattern ==
2626*b843c749SSergey Zigachev DP_TEST_PATTERN_VIDEO_MODE) {
2627*b843c749SSergey Zigachev /* Set CRTC Test Pattern */
2628*b843c749SSergey Zigachev set_crtc_test_pattern(link, pipe_ctx, test_pattern);
2629*b843c749SSergey Zigachev dp_set_hw_test_pattern(link, test_pattern,
2630*b843c749SSergey Zigachev (uint8_t *)p_custom_pattern,
2631*b843c749SSergey Zigachev (uint32_t)cust_pattern_size);
2632*b843c749SSergey Zigachev
2633*b843c749SSergey Zigachev /* Unblank Stream */
2634*b843c749SSergey Zigachev link->dc->hwss.unblank_stream(
2635*b843c749SSergey Zigachev pipe_ctx,
2636*b843c749SSergey Zigachev &link->verified_link_cap);
2637*b843c749SSergey Zigachev /* TODO:m_pHwss->MuteAudioEndpoint
2638*b843c749SSergey Zigachev * (pPathMode->pDisplayPath, false);
2639*b843c749SSergey Zigachev */
2640*b843c749SSergey Zigachev
2641*b843c749SSergey Zigachev /* Reset Test Pattern state */
2642*b843c749SSergey Zigachev link->test_pattern_enabled = false;
2643*b843c749SSergey Zigachev
2644*b843c749SSergey Zigachev return true;
2645*b843c749SSergey Zigachev }
2646*b843c749SSergey Zigachev
2647*b843c749SSergey Zigachev /* Check for PHY Test Patterns */
2648*b843c749SSergey Zigachev if (is_dp_phy_pattern(test_pattern)) {
2649*b843c749SSergey Zigachev /* Set DPCD Lane Settings before running test pattern */
2650*b843c749SSergey Zigachev if (p_link_settings != NULL) {
2651*b843c749SSergey Zigachev dp_set_hw_lane_settings(link, p_link_settings);
2652*b843c749SSergey Zigachev dpcd_set_lane_settings(link, p_link_settings);
2653*b843c749SSergey Zigachev }
2654*b843c749SSergey Zigachev
2655*b843c749SSergey Zigachev /* Blank stream if running test pattern */
2656*b843c749SSergey Zigachev if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
2657*b843c749SSergey Zigachev /*TODO:
2658*b843c749SSergey Zigachev * m_pHwss->
2659*b843c749SSergey Zigachev * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
2660*b843c749SSergey Zigachev */
2661*b843c749SSergey Zigachev /* Blank stream */
2662*b843c749SSergey Zigachev pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
2663*b843c749SSergey Zigachev }
2664*b843c749SSergey Zigachev
2665*b843c749SSergey Zigachev dp_set_hw_test_pattern(link, test_pattern,
2666*b843c749SSergey Zigachev (uint8_t *)p_custom_pattern,
2667*b843c749SSergey Zigachev (uint32_t)cust_pattern_size);
2668*b843c749SSergey Zigachev
2669*b843c749SSergey Zigachev if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
2670*b843c749SSergey Zigachev /* Set Test Pattern state */
2671*b843c749SSergey Zigachev link->test_pattern_enabled = true;
2672*b843c749SSergey Zigachev if (p_link_settings != NULL)
2673*b843c749SSergey Zigachev dpcd_set_link_settings(link,
2674*b843c749SSergey Zigachev p_link_settings);
2675*b843c749SSergey Zigachev }
2676*b843c749SSergey Zigachev
2677*b843c749SSergey Zigachev switch (test_pattern) {
2678*b843c749SSergey Zigachev case DP_TEST_PATTERN_VIDEO_MODE:
2679*b843c749SSergey Zigachev pattern = PHY_TEST_PATTERN_NONE;
2680*b843c749SSergey Zigachev break;
2681*b843c749SSergey Zigachev case DP_TEST_PATTERN_D102:
2682*b843c749SSergey Zigachev pattern = PHY_TEST_PATTERN_D10_2;
2683*b843c749SSergey Zigachev break;
2684*b843c749SSergey Zigachev case DP_TEST_PATTERN_SYMBOL_ERROR:
2685*b843c749SSergey Zigachev pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
2686*b843c749SSergey Zigachev break;
2687*b843c749SSergey Zigachev case DP_TEST_PATTERN_PRBS7:
2688*b843c749SSergey Zigachev pattern = PHY_TEST_PATTERN_PRBS7;
2689*b843c749SSergey Zigachev break;
2690*b843c749SSergey Zigachev case DP_TEST_PATTERN_80BIT_CUSTOM:
2691*b843c749SSergey Zigachev pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
2692*b843c749SSergey Zigachev break;
2693*b843c749SSergey Zigachev case DP_TEST_PATTERN_CP2520_1:
2694*b843c749SSergey Zigachev pattern = PHY_TEST_PATTERN_CP2520_1;
2695*b843c749SSergey Zigachev break;
2696*b843c749SSergey Zigachev case DP_TEST_PATTERN_CP2520_2:
2697*b843c749SSergey Zigachev pattern = PHY_TEST_PATTERN_CP2520_2;
2698*b843c749SSergey Zigachev break;
2699*b843c749SSergey Zigachev case DP_TEST_PATTERN_CP2520_3:
2700*b843c749SSergey Zigachev pattern = PHY_TEST_PATTERN_CP2520_3;
2701*b843c749SSergey Zigachev break;
2702*b843c749SSergey Zigachev default:
2703*b843c749SSergey Zigachev return false;
2704*b843c749SSergey Zigachev }
2705*b843c749SSergey Zigachev
2706*b843c749SSergey Zigachev if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
2707*b843c749SSergey Zigachev /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
2708*b843c749SSergey Zigachev return false;
2709*b843c749SSergey Zigachev
2710*b843c749SSergey Zigachev if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
2711*b843c749SSergey Zigachev /* tell receiver that we are sending qualification
2712*b843c749SSergey Zigachev * pattern DP 1.2 or later - DP receiver's link quality
2713*b843c749SSergey Zigachev * pattern is set using DPCD LINK_QUAL_LANEx_SET
2714*b843c749SSergey Zigachev * register (0x10B~0x10E)\
2715*b843c749SSergey Zigachev */
2716*b843c749SSergey Zigachev for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
2717*b843c749SSergey Zigachev link_qual_pattern[lane] =
2718*b843c749SSergey Zigachev (unsigned char)(pattern);
2719*b843c749SSergey Zigachev
2720*b843c749SSergey Zigachev core_link_write_dpcd(link,
2721*b843c749SSergey Zigachev DP_LINK_QUAL_LANE0_SET,
2722*b843c749SSergey Zigachev link_qual_pattern,
2723*b843c749SSergey Zigachev sizeof(link_qual_pattern));
2724*b843c749SSergey Zigachev } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
2725*b843c749SSergey Zigachev link->dpcd_caps.dpcd_rev.raw == 0) {
2726*b843c749SSergey Zigachev /* tell receiver that we are sending qualification
2727*b843c749SSergey Zigachev * pattern DP 1.1a or earlier - DP receiver's link
2728*b843c749SSergey Zigachev * quality pattern is set using
2729*b843c749SSergey Zigachev * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
2730*b843c749SSergey Zigachev * register (0x102). We will use v_1.3 when we are
2731*b843c749SSergey Zigachev * setting test pattern for DP 1.1.
2732*b843c749SSergey Zigachev */
2733*b843c749SSergey Zigachev core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
2734*b843c749SSergey Zigachev &training_pattern.raw,
2735*b843c749SSergey Zigachev sizeof(training_pattern));
2736*b843c749SSergey Zigachev training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
2737*b843c749SSergey Zigachev core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
2738*b843c749SSergey Zigachev &training_pattern.raw,
2739*b843c749SSergey Zigachev sizeof(training_pattern));
2740*b843c749SSergey Zigachev }
2741*b843c749SSergey Zigachev } else {
2742*b843c749SSergey Zigachev /* CRTC Patterns */
2743*b843c749SSergey Zigachev set_crtc_test_pattern(link, pipe_ctx, test_pattern);
2744*b843c749SSergey Zigachev /* Set Test Pattern state */
2745*b843c749SSergey Zigachev link->test_pattern_enabled = true;
2746*b843c749SSergey Zigachev }
2747*b843c749SSergey Zigachev
2748*b843c749SSergey Zigachev return true;
2749*b843c749SSergey Zigachev }
2750*b843c749SSergey Zigachev
dp_enable_mst_on_sink(struct dc_link * link,bool enable)2751*b843c749SSergey Zigachev void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
2752*b843c749SSergey Zigachev {
2753*b843c749SSergey Zigachev unsigned char mstmCntl;
2754*b843c749SSergey Zigachev
2755*b843c749SSergey Zigachev core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
2756*b843c749SSergey Zigachev if (enable)
2757*b843c749SSergey Zigachev mstmCntl |= DP_MST_EN;
2758*b843c749SSergey Zigachev else
2759*b843c749SSergey Zigachev mstmCntl &= (~DP_MST_EN);
2760*b843c749SSergey Zigachev
2761*b843c749SSergey Zigachev core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
2762*b843c749SSergey Zigachev }
2763