1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "dc.h" 28 #include "core_types.h" 29 #include "resource.h" 30 #include "ipp.h" 31 #include "timing_generator.h" 32 33 #define DC_LOGGER dc->ctx->logger 34 35 /******************************************************************************* 36 * Private functions 37 ******************************************************************************/ 38 void update_stream_signal(struct dc_stream_state *stream) 39 { 40 41 struct dc_sink *dc_sink = stream->sink; 42 43 if (dc_sink->sink_signal == SIGNAL_TYPE_NONE) 44 stream->signal = stream->sink->link->connector_signal; 45 else 46 stream->signal = dc_sink->sink_signal; 47 48 if (dc_is_dvi_signal(stream->signal)) { 49 if (stream->ctx->dc->caps.dual_link_dvi && 50 stream->timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK && 51 stream->sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) 52 stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK; 53 else 54 stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 55 } 56 } 57 58 static void construct(struct dc_stream_state *stream, 59 struct dc_sink *dc_sink_data) 60 { 61 uint32_t i = 0; 62 63 stream->sink = dc_sink_data; 64 stream->ctx = stream->sink->ctx; 65 66 dc_sink_retain(dc_sink_data); 67 68 /* Copy audio modes */ 69 /* TODO - Remove this translation */ 70 for (i = 0; i < (dc_sink_data->edid_caps.audio_mode_count); i++) 71 { 72 stream->audio_info.modes[i].channel_count = dc_sink_data->edid_caps.audio_modes[i].channel_count; 73 stream->audio_info.modes[i].format_code = dc_sink_data->edid_caps.audio_modes[i].format_code; 74 stream->audio_info.modes[i].sample_rates.all = dc_sink_data->edid_caps.audio_modes[i].sample_rate; 75 stream->audio_info.modes[i].sample_size = dc_sink_data->edid_caps.audio_modes[i].sample_size; 76 } 77 stream->audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count; 78 stream->audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency; 79 stream->audio_info.video_latency = dc_sink_data->edid_caps.video_latency; 80 memmove( 81 stream->audio_info.display_name, 82 dc_sink_data->edid_caps.display_name, 83 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 84 stream->audio_info.manufacture_id = dc_sink_data->edid_caps.manufacturer_id; 85 stream->audio_info.product_id = dc_sink_data->edid_caps.product_id; 86 stream->audio_info.flags.all = dc_sink_data->edid_caps.speaker_flags; 87 88 if (dc_sink_data->dc_container_id != NULL) { 89 struct dc_container_id *dc_container_id = dc_sink_data->dc_container_id; 90 91 stream->audio_info.port_id[0] = dc_container_id->portId[0]; 92 stream->audio_info.port_id[1] = dc_container_id->portId[1]; 93 } else { 94 /* TODO - WindowDM has implemented, 95 other DMs need Unhardcode port_id */ 96 stream->audio_info.port_id[0] = 0x5558859e; 97 stream->audio_info.port_id[1] = 0xd989449; 98 } 99 100 /* EDID CAP translation for HDMI 2.0 */ 101 stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; 102 103 stream->status.link = stream->sink->link; 104 105 update_stream_signal(stream); 106 107 stream->out_transfer_func = dc_create_transfer_func(); 108 stream->out_transfer_func->type = TF_TYPE_BYPASS; 109 } 110 111 static void destruct(struct dc_stream_state *stream) 112 { 113 dc_sink_release(stream->sink); 114 if (stream->out_transfer_func != NULL) { 115 dc_transfer_func_release(stream->out_transfer_func); 116 stream->out_transfer_func = NULL; 117 } 118 } 119 120 void dc_stream_retain(struct dc_stream_state *stream) 121 { 122 kref_get(&stream->refcount); 123 } 124 125 static void dc_stream_free(struct kref *kref) 126 { 127 struct dc_stream_state *stream = container_of(kref, struct dc_stream_state, refcount); 128 129 destruct(stream); 130 kfree(stream); 131 } 132 133 void dc_stream_release(struct dc_stream_state *stream) 134 { 135 if (stream != NULL) { 136 kref_put(&stream->refcount, dc_stream_free); 137 } 138 } 139 140 struct dc_stream_state *dc_create_stream_for_sink( 141 struct dc_sink *sink) 142 { 143 struct dc_stream_state *stream; 144 145 if (sink == NULL) 146 return NULL; 147 148 stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL); 149 if (stream == NULL) 150 return NULL; 151 152 construct(stream, sink); 153 154 kref_init(&stream->refcount); 155 156 return stream; 157 } 158 159 struct dc_stream_status *dc_stream_get_status( 160 struct dc_stream_state *stream) 161 { 162 uint8_t i; 163 struct dc *dc = stream->ctx->dc; 164 165 for (i = 0; i < dc->current_state->stream_count; i++) { 166 if (stream == dc->current_state->streams[i]) 167 return &dc->current_state->stream_status[i]; 168 } 169 170 return NULL; 171 } 172 173 /** 174 * Update the cursor attributes and set cursor surface address 175 */ 176 bool dc_stream_set_cursor_attributes( 177 struct dc_stream_state *stream, 178 const struct dc_cursor_attributes *attributes) 179 { 180 int i; 181 struct dc *core_dc; 182 struct resource_context *res_ctx; 183 struct pipe_ctx *pipe_to_program = NULL; 184 185 if (NULL == stream) { 186 dm_error("DC: dc_stream is NULL!\n"); 187 return false; 188 } 189 if (NULL == attributes) { 190 dm_error("DC: attributes is NULL!\n"); 191 return false; 192 } 193 194 if (attributes->address.quad_part == 0) { 195 dm_output_to_console("DC: Cursor address is 0!\n"); 196 return false; 197 } 198 199 core_dc = stream->ctx->dc; 200 res_ctx = &core_dc->current_state->res_ctx; 201 stream->cursor_attributes = *attributes; 202 203 for (i = 0; i < MAX_PIPES; i++) { 204 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 205 206 if (pipe_ctx->stream != stream) 207 continue; 208 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) 209 continue; 210 211 if (!pipe_to_program) { 212 pipe_to_program = pipe_ctx; 213 core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, true); 214 } 215 216 core_dc->hwss.set_cursor_attribute(pipe_ctx); 217 if (core_dc->hwss.set_cursor_sdr_white_level) 218 core_dc->hwss.set_cursor_sdr_white_level(pipe_ctx); 219 } 220 221 if (pipe_to_program) 222 core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, false); 223 224 return true; 225 } 226 227 bool dc_stream_set_cursor_position( 228 struct dc_stream_state *stream, 229 const struct dc_cursor_position *position) 230 { 231 int i; 232 struct dc *core_dc; 233 struct resource_context *res_ctx; 234 struct pipe_ctx *pipe_to_program = NULL; 235 236 if (NULL == stream) { 237 dm_error("DC: dc_stream is NULL!\n"); 238 return false; 239 } 240 241 if (NULL == position) { 242 dm_error("DC: cursor position is NULL!\n"); 243 return false; 244 } 245 246 core_dc = stream->ctx->dc; 247 res_ctx = &core_dc->current_state->res_ctx; 248 stream->cursor_position = *position; 249 250 for (i = 0; i < MAX_PIPES; i++) { 251 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 252 253 if (pipe_ctx->stream != stream || 254 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || 255 !pipe_ctx->plane_state || 256 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) || 257 !pipe_ctx->plane_res.ipp) 258 continue; 259 260 if (!pipe_to_program) { 261 pipe_to_program = pipe_ctx; 262 core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, true); 263 } 264 265 core_dc->hwss.set_cursor_position(pipe_ctx); 266 } 267 268 if (pipe_to_program) 269 core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, false); 270 271 return true; 272 } 273 274 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream) 275 { 276 uint8_t i; 277 struct dc *core_dc = stream->ctx->dc; 278 struct resource_context *res_ctx = 279 &core_dc->current_state->res_ctx; 280 281 for (i = 0; i < MAX_PIPES; i++) { 282 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; 283 284 if (res_ctx->pipe_ctx[i].stream != stream) 285 continue; 286 287 return tg->funcs->get_frame_count(tg); 288 } 289 290 return 0; 291 } 292 293 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, 294 uint32_t *v_blank_start, 295 uint32_t *v_blank_end, 296 uint32_t *h_position, 297 uint32_t *v_position) 298 { 299 uint8_t i; 300 bool ret = false; 301 struct dc *core_dc = stream->ctx->dc; 302 struct resource_context *res_ctx = 303 &core_dc->current_state->res_ctx; 304 305 for (i = 0; i < MAX_PIPES; i++) { 306 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; 307 308 if (res_ctx->pipe_ctx[i].stream != stream) 309 continue; 310 311 tg->funcs->get_scanoutpos(tg, 312 v_blank_start, 313 v_blank_end, 314 h_position, 315 v_position); 316 317 ret = true; 318 break; 319 } 320 321 return ret; 322 } 323 324 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream) 325 { 326 DC_LOG_DC( 327 "core_stream 0x%p: src: %d, %d, %d, %d; dst: %d, %d, %d, %d, colorSpace:%d\n", 328 stream, 329 stream->src.x, 330 stream->src.y, 331 stream->src.width, 332 stream->src.height, 333 stream->dst.x, 334 stream->dst.y, 335 stream->dst.width, 336 stream->dst.height, 337 stream->output_color_space); 338 DC_LOG_DC( 339 "\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n", 340 stream->timing.pix_clk_khz, 341 stream->timing.h_total, 342 stream->timing.v_total, 343 stream->timing.pixel_encoding, 344 stream->timing.display_color_depth); 345 DC_LOG_DC( 346 "\tsink name: %s, serial: %d\n", 347 stream->sink->edid_caps.display_name, 348 stream->sink->edid_caps.serial_number); 349 DC_LOG_DC( 350 "\tlink: %d\n", 351 stream->sink->link->link_index); 352 } 353