1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2016 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev * Authors: AMD 23*b843c749SSergey Zigachev * 24*b843c749SSergey Zigachev */ 25*b843c749SSergey Zigachev 26*b843c749SSergey Zigachev #ifndef DC_DP_TYPES_H 27*b843c749SSergey Zigachev #define DC_DP_TYPES_H 28*b843c749SSergey Zigachev 29*b843c749SSergey Zigachev #include "os_types.h" 30*b843c749SSergey Zigachev 31*b843c749SSergey Zigachev enum dc_lane_count { 32*b843c749SSergey Zigachev LANE_COUNT_UNKNOWN = 0, 33*b843c749SSergey Zigachev LANE_COUNT_ONE = 1, 34*b843c749SSergey Zigachev LANE_COUNT_TWO = 2, 35*b843c749SSergey Zigachev LANE_COUNT_FOUR = 4, 36*b843c749SSergey Zigachev LANE_COUNT_EIGHT = 8, 37*b843c749SSergey Zigachev LANE_COUNT_DP_MAX = LANE_COUNT_FOUR 38*b843c749SSergey Zigachev }; 39*b843c749SSergey Zigachev 40*b843c749SSergey Zigachev /* This is actually a reference clock (27MHz) multiplier 41*b843c749SSergey Zigachev * 162MBps bandwidth for 1.62GHz like rate, 42*b843c749SSergey Zigachev * 270MBps for 2.70GHz, 43*b843c749SSergey Zigachev * 324MBps for 3.24Ghz, 44*b843c749SSergey Zigachev * 540MBps for 5.40GHz 45*b843c749SSergey Zigachev * 810MBps for 8.10GHz 46*b843c749SSergey Zigachev */ 47*b843c749SSergey Zigachev enum dc_link_rate { 48*b843c749SSergey Zigachev LINK_RATE_UNKNOWN = 0, 49*b843c749SSergey Zigachev LINK_RATE_LOW = 0x06, 50*b843c749SSergey Zigachev LINK_RATE_HIGH = 0x0A, 51*b843c749SSergey Zigachev LINK_RATE_RBR2 = 0x0C, 52*b843c749SSergey Zigachev LINK_RATE_HIGH2 = 0x14, 53*b843c749SSergey Zigachev LINK_RATE_HIGH3 = 0x1E 54*b843c749SSergey Zigachev }; 55*b843c749SSergey Zigachev 56*b843c749SSergey Zigachev enum dc_link_spread { 57*b843c749SSergey Zigachev LINK_SPREAD_DISABLED = 0x00, 58*b843c749SSergey Zigachev /* 0.5 % downspread 30 kHz */ 59*b843c749SSergey Zigachev LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10, 60*b843c749SSergey Zigachev /* 0.5 % downspread 33 kHz */ 61*b843c749SSergey Zigachev LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11 62*b843c749SSergey Zigachev }; 63*b843c749SSergey Zigachev 64*b843c749SSergey Zigachev enum dc_voltage_swing { 65*b843c749SSergey Zigachev VOLTAGE_SWING_LEVEL0 = 0, /* direct HW translation! */ 66*b843c749SSergey Zigachev VOLTAGE_SWING_LEVEL1, 67*b843c749SSergey Zigachev VOLTAGE_SWING_LEVEL2, 68*b843c749SSergey Zigachev VOLTAGE_SWING_LEVEL3, 69*b843c749SSergey Zigachev VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3 70*b843c749SSergey Zigachev }; 71*b843c749SSergey Zigachev 72*b843c749SSergey Zigachev enum dc_pre_emphasis { 73*b843c749SSergey Zigachev PRE_EMPHASIS_DISABLED = 0, /* direct HW translation! */ 74*b843c749SSergey Zigachev PRE_EMPHASIS_LEVEL1, 75*b843c749SSergey Zigachev PRE_EMPHASIS_LEVEL2, 76*b843c749SSergey Zigachev PRE_EMPHASIS_LEVEL3, 77*b843c749SSergey Zigachev PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3 78*b843c749SSergey Zigachev }; 79*b843c749SSergey Zigachev /* Post Cursor 2 is optional for transmitter 80*b843c749SSergey Zigachev * and it applies only to the main link operating at HBR2 81*b843c749SSergey Zigachev */ 82*b843c749SSergey Zigachev enum dc_post_cursor2 { 83*b843c749SSergey Zigachev POST_CURSOR2_DISABLED = 0, /* direct HW translation! */ 84*b843c749SSergey Zigachev POST_CURSOR2_LEVEL1, 85*b843c749SSergey Zigachev POST_CURSOR2_LEVEL2, 86*b843c749SSergey Zigachev POST_CURSOR2_LEVEL3, 87*b843c749SSergey Zigachev POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3, 88*b843c749SSergey Zigachev }; 89*b843c749SSergey Zigachev 90*b843c749SSergey Zigachev struct dc_link_settings { 91*b843c749SSergey Zigachev enum dc_lane_count lane_count; 92*b843c749SSergey Zigachev enum dc_link_rate link_rate; 93*b843c749SSergey Zigachev enum dc_link_spread link_spread; 94*b843c749SSergey Zigachev }; 95*b843c749SSergey Zigachev 96*b843c749SSergey Zigachev struct dc_lane_settings { 97*b843c749SSergey Zigachev enum dc_voltage_swing VOLTAGE_SWING; 98*b843c749SSergey Zigachev enum dc_pre_emphasis PRE_EMPHASIS; 99*b843c749SSergey Zigachev enum dc_post_cursor2 POST_CURSOR2; 100*b843c749SSergey Zigachev }; 101*b843c749SSergey Zigachev 102*b843c749SSergey Zigachev struct dc_link_training_settings { 103*b843c749SSergey Zigachev struct dc_link_settings link; 104*b843c749SSergey Zigachev struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]; 105*b843c749SSergey Zigachev }; 106*b843c749SSergey Zigachev 107*b843c749SSergey Zigachev 108*b843c749SSergey Zigachev union dpcd_rev { 109*b843c749SSergey Zigachev struct { 110*b843c749SSergey Zigachev uint8_t MINOR:4; 111*b843c749SSergey Zigachev uint8_t MAJOR:4; 112*b843c749SSergey Zigachev } bits; 113*b843c749SSergey Zigachev uint8_t raw; 114*b843c749SSergey Zigachev }; 115*b843c749SSergey Zigachev 116*b843c749SSergey Zigachev union max_lane_count { 117*b843c749SSergey Zigachev struct { 118*b843c749SSergey Zigachev uint8_t MAX_LANE_COUNT:5; 119*b843c749SSergey Zigachev uint8_t POST_LT_ADJ_REQ_SUPPORTED:1; 120*b843c749SSergey Zigachev uint8_t TPS3_SUPPORTED:1; 121*b843c749SSergey Zigachev uint8_t ENHANCED_FRAME_CAP:1; 122*b843c749SSergey Zigachev } bits; 123*b843c749SSergey Zigachev uint8_t raw; 124*b843c749SSergey Zigachev }; 125*b843c749SSergey Zigachev 126*b843c749SSergey Zigachev union max_down_spread { 127*b843c749SSergey Zigachev struct { 128*b843c749SSergey Zigachev uint8_t MAX_DOWN_SPREAD:1; 129*b843c749SSergey Zigachev uint8_t RESERVED:5; 130*b843c749SSergey Zigachev uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1; 131*b843c749SSergey Zigachev uint8_t TPS4_SUPPORTED:1; 132*b843c749SSergey Zigachev } bits; 133*b843c749SSergey Zigachev uint8_t raw; 134*b843c749SSergey Zigachev }; 135*b843c749SSergey Zigachev 136*b843c749SSergey Zigachev union mstm_cap { 137*b843c749SSergey Zigachev struct { 138*b843c749SSergey Zigachev uint8_t MST_CAP:1; 139*b843c749SSergey Zigachev uint8_t RESERVED:7; 140*b843c749SSergey Zigachev } bits; 141*b843c749SSergey Zigachev uint8_t raw; 142*b843c749SSergey Zigachev }; 143*b843c749SSergey Zigachev 144*b843c749SSergey Zigachev union lane_count_set { 145*b843c749SSergey Zigachev struct { 146*b843c749SSergey Zigachev uint8_t LANE_COUNT_SET:5; 147*b843c749SSergey Zigachev uint8_t POST_LT_ADJ_REQ_GRANTED:1; 148*b843c749SSergey Zigachev uint8_t RESERVED:1; 149*b843c749SSergey Zigachev uint8_t ENHANCED_FRAMING:1; 150*b843c749SSergey Zigachev } bits; 151*b843c749SSergey Zigachev uint8_t raw; 152*b843c749SSergey Zigachev }; 153*b843c749SSergey Zigachev 154*b843c749SSergey Zigachev union lane_status { 155*b843c749SSergey Zigachev struct { 156*b843c749SSergey Zigachev uint8_t CR_DONE_0:1; 157*b843c749SSergey Zigachev uint8_t CHANNEL_EQ_DONE_0:1; 158*b843c749SSergey Zigachev uint8_t SYMBOL_LOCKED_0:1; 159*b843c749SSergey Zigachev uint8_t RESERVED0:1; 160*b843c749SSergey Zigachev uint8_t CR_DONE_1:1; 161*b843c749SSergey Zigachev uint8_t CHANNEL_EQ_DONE_1:1; 162*b843c749SSergey Zigachev uint8_t SYMBOL_LOCKED_1:1; 163*b843c749SSergey Zigachev uint8_t RESERVED_1:1; 164*b843c749SSergey Zigachev } bits; 165*b843c749SSergey Zigachev uint8_t raw; 166*b843c749SSergey Zigachev }; 167*b843c749SSergey Zigachev 168*b843c749SSergey Zigachev union device_service_irq { 169*b843c749SSergey Zigachev struct { 170*b843c749SSergey Zigachev uint8_t REMOTE_CONTROL_CMD_PENDING:1; 171*b843c749SSergey Zigachev uint8_t AUTOMATED_TEST:1; 172*b843c749SSergey Zigachev uint8_t CP_IRQ:1; 173*b843c749SSergey Zigachev uint8_t MCCS_IRQ:1; 174*b843c749SSergey Zigachev uint8_t DOWN_REP_MSG_RDY:1; 175*b843c749SSergey Zigachev uint8_t UP_REQ_MSG_RDY:1; 176*b843c749SSergey Zigachev uint8_t SINK_SPECIFIC:1; 177*b843c749SSergey Zigachev uint8_t reserved:1; 178*b843c749SSergey Zigachev } bits; 179*b843c749SSergey Zigachev uint8_t raw; 180*b843c749SSergey Zigachev }; 181*b843c749SSergey Zigachev 182*b843c749SSergey Zigachev union sink_count { 183*b843c749SSergey Zigachev struct { 184*b843c749SSergey Zigachev uint8_t SINK_COUNT:6; 185*b843c749SSergey Zigachev uint8_t CPREADY:1; 186*b843c749SSergey Zigachev uint8_t RESERVED:1; 187*b843c749SSergey Zigachev } bits; 188*b843c749SSergey Zigachev uint8_t raw; 189*b843c749SSergey Zigachev }; 190*b843c749SSergey Zigachev 191*b843c749SSergey Zigachev union lane_align_status_updated { 192*b843c749SSergey Zigachev struct { 193*b843c749SSergey Zigachev uint8_t INTERLANE_ALIGN_DONE:1; 194*b843c749SSergey Zigachev uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1; 195*b843c749SSergey Zigachev uint8_t RESERVED:4; 196*b843c749SSergey Zigachev uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1; 197*b843c749SSergey Zigachev uint8_t LINK_STATUS_UPDATED:1; 198*b843c749SSergey Zigachev } bits; 199*b843c749SSergey Zigachev uint8_t raw; 200*b843c749SSergey Zigachev }; 201*b843c749SSergey Zigachev 202*b843c749SSergey Zigachev union lane_adjust { 203*b843c749SSergey Zigachev struct { 204*b843c749SSergey Zigachev uint8_t VOLTAGE_SWING_LANE:2; 205*b843c749SSergey Zigachev uint8_t PRE_EMPHASIS_LANE:2; 206*b843c749SSergey Zigachev uint8_t RESERVED:4; 207*b843c749SSergey Zigachev } bits; 208*b843c749SSergey Zigachev uint8_t raw; 209*b843c749SSergey Zigachev }; 210*b843c749SSergey Zigachev 211*b843c749SSergey Zigachev union dpcd_training_pattern { 212*b843c749SSergey Zigachev struct { 213*b843c749SSergey Zigachev uint8_t TRAINING_PATTERN_SET:4; 214*b843c749SSergey Zigachev uint8_t RECOVERED_CLOCK_OUT_EN:1; 215*b843c749SSergey Zigachev uint8_t SCRAMBLING_DISABLE:1; 216*b843c749SSergey Zigachev uint8_t SYMBOL_ERROR_COUNT_SEL:2; 217*b843c749SSergey Zigachev } v1_4; 218*b843c749SSergey Zigachev struct { 219*b843c749SSergey Zigachev uint8_t TRAINING_PATTERN_SET:2; 220*b843c749SSergey Zigachev uint8_t LINK_QUAL_PATTERN_SET:2; 221*b843c749SSergey Zigachev uint8_t RESERVED:4; 222*b843c749SSergey Zigachev } v1_3; 223*b843c749SSergey Zigachev uint8_t raw; 224*b843c749SSergey Zigachev }; 225*b843c749SSergey Zigachev 226*b843c749SSergey Zigachev /* Training Lane is used to configure downstream DP device's voltage swing 227*b843c749SSergey Zigachev and pre-emphasis levels*/ 228*b843c749SSergey Zigachev /* The DPCD addresses are from 0x103 to 0x106*/ 229*b843c749SSergey Zigachev union dpcd_training_lane { 230*b843c749SSergey Zigachev struct { 231*b843c749SSergey Zigachev uint8_t VOLTAGE_SWING_SET:2; 232*b843c749SSergey Zigachev uint8_t MAX_SWING_REACHED:1; 233*b843c749SSergey Zigachev uint8_t PRE_EMPHASIS_SET:2; 234*b843c749SSergey Zigachev uint8_t MAX_PRE_EMPHASIS_REACHED:1; 235*b843c749SSergey Zigachev uint8_t RESERVED:2; 236*b843c749SSergey Zigachev } bits; 237*b843c749SSergey Zigachev uint8_t raw; 238*b843c749SSergey Zigachev }; 239*b843c749SSergey Zigachev 240*b843c749SSergey Zigachev /* TMDS-converter related */ 241*b843c749SSergey Zigachev union dwnstream_port_caps_byte0 { 242*b843c749SSergey Zigachev struct { 243*b843c749SSergey Zigachev uint8_t DWN_STRM_PORTX_TYPE:3; 244*b843c749SSergey Zigachev uint8_t DWN_STRM_PORTX_HPD:1; 245*b843c749SSergey Zigachev uint8_t RESERVERD:4; 246*b843c749SSergey Zigachev } bits; 247*b843c749SSergey Zigachev uint8_t raw; 248*b843c749SSergey Zigachev }; 249*b843c749SSergey Zigachev 250*b843c749SSergey Zigachev /* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/ 251*b843c749SSergey Zigachev enum dpcd_downstream_port_detailed_type { 252*b843c749SSergey Zigachev DOWN_STREAM_DETAILED_DP = 0, 253*b843c749SSergey Zigachev DOWN_STREAM_DETAILED_VGA, 254*b843c749SSergey Zigachev DOWN_STREAM_DETAILED_DVI, 255*b843c749SSergey Zigachev DOWN_STREAM_DETAILED_HDMI, 256*b843c749SSergey Zigachev DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/ 257*b843c749SSergey Zigachev DOWN_STREAM_DETAILED_DP_PLUS_PLUS 258*b843c749SSergey Zigachev }; 259*b843c749SSergey Zigachev 260*b843c749SSergey Zigachev union dwnstream_port_caps_byte2 { 261*b843c749SSergey Zigachev struct { 262*b843c749SSergey Zigachev uint8_t MAX_BITS_PER_COLOR_COMPONENT:2; 263*b843c749SSergey Zigachev uint8_t RESERVED:6; 264*b843c749SSergey Zigachev } bits; 265*b843c749SSergey Zigachev uint8_t raw; 266*b843c749SSergey Zigachev }; 267*b843c749SSergey Zigachev 268*b843c749SSergey Zigachev union dp_downstream_port_present { 269*b843c749SSergey Zigachev uint8_t byte; 270*b843c749SSergey Zigachev struct { 271*b843c749SSergey Zigachev uint8_t PORT_PRESENT:1; 272*b843c749SSergey Zigachev uint8_t PORT_TYPE:2; 273*b843c749SSergey Zigachev uint8_t FMT_CONVERSION:1; 274*b843c749SSergey Zigachev uint8_t DETAILED_CAPS:1; 275*b843c749SSergey Zigachev uint8_t RESERVED:3; 276*b843c749SSergey Zigachev } fields; 277*b843c749SSergey Zigachev }; 278*b843c749SSergey Zigachev 279*b843c749SSergey Zigachev union dwnstream_port_caps_byte3_dvi { 280*b843c749SSergey Zigachev struct { 281*b843c749SSergey Zigachev uint8_t RESERVED1:1; 282*b843c749SSergey Zigachev uint8_t DUAL_LINK:1; 283*b843c749SSergey Zigachev uint8_t HIGH_COLOR_DEPTH:1; 284*b843c749SSergey Zigachev uint8_t RESERVED2:5; 285*b843c749SSergey Zigachev } bits; 286*b843c749SSergey Zigachev uint8_t raw; 287*b843c749SSergey Zigachev }; 288*b843c749SSergey Zigachev 289*b843c749SSergey Zigachev union dwnstream_port_caps_byte3_hdmi { 290*b843c749SSergey Zigachev struct { 291*b843c749SSergey Zigachev uint8_t FRAME_SEQ_TO_FRAME_PACK:1; 292*b843c749SSergey Zigachev uint8_t YCrCr422_PASS_THROUGH:1; 293*b843c749SSergey Zigachev uint8_t YCrCr420_PASS_THROUGH:1; 294*b843c749SSergey Zigachev uint8_t YCrCr422_CONVERSION:1; 295*b843c749SSergey Zigachev uint8_t YCrCr420_CONVERSION:1; 296*b843c749SSergey Zigachev uint8_t RESERVED:3; 297*b843c749SSergey Zigachev } bits; 298*b843c749SSergey Zigachev uint8_t raw; 299*b843c749SSergey Zigachev }; 300*b843c749SSergey Zigachev 301*b843c749SSergey Zigachev /*4-byte structure for detailed capabilities of a down-stream port 302*b843c749SSergey Zigachev (DP-to-TMDS converter).*/ 303*b843c749SSergey Zigachev union dwnstream_portxcaps { 304*b843c749SSergey Zigachev struct { 305*b843c749SSergey Zigachev union dwnstream_port_caps_byte0 byte0; 306*b843c749SSergey Zigachev unsigned char max_TMDS_clock; //byte1 307*b843c749SSergey Zigachev union dwnstream_port_caps_byte2 byte2; 308*b843c749SSergey Zigachev 309*b843c749SSergey Zigachev union { 310*b843c749SSergey Zigachev union dwnstream_port_caps_byte3_dvi byteDVI; 311*b843c749SSergey Zigachev union dwnstream_port_caps_byte3_hdmi byteHDMI; 312*b843c749SSergey Zigachev } byte3; 313*b843c749SSergey Zigachev } bytes; 314*b843c749SSergey Zigachev 315*b843c749SSergey Zigachev unsigned char raw[4]; 316*b843c749SSergey Zigachev }; 317*b843c749SSergey Zigachev 318*b843c749SSergey Zigachev union downstream_port { 319*b843c749SSergey Zigachev struct { 320*b843c749SSergey Zigachev unsigned char present:1; 321*b843c749SSergey Zigachev unsigned char type:2; 322*b843c749SSergey Zigachev unsigned char format_conv:1; 323*b843c749SSergey Zigachev unsigned char detailed_caps:1; 324*b843c749SSergey Zigachev unsigned char reserved:3; 325*b843c749SSergey Zigachev } bits; 326*b843c749SSergey Zigachev unsigned char raw; 327*b843c749SSergey Zigachev }; 328*b843c749SSergey Zigachev 329*b843c749SSergey Zigachev 330*b843c749SSergey Zigachev union sink_status { 331*b843c749SSergey Zigachev struct { 332*b843c749SSergey Zigachev uint8_t RX_PORT0_STATUS:1; 333*b843c749SSergey Zigachev uint8_t RX_PORT1_STATUS:1; 334*b843c749SSergey Zigachev uint8_t RESERVED:6; 335*b843c749SSergey Zigachev } bits; 336*b843c749SSergey Zigachev uint8_t raw; 337*b843c749SSergey Zigachev }; 338*b843c749SSergey Zigachev 339*b843c749SSergey Zigachev /*6-byte structure corresponding to 6 registers (200h-205h) 340*b843c749SSergey Zigachev read during handling of HPD-IRQ*/ 341*b843c749SSergey Zigachev union hpd_irq_data { 342*b843c749SSergey Zigachev struct { 343*b843c749SSergey Zigachev union sink_count sink_cnt;/* 200h */ 344*b843c749SSergey Zigachev union device_service_irq device_service_irq;/* 201h */ 345*b843c749SSergey Zigachev union lane_status lane01_status;/* 202h */ 346*b843c749SSergey Zigachev union lane_status lane23_status;/* 203h */ 347*b843c749SSergey Zigachev union lane_align_status_updated lane_status_updated;/* 204h */ 348*b843c749SSergey Zigachev union sink_status sink_status; 349*b843c749SSergey Zigachev } bytes; 350*b843c749SSergey Zigachev uint8_t raw[6]; 351*b843c749SSergey Zigachev }; 352*b843c749SSergey Zigachev 353*b843c749SSergey Zigachev union down_stream_port_count { 354*b843c749SSergey Zigachev struct { 355*b843c749SSergey Zigachev uint8_t DOWN_STR_PORT_COUNT:4; 356*b843c749SSergey Zigachev uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/ 357*b843c749SSergey Zigachev /*Bit 6 = MSA_TIMING_PAR_IGNORED 358*b843c749SSergey Zigachev 0 = Sink device requires the MSA timing parameters 359*b843c749SSergey Zigachev 1 = Sink device is capable of rendering incoming video 360*b843c749SSergey Zigachev stream without MSA timing parameters*/ 361*b843c749SSergey Zigachev uint8_t IGNORE_MSA_TIMING_PARAM:1; 362*b843c749SSergey Zigachev /*Bit 7 = OUI Support 363*b843c749SSergey Zigachev 0 = OUI not supported 364*b843c749SSergey Zigachev 1 = OUI supported 365*b843c749SSergey Zigachev (OUI and Device Identification mandatory for DP 1.2)*/ 366*b843c749SSergey Zigachev uint8_t OUI_SUPPORT:1; 367*b843c749SSergey Zigachev } bits; 368*b843c749SSergey Zigachev uint8_t raw; 369*b843c749SSergey Zigachev }; 370*b843c749SSergey Zigachev 371*b843c749SSergey Zigachev union down_spread_ctrl { 372*b843c749SSergey Zigachev struct { 373*b843c749SSergey Zigachev uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/ 374*b843c749SSergey Zigachev /* Bits 4 = SPREAD_AMP. Spreading amplitude 375*b843c749SSergey Zigachev 0 = Main link signal is not downspread 376*b843c749SSergey Zigachev 1 = Main link signal is downspread <= 0.5% 377*b843c749SSergey Zigachev with frequency in the range of 30kHz ~ 33kHz*/ 378*b843c749SSergey Zigachev uint8_t SPREAD_AMP:1; 379*b843c749SSergey Zigachev uint8_t RESERVED2:2;/*Bit 6:5 = RESERVED. Read all 0s*/ 380*b843c749SSergey Zigachev /*Bit 7 = MSA_TIMING_PAR_IGNORE_EN 381*b843c749SSergey Zigachev 0 = Source device will send valid data for the MSA Timing Params 382*b843c749SSergey Zigachev 1 = Source device may send invalid data for these MSA Timing Params*/ 383*b843c749SSergey Zigachev uint8_t IGNORE_MSA_TIMING_PARAM:1; 384*b843c749SSergey Zigachev } bits; 385*b843c749SSergey Zigachev uint8_t raw; 386*b843c749SSergey Zigachev }; 387*b843c749SSergey Zigachev 388*b843c749SSergey Zigachev union dpcd_edp_config { 389*b843c749SSergey Zigachev struct { 390*b843c749SSergey Zigachev uint8_t PANEL_MODE_EDP:1; 391*b843c749SSergey Zigachev uint8_t FRAMING_CHANGE_ENABLE:1; 392*b843c749SSergey Zigachev uint8_t RESERVED:5; 393*b843c749SSergey Zigachev uint8_t PANEL_SELF_TEST_ENABLE:1; 394*b843c749SSergey Zigachev } bits; 395*b843c749SSergey Zigachev uint8_t raw; 396*b843c749SSergey Zigachev }; 397*b843c749SSergey Zigachev 398*b843c749SSergey Zigachev struct dp_device_vendor_id { 399*b843c749SSergey Zigachev uint8_t ieee_oui[3];/*24-bit IEEE OUI*/ 400*b843c749SSergey Zigachev uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/ 401*b843c749SSergey Zigachev }; 402*b843c749SSergey Zigachev 403*b843c749SSergey Zigachev struct dp_sink_hw_fw_revision { 404*b843c749SSergey Zigachev uint8_t ieee_hw_rev; 405*b843c749SSergey Zigachev uint8_t ieee_fw_rev[2]; 406*b843c749SSergey Zigachev }; 407*b843c749SSergey Zigachev 408*b843c749SSergey Zigachev /*DPCD register of DP receiver capability field bits-*/ 409*b843c749SSergey Zigachev union edp_configuration_cap { 410*b843c749SSergey Zigachev struct { 411*b843c749SSergey Zigachev uint8_t ALT_SCRAMBLER_RESET:1; 412*b843c749SSergey Zigachev uint8_t FRAMING_CHANGE:1; 413*b843c749SSergey Zigachev uint8_t RESERVED:1; 414*b843c749SSergey Zigachev uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1; 415*b843c749SSergey Zigachev uint8_t RESERVED2:4; 416*b843c749SSergey Zigachev } bits; 417*b843c749SSergey Zigachev uint8_t raw; 418*b843c749SSergey Zigachev }; 419*b843c749SSergey Zigachev 420*b843c749SSergey Zigachev union training_aux_rd_interval { 421*b843c749SSergey Zigachev struct { 422*b843c749SSergey Zigachev uint8_t TRAINIG_AUX_RD_INTERVAL:7; 423*b843c749SSergey Zigachev uint8_t EXT_RECIEVER_CAP_FIELD_PRESENT:1; 424*b843c749SSergey Zigachev } bits; 425*b843c749SSergey Zigachev uint8_t raw; 426*b843c749SSergey Zigachev }; 427*b843c749SSergey Zigachev 428*b843c749SSergey Zigachev /* Automated test structures */ 429*b843c749SSergey Zigachev union test_request { 430*b843c749SSergey Zigachev struct { 431*b843c749SSergey Zigachev uint8_t LINK_TRAINING :1; 432*b843c749SSergey Zigachev uint8_t LINK_TEST_PATTRN :1; 433*b843c749SSergey Zigachev uint8_t EDID_READ :1; 434*b843c749SSergey Zigachev uint8_t PHY_TEST_PATTERN :1; 435*b843c749SSergey Zigachev uint8_t AUDIO_TEST_PATTERN :1; 436*b843c749SSergey Zigachev uint8_t RESERVED :1; 437*b843c749SSergey Zigachev uint8_t TEST_STEREO_3D :1; 438*b843c749SSergey Zigachev } bits; 439*b843c749SSergey Zigachev uint8_t raw; 440*b843c749SSergey Zigachev }; 441*b843c749SSergey Zigachev 442*b843c749SSergey Zigachev union test_response { 443*b843c749SSergey Zigachev struct { 444*b843c749SSergey Zigachev uint8_t ACK :1; 445*b843c749SSergey Zigachev uint8_t NO_ACK :1; 446*b843c749SSergey Zigachev uint8_t EDID_CHECKSUM_WRITE:1; 447*b843c749SSergey Zigachev uint8_t RESERVED :5; 448*b843c749SSergey Zigachev } bits; 449*b843c749SSergey Zigachev uint8_t raw; 450*b843c749SSergey Zigachev }; 451*b843c749SSergey Zigachev 452*b843c749SSergey Zigachev union phy_test_pattern { 453*b843c749SSergey Zigachev struct { 454*b843c749SSergey Zigachev /* DpcdPhyTestPatterns. This field is 2 bits for DP1.1 455*b843c749SSergey Zigachev * and 3 bits for DP1.2. 456*b843c749SSergey Zigachev */ 457*b843c749SSergey Zigachev uint8_t PATTERN :3; 458*b843c749SSergey Zigachev /* BY speci, bit7:2 is 0 for DP1.1. */ 459*b843c749SSergey Zigachev uint8_t RESERVED :5; 460*b843c749SSergey Zigachev } bits; 461*b843c749SSergey Zigachev uint8_t raw; 462*b843c749SSergey Zigachev }; 463*b843c749SSergey Zigachev 464*b843c749SSergey Zigachev /* States of Compliance Test Specification (CTS DP1.2). */ 465*b843c749SSergey Zigachev union compliance_test_state { 466*b843c749SSergey Zigachev struct { 467*b843c749SSergey Zigachev unsigned char STEREO_3D_RUNNING : 1; 468*b843c749SSergey Zigachev unsigned char RESERVED : 7; 469*b843c749SSergey Zigachev } bits; 470*b843c749SSergey Zigachev unsigned char raw; 471*b843c749SSergey Zigachev }; 472*b843c749SSergey Zigachev 473*b843c749SSergey Zigachev union link_test_pattern { 474*b843c749SSergey Zigachev struct { 475*b843c749SSergey Zigachev /* dpcd_link_test_patterns */ 476*b843c749SSergey Zigachev unsigned char PATTERN :2; 477*b843c749SSergey Zigachev unsigned char RESERVED:6; 478*b843c749SSergey Zigachev } bits; 479*b843c749SSergey Zigachev unsigned char raw; 480*b843c749SSergey Zigachev }; 481*b843c749SSergey Zigachev 482*b843c749SSergey Zigachev union test_misc { 483*b843c749SSergey Zigachev struct dpcd_test_misc_bits { 484*b843c749SSergey Zigachev unsigned char SYNC_CLOCK :1; 485*b843c749SSergey Zigachev /* dpcd_test_color_format */ 486*b843c749SSergey Zigachev unsigned char CLR_FORMAT :2; 487*b843c749SSergey Zigachev /* dpcd_test_dyn_range */ 488*b843c749SSergey Zigachev unsigned char DYN_RANGE :1; 489*b843c749SSergey Zigachev unsigned char YCBCR :1; 490*b843c749SSergey Zigachev /* dpcd_test_bit_depth */ 491*b843c749SSergey Zigachev unsigned char BPC :3; 492*b843c749SSergey Zigachev } bits; 493*b843c749SSergey Zigachev unsigned char raw; 494*b843c749SSergey Zigachev }; 495*b843c749SSergey Zigachev 496*b843c749SSergey Zigachev #endif /* DC_DP_TYPES_H */ 497