1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 /* 24 * dc_helper.c 25 * 26 * Created on: Aug 30, 2016 27 * Author: agrodzov 28 */ 29 #include "dm_services.h" 30 #include <stdarg.h> 31 32 uint32_t generic_reg_update_ex(const struct dc_context *ctx, 33 uint32_t addr, uint32_t reg_val, int n, 34 uint8_t shift1, uint32_t mask1, uint32_t field_value1, 35 ...) 36 { 37 uint32_t shift, mask, field_value; 38 int i = 1; 39 40 va_list ap; 41 va_start(ap, field_value1); 42 43 reg_val = set_reg_field_value_ex(reg_val, field_value1, mask1, shift1); 44 45 while (i < n) { 46 shift = va_arg(ap, uint32_t); 47 mask = va_arg(ap, uint32_t); 48 field_value = va_arg(ap, uint32_t); 49 50 reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift); 51 i++; 52 } 53 54 dm_write_reg(ctx, addr, reg_val); 55 va_end(ap); 56 57 return reg_val; 58 } 59 60 uint32_t generic_reg_get(const struct dc_context *ctx, uint32_t addr, 61 uint8_t shift, uint32_t mask, uint32_t *field_value); 62 uint32_t generic_reg_get(const struct dc_context *ctx, uint32_t addr, 63 uint8_t shift, uint32_t mask, uint32_t *field_value) 64 { 65 uint32_t reg_val = dm_read_reg(ctx, addr); 66 *field_value = get_reg_field_value_ex(reg_val, mask, shift); 67 return reg_val; 68 } 69 70 uint32_t generic_reg_get2(const struct dc_context *ctx, uint32_t addr, 71 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 72 uint8_t shift2, uint32_t mask2, uint32_t *field_value2); 73 uint32_t generic_reg_get2(const struct dc_context *ctx, uint32_t addr, 74 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 75 uint8_t shift2, uint32_t mask2, uint32_t *field_value2) 76 { 77 uint32_t reg_val = dm_read_reg(ctx, addr); 78 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); 79 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); 80 return reg_val; 81 } 82 83 uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr, 84 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 85 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, 86 uint8_t shift3, uint32_t mask3, uint32_t *field_value3); 87 uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr, 88 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 89 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, 90 uint8_t shift3, uint32_t mask3, uint32_t *field_value3) 91 { 92 uint32_t reg_val = dm_read_reg(ctx, addr); 93 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); 94 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); 95 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); 96 return reg_val; 97 } 98 99 uint32_t generic_reg_get4(const struct dc_context *ctx, uint32_t addr, 100 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 101 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, 102 uint8_t shift3, uint32_t mask3, uint32_t *field_value3, 103 uint8_t shift4, uint32_t mask4, uint32_t *field_value4); 104 uint32_t generic_reg_get4(const struct dc_context *ctx, uint32_t addr, 105 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 106 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, 107 uint8_t shift3, uint32_t mask3, uint32_t *field_value3, 108 uint8_t shift4, uint32_t mask4, uint32_t *field_value4) 109 { 110 uint32_t reg_val = dm_read_reg(ctx, addr); 111 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); 112 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); 113 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); 114 *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4); 115 return reg_val; 116 } 117 118 uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr, 119 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 120 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, 121 uint8_t shift3, uint32_t mask3, uint32_t *field_value3, 122 uint8_t shift4, uint32_t mask4, uint32_t *field_value4, 123 uint8_t shift5, uint32_t mask5, uint32_t *field_value5); 124 uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr, 125 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 126 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, 127 uint8_t shift3, uint32_t mask3, uint32_t *field_value3, 128 uint8_t shift4, uint32_t mask4, uint32_t *field_value4, 129 uint8_t shift5, uint32_t mask5, uint32_t *field_value5) 130 { 131 uint32_t reg_val = dm_read_reg(ctx, addr); 132 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); 133 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); 134 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); 135 *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4); 136 *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5); 137 return reg_val; 138 } 139 140 uint32_t generic_reg_get6(const struct dc_context *ctx, uint32_t addr, 141 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 142 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, 143 uint8_t shift3, uint32_t mask3, uint32_t *field_value3, 144 uint8_t shift4, uint32_t mask4, uint32_t *field_value4, 145 uint8_t shift5, uint32_t mask5, uint32_t *field_value5, 146 uint8_t shift6, uint32_t mask6, uint32_t *field_value6); 147 uint32_t generic_reg_get6(const struct dc_context *ctx, uint32_t addr, 148 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 149 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, 150 uint8_t shift3, uint32_t mask3, uint32_t *field_value3, 151 uint8_t shift4, uint32_t mask4, uint32_t *field_value4, 152 uint8_t shift5, uint32_t mask5, uint32_t *field_value5, 153 uint8_t shift6, uint32_t mask6, uint32_t *field_value6) 154 { 155 uint32_t reg_val = dm_read_reg(ctx, addr); 156 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); 157 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); 158 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); 159 *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4); 160 *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5); 161 *field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6); 162 return reg_val; 163 } 164 165 uint32_t generic_reg_get7(const struct dc_context *ctx, uint32_t addr, 166 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 167 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, 168 uint8_t shift3, uint32_t mask3, uint32_t *field_value3, 169 uint8_t shift4, uint32_t mask4, uint32_t *field_value4, 170 uint8_t shift5, uint32_t mask5, uint32_t *field_value5, 171 uint8_t shift6, uint32_t mask6, uint32_t *field_value6, 172 uint8_t shift7, uint32_t mask7, uint32_t *field_value7); 173 uint32_t generic_reg_get7(const struct dc_context *ctx, uint32_t addr, 174 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 175 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, 176 uint8_t shift3, uint32_t mask3, uint32_t *field_value3, 177 uint8_t shift4, uint32_t mask4, uint32_t *field_value4, 178 uint8_t shift5, uint32_t mask5, uint32_t *field_value5, 179 uint8_t shift6, uint32_t mask6, uint32_t *field_value6, 180 uint8_t shift7, uint32_t mask7, uint32_t *field_value7) 181 { 182 uint32_t reg_val = dm_read_reg(ctx, addr); 183 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); 184 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); 185 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); 186 *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4); 187 *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5); 188 *field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6); 189 *field_value7 = get_reg_field_value_ex(reg_val, mask7, shift7); 190 return reg_val; 191 } 192 193 uint32_t generic_reg_get8(const struct dc_context *ctx, uint32_t addr, 194 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 195 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, 196 uint8_t shift3, uint32_t mask3, uint32_t *field_value3, 197 uint8_t shift4, uint32_t mask4, uint32_t *field_value4, 198 uint8_t shift5, uint32_t mask5, uint32_t *field_value5, 199 uint8_t shift6, uint32_t mask6, uint32_t *field_value6, 200 uint8_t shift7, uint32_t mask7, uint32_t *field_value7, 201 uint8_t shift8, uint32_t mask8, uint32_t *field_value8); 202 uint32_t generic_reg_get8(const struct dc_context *ctx, uint32_t addr, 203 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 204 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, 205 uint8_t shift3, uint32_t mask3, uint32_t *field_value3, 206 uint8_t shift4, uint32_t mask4, uint32_t *field_value4, 207 uint8_t shift5, uint32_t mask5, uint32_t *field_value5, 208 uint8_t shift6, uint32_t mask6, uint32_t *field_value6, 209 uint8_t shift7, uint32_t mask7, uint32_t *field_value7, 210 uint8_t shift8, uint32_t mask8, uint32_t *field_value8) 211 { 212 uint32_t reg_val = dm_read_reg(ctx, addr); 213 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); 214 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); 215 *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); 216 *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4); 217 *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5); 218 *field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6); 219 *field_value7 = get_reg_field_value_ex(reg_val, mask7, shift7); 220 *field_value8 = get_reg_field_value_ex(reg_val, mask8, shift8); 221 return reg_val; 222 } 223 /* note: va version of this is pretty bad idea, since there is a output parameter pass by pointer 224 * compiler won't be able to check for size match and is prone to stack corruption type of bugs 225 226 uint32_t generic_reg_get(const struct dc_context *ctx, 227 uint32_t addr, int n, ...) 228 { 229 uint32_t shift, mask; 230 uint32_t *field_value; 231 uint32_t reg_val; 232 int i = 0; 233 234 reg_val = dm_read_reg(ctx, addr); 235 236 va_list ap; 237 va_start(ap, n); 238 239 while (i < n) { 240 shift = va_arg(ap, uint32_t); 241 mask = va_arg(ap, uint32_t); 242 field_value = va_arg(ap, uint32_t *); 243 244 *field_value = get_reg_field_value_ex(reg_val, mask, shift); 245 i++; 246 } 247 248 va_end(ap); 249 250 return reg_val; 251 } 252 */ 253 254 uint32_t generic_reg_wait(const struct dc_context *ctx, 255 uint32_t addr, uint32_t shift, uint32_t mask, uint32_t condition_value, 256 unsigned int delay_between_poll_us, unsigned int time_out_num_tries, 257 const char *func_name, int line) 258 { 259 uint32_t field_value; 260 uint32_t reg_val = 0; 261 int i; 262 263 /* something is terribly wrong if time out is > 200ms. (5Hz) */ 264 ASSERT(delay_between_poll_us * time_out_num_tries <= 200000); 265 266 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { 267 /* 35 seconds */ 268 delay_between_poll_us = 35000; 269 time_out_num_tries = 1000; 270 } 271 272 for (i = 0; i <= time_out_num_tries; i++) { 273 if (i) { 274 if (delay_between_poll_us >= 1000) 275 msleep(delay_between_poll_us/1000); 276 else if (delay_between_poll_us > 0) 277 udelay(delay_between_poll_us); 278 } 279 280 reg_val = dm_read_reg(ctx, addr); 281 282 field_value = get_reg_field_value_ex(reg_val, mask, shift); 283 284 if (field_value == condition_value) { 285 if (i * delay_between_poll_us > 1000) 286 dm_output_to_console("REG_WAIT taking a while: %dms in %s line:%d\n", 287 delay_between_poll_us * i / 1000, 288 func_name, line); 289 return reg_val; 290 } 291 } 292 293 dm_error("REG_WAIT timeout %dus * %d tries - %s line:%d\n", 294 delay_between_poll_us, time_out_num_tries, 295 func_name, line); 296 297 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 298 BREAK_TO_DEBUGGER(); 299 300 return reg_val; 301 } 302 303 void generic_write_indirect_reg(const struct dc_context *ctx, 304 uint32_t addr_index, uint32_t addr_data, 305 uint32_t index, uint32_t data); 306 void generic_write_indirect_reg(const struct dc_context *ctx, 307 uint32_t addr_index, uint32_t addr_data, 308 uint32_t index, uint32_t data) 309 { 310 dm_write_reg(ctx, addr_index, index); 311 dm_write_reg(ctx, addr_data, data); 312 } 313 314 uint32_t generic_read_indirect_reg(const struct dc_context *ctx, 315 uint32_t addr_index, uint32_t addr_data, 316 uint32_t index); 317 uint32_t generic_read_indirect_reg(const struct dc_context *ctx, 318 uint32_t addr_index, uint32_t addr_data, 319 uint32_t index) 320 { 321 uint32_t value = 0; 322 323 dm_write_reg(ctx, addr_index, index); 324 value = dm_read_reg(ctx, addr_data); 325 326 return value; 327 } 328 329 uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx, 330 uint32_t addr_index, uint32_t addr_data, 331 uint32_t index, uint32_t reg_val, int n, 332 uint8_t shift1, uint32_t mask1, uint32_t field_value1, 333 ...); 334 uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx, 335 uint32_t addr_index, uint32_t addr_data, 336 uint32_t index, uint32_t reg_val, int n, 337 uint8_t shift1, uint32_t mask1, uint32_t field_value1, 338 ...) 339 { 340 uint32_t shift, mask, field_value; 341 int i = 1; 342 343 va_list ap; 344 345 va_start(ap, field_value1); 346 347 reg_val = set_reg_field_value_ex(reg_val, field_value1, mask1, shift1); 348 349 while (i < n) { 350 shift = va_arg(ap, uint32_t); 351 mask = va_arg(ap, uint32_t); 352 field_value = va_arg(ap, uint32_t); 353 354 reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift); 355 i++; 356 } 357 358 generic_write_indirect_reg(ctx, addr_index, addr_data, index, reg_val); 359 va_end(ap); 360 361 return reg_val; 362 } 363