1*b843c749SSergey Zigachev /*
2*b843c749SSergey Zigachev * Copyright 2012-16 Advanced Micro Devices, Inc.
3*b843c749SSergey Zigachev *
4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a
5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"),
6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation
7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the
9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions:
10*b843c749SSergey Zigachev *
11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in
12*b843c749SSergey Zigachev * all copies or substantial portions of the Software.
13*b843c749SSergey Zigachev *
14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE.
21*b843c749SSergey Zigachev *
22*b843c749SSergey Zigachev * Authors: AMD
23*b843c749SSergey Zigachev *
24*b843c749SSergey Zigachev */
25*b843c749SSergey Zigachev
26*b843c749SSergey Zigachev #include "dce_abm.h"
27*b843c749SSergey Zigachev #include "dm_services.h"
28*b843c749SSergey Zigachev #include "reg_helper.h"
29*b843c749SSergey Zigachev #include "fixed31_32.h"
30*b843c749SSergey Zigachev #include "dc.h"
31*b843c749SSergey Zigachev
32*b843c749SSergey Zigachev #include "atom.h"
33*b843c749SSergey Zigachev
34*b843c749SSergey Zigachev
35*b843c749SSergey Zigachev #define TO_DCE_ABM(abm)\
36*b843c749SSergey Zigachev container_of(abm, struct dce_abm, base)
37*b843c749SSergey Zigachev
38*b843c749SSergey Zigachev #define REG(reg) \
39*b843c749SSergey Zigachev (abm_dce->regs->reg)
40*b843c749SSergey Zigachev
41*b843c749SSergey Zigachev #undef FN
42*b843c749SSergey Zigachev #define FN(reg_name, field_name) \
43*b843c749SSergey Zigachev abm_dce->abm_shift->field_name, abm_dce->abm_mask->field_name
44*b843c749SSergey Zigachev
45*b843c749SSergey Zigachev #define DC_LOGGER \
46*b843c749SSergey Zigachev abm->ctx->logger
47*b843c749SSergey Zigachev #define CTX \
48*b843c749SSergey Zigachev abm_dce->base.ctx
49*b843c749SSergey Zigachev
50*b843c749SSergey Zigachev #define MCP_ABM_LEVEL_SET 0x65
51*b843c749SSergey Zigachev #define MCP_ABM_PIPE_SET 0x66
52*b843c749SSergey Zigachev #define MCP_BL_SET 0x67
53*b843c749SSergey Zigachev
54*b843c749SSergey Zigachev #define MCP_DISABLE_ABM_IMMEDIATELY 255
55*b843c749SSergey Zigachev
56*b843c749SSergey Zigachev
get_current_backlight_16_bit(struct dce_abm * abm_dce)57*b843c749SSergey Zigachev static unsigned int get_current_backlight_16_bit(struct dce_abm *abm_dce)
58*b843c749SSergey Zigachev {
59*b843c749SSergey Zigachev uint64_t current_backlight;
60*b843c749SSergey Zigachev uint32_t round_result;
61*b843c749SSergey Zigachev uint32_t pwm_period_cntl, bl_period, bl_int_count;
62*b843c749SSergey Zigachev uint32_t bl_pwm_cntl, bl_pwm, fractional_duty_cycle_en;
63*b843c749SSergey Zigachev uint32_t bl_period_mask, bl_pwm_mask;
64*b843c749SSergey Zigachev
65*b843c749SSergey Zigachev pwm_period_cntl = REG_READ(BL_PWM_PERIOD_CNTL);
66*b843c749SSergey Zigachev REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period);
67*b843c749SSergey Zigachev REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count);
68*b843c749SSergey Zigachev
69*b843c749SSergey Zigachev bl_pwm_cntl = REG_READ(BL_PWM_CNTL);
70*b843c749SSergey Zigachev REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm));
71*b843c749SSergey Zigachev REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en);
72*b843c749SSergey Zigachev
73*b843c749SSergey Zigachev if (bl_int_count == 0)
74*b843c749SSergey Zigachev bl_int_count = 16;
75*b843c749SSergey Zigachev
76*b843c749SSergey Zigachev bl_period_mask = (1 << bl_int_count) - 1;
77*b843c749SSergey Zigachev bl_period &= bl_period_mask;
78*b843c749SSergey Zigachev
79*b843c749SSergey Zigachev bl_pwm_mask = bl_period_mask << (16 - bl_int_count);
80*b843c749SSergey Zigachev
81*b843c749SSergey Zigachev if (fractional_duty_cycle_en == 0)
82*b843c749SSergey Zigachev bl_pwm &= bl_pwm_mask;
83*b843c749SSergey Zigachev else
84*b843c749SSergey Zigachev bl_pwm &= 0xFFFF;
85*b843c749SSergey Zigachev
86*b843c749SSergey Zigachev current_backlight = bl_pwm << (1 + bl_int_count);
87*b843c749SSergey Zigachev
88*b843c749SSergey Zigachev if (bl_period == 0)
89*b843c749SSergey Zigachev bl_period = 0xFFFF;
90*b843c749SSergey Zigachev
91*b843c749SSergey Zigachev current_backlight = div_u64(current_backlight, bl_period);
92*b843c749SSergey Zigachev current_backlight = (current_backlight + 1) >> 1;
93*b843c749SSergey Zigachev
94*b843c749SSergey Zigachev current_backlight = (uint64_t)(current_backlight) * bl_period;
95*b843c749SSergey Zigachev
96*b843c749SSergey Zigachev round_result = (uint32_t)(current_backlight & 0xFFFFFFFF);
97*b843c749SSergey Zigachev
98*b843c749SSergey Zigachev round_result = (round_result >> (bl_int_count-1)) & 1;
99*b843c749SSergey Zigachev
100*b843c749SSergey Zigachev current_backlight >>= bl_int_count;
101*b843c749SSergey Zigachev current_backlight += round_result;
102*b843c749SSergey Zigachev
103*b843c749SSergey Zigachev return (uint32_t)(current_backlight);
104*b843c749SSergey Zigachev }
105*b843c749SSergey Zigachev
driver_set_backlight_level(struct dce_abm * abm_dce,uint32_t level)106*b843c749SSergey Zigachev static void driver_set_backlight_level(struct dce_abm *abm_dce, uint32_t level)
107*b843c749SSergey Zigachev {
108*b843c749SSergey Zigachev uint32_t backlight_24bit;
109*b843c749SSergey Zigachev uint32_t backlight_17bit;
110*b843c749SSergey Zigachev uint32_t backlight_16bit;
111*b843c749SSergey Zigachev uint32_t masked_pwm_period;
112*b843c749SSergey Zigachev uint8_t rounding_bit;
113*b843c749SSergey Zigachev uint8_t bit_count;
114*b843c749SSergey Zigachev uint64_t active_duty_cycle;
115*b843c749SSergey Zigachev uint32_t pwm_period_bitcnt;
116*b843c749SSergey Zigachev
117*b843c749SSergey Zigachev /*
118*b843c749SSergey Zigachev * 1. Convert 8-bit value to 17 bit U1.16 format
119*b843c749SSergey Zigachev * (1 integer, 16 fractional bits)
120*b843c749SSergey Zigachev */
121*b843c749SSergey Zigachev
122*b843c749SSergey Zigachev /* 1.1 multiply 8 bit value by 0x10101 to get a 24 bit value,
123*b843c749SSergey Zigachev * effectively multiplying value by 256/255
124*b843c749SSergey Zigachev * eg. for a level of 0xEF, backlight_24bit = 0xEF * 0x10101 = 0xEFEFEF
125*b843c749SSergey Zigachev */
126*b843c749SSergey Zigachev backlight_24bit = level * 0x10101;
127*b843c749SSergey Zigachev
128*b843c749SSergey Zigachev /* 1.2 The upper 16 bits of the 24 bit value is the fraction, lower 8
129*b843c749SSergey Zigachev * used for rounding, take most significant bit of fraction for
130*b843c749SSergey Zigachev * rounding, e.g. for 0xEFEFEF, rounding bit is 1
131*b843c749SSergey Zigachev */
132*b843c749SSergey Zigachev rounding_bit = (backlight_24bit >> 7) & 1;
133*b843c749SSergey Zigachev
134*b843c749SSergey Zigachev /* 1.3 Add the upper 16 bits of the 24 bit value with the rounding bit
135*b843c749SSergey Zigachev * resulting in a 17 bit value e.g. 0xEFF0 = (0xEFEFEF >> 8) + 1
136*b843c749SSergey Zigachev */
137*b843c749SSergey Zigachev backlight_17bit = (backlight_24bit >> 8) + rounding_bit;
138*b843c749SSergey Zigachev
139*b843c749SSergey Zigachev /*
140*b843c749SSergey Zigachev * 2. Find 16 bit backlight active duty cycle, where 0 <= backlight
141*b843c749SSergey Zigachev * active duty cycle <= backlight period
142*b843c749SSergey Zigachev */
143*b843c749SSergey Zigachev
144*b843c749SSergey Zigachev /* 2.1 Apply bitmask for backlight period value based on value of BITCNT
145*b843c749SSergey Zigachev */
146*b843c749SSergey Zigachev REG_GET_2(BL_PWM_PERIOD_CNTL,
147*b843c749SSergey Zigachev BL_PWM_PERIOD_BITCNT, &pwm_period_bitcnt,
148*b843c749SSergey Zigachev BL_PWM_PERIOD, &masked_pwm_period);
149*b843c749SSergey Zigachev
150*b843c749SSergey Zigachev if (pwm_period_bitcnt == 0)
151*b843c749SSergey Zigachev bit_count = 16;
152*b843c749SSergey Zigachev else
153*b843c749SSergey Zigachev bit_count = pwm_period_bitcnt;
154*b843c749SSergey Zigachev
155*b843c749SSergey Zigachev /* e.g. maskedPwmPeriod = 0x24 when bitCount is 6 */
156*b843c749SSergey Zigachev masked_pwm_period = masked_pwm_period & ((1 << bit_count) - 1);
157*b843c749SSergey Zigachev
158*b843c749SSergey Zigachev /* 2.2 Calculate integer active duty cycle required upper 16 bits
159*b843c749SSergey Zigachev * contain integer component, lower 16 bits contain fractional component
160*b843c749SSergey Zigachev * of active duty cycle e.g. 0x21BDC0 = 0xEFF0 * 0x24
161*b843c749SSergey Zigachev */
162*b843c749SSergey Zigachev active_duty_cycle = backlight_17bit * masked_pwm_period;
163*b843c749SSergey Zigachev
164*b843c749SSergey Zigachev /* 2.3 Calculate 16 bit active duty cycle from integer and fractional
165*b843c749SSergey Zigachev * components shift by bitCount then mask 16 bits and add rounding bit
166*b843c749SSergey Zigachev * from MSB of fraction e.g. 0x86F7 = ((0x21BDC0 >> 6) & 0xFFF) + 0
167*b843c749SSergey Zigachev */
168*b843c749SSergey Zigachev backlight_16bit = active_duty_cycle >> bit_count;
169*b843c749SSergey Zigachev backlight_16bit &= 0xFFFF;
170*b843c749SSergey Zigachev backlight_16bit += (active_duty_cycle >> (bit_count - 1)) & 0x1;
171*b843c749SSergey Zigachev
172*b843c749SSergey Zigachev /*
173*b843c749SSergey Zigachev * 3. Program register with updated value
174*b843c749SSergey Zigachev */
175*b843c749SSergey Zigachev
176*b843c749SSergey Zigachev /* 3.1 Lock group 2 backlight registers */
177*b843c749SSergey Zigachev
178*b843c749SSergey Zigachev REG_UPDATE_2(BL_PWM_GRP1_REG_LOCK,
179*b843c749SSergey Zigachev BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, 1,
180*b843c749SSergey Zigachev BL_PWM_GRP1_REG_LOCK, 1);
181*b843c749SSergey Zigachev
182*b843c749SSergey Zigachev // 3.2 Write new active duty cycle
183*b843c749SSergey Zigachev REG_UPDATE(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, backlight_16bit);
184*b843c749SSergey Zigachev
185*b843c749SSergey Zigachev /* 3.3 Unlock group 2 backlight registers */
186*b843c749SSergey Zigachev REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
187*b843c749SSergey Zigachev BL_PWM_GRP1_REG_LOCK, 0);
188*b843c749SSergey Zigachev
189*b843c749SSergey Zigachev /* 5.4.4 Wait for pending bit to be cleared */
190*b843c749SSergey Zigachev REG_WAIT(BL_PWM_GRP1_REG_LOCK,
191*b843c749SSergey Zigachev BL_PWM_GRP1_REG_UPDATE_PENDING, 0,
192*b843c749SSergey Zigachev 1, 10000);
193*b843c749SSergey Zigachev }
194*b843c749SSergey Zigachev
dmcu_set_backlight_level(struct dce_abm * abm_dce,uint32_t level,uint32_t frame_ramp,uint32_t controller_id)195*b843c749SSergey Zigachev static void dmcu_set_backlight_level(
196*b843c749SSergey Zigachev struct dce_abm *abm_dce,
197*b843c749SSergey Zigachev uint32_t level,
198*b843c749SSergey Zigachev uint32_t frame_ramp,
199*b843c749SSergey Zigachev uint32_t controller_id)
200*b843c749SSergey Zigachev {
201*b843c749SSergey Zigachev unsigned int backlight_16_bit = (level * 0x10101) >> 8;
202*b843c749SSergey Zigachev unsigned int backlight_17_bit = backlight_16_bit +
203*b843c749SSergey Zigachev (((backlight_16_bit & 0x80) >> 7) & 1);
204*b843c749SSergey Zigachev uint32_t rampingBoundary = 0xFFFF;
205*b843c749SSergey Zigachev uint32_t s2;
206*b843c749SSergey Zigachev
207*b843c749SSergey Zigachev /* set ramping boundary */
208*b843c749SSergey Zigachev REG_WRITE(MASTER_COMM_DATA_REG1, rampingBoundary);
209*b843c749SSergey Zigachev
210*b843c749SSergey Zigachev /* setDMCUParam_Pipe */
211*b843c749SSergey Zigachev REG_UPDATE_2(MASTER_COMM_CMD_REG,
212*b843c749SSergey Zigachev MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_PIPE_SET,
213*b843c749SSergey Zigachev MASTER_COMM_CMD_REG_BYTE1, controller_id);
214*b843c749SSergey Zigachev
215*b843c749SSergey Zigachev /* notifyDMCUMsg */
216*b843c749SSergey Zigachev REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
217*b843c749SSergey Zigachev
218*b843c749SSergey Zigachev /* waitDMCUReadyForCmd */
219*b843c749SSergey Zigachev REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT,
220*b843c749SSergey Zigachev 0, 1, 80000);
221*b843c749SSergey Zigachev
222*b843c749SSergey Zigachev /* setDMCUParam_BL */
223*b843c749SSergey Zigachev REG_UPDATE(BL1_PWM_USER_LEVEL, BL1_PWM_USER_LEVEL, backlight_17_bit);
224*b843c749SSergey Zigachev
225*b843c749SSergey Zigachev /* write ramp */
226*b843c749SSergey Zigachev if (controller_id == 0)
227*b843c749SSergey Zigachev frame_ramp = 0;
228*b843c749SSergey Zigachev REG_WRITE(MASTER_COMM_DATA_REG1, frame_ramp);
229*b843c749SSergey Zigachev
230*b843c749SSergey Zigachev /* setDMCUParam_Cmd */
231*b843c749SSergey Zigachev REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET);
232*b843c749SSergey Zigachev
233*b843c749SSergey Zigachev /* notifyDMCUMsg */
234*b843c749SSergey Zigachev REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
235*b843c749SSergey Zigachev
236*b843c749SSergey Zigachev /* UpdateRequestedBacklightLevel */
237*b843c749SSergey Zigachev s2 = REG_READ(BIOS_SCRATCH_2);
238*b843c749SSergey Zigachev
239*b843c749SSergey Zigachev s2 &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
240*b843c749SSergey Zigachev level &= (ATOM_S2_CURRENT_BL_LEVEL_MASK >>
241*b843c749SSergey Zigachev ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
242*b843c749SSergey Zigachev s2 |= (level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
243*b843c749SSergey Zigachev
244*b843c749SSergey Zigachev REG_WRITE(BIOS_SCRATCH_2, s2);
245*b843c749SSergey Zigachev
246*b843c749SSergey Zigachev /* waitDMCUReadyForCmd */
247*b843c749SSergey Zigachev REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT,
248*b843c749SSergey Zigachev 0, 1, 80000);
249*b843c749SSergey Zigachev }
250*b843c749SSergey Zigachev
dce_abm_init(struct abm * abm)251*b843c749SSergey Zigachev static void dce_abm_init(struct abm *abm)
252*b843c749SSergey Zigachev {
253*b843c749SSergey Zigachev struct dce_abm *abm_dce = TO_DCE_ABM(abm);
254*b843c749SSergey Zigachev unsigned int backlight = get_current_backlight_16_bit(abm_dce);
255*b843c749SSergey Zigachev
256*b843c749SSergey Zigachev REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x103);
257*b843c749SSergey Zigachev REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101);
258*b843c749SSergey Zigachev REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x103);
259*b843c749SSergey Zigachev REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x101);
260*b843c749SSergey Zigachev REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x101);
261*b843c749SSergey Zigachev
262*b843c749SSergey Zigachev REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0,
263*b843c749SSergey Zigachev ABM1_HG_NUM_OF_BINS_SEL, 0,
264*b843c749SSergey Zigachev ABM1_HG_VMAX_SEL, 1,
265*b843c749SSergey Zigachev ABM1_HG_BIN_BITWIDTH_SIZE_SEL, 0);
266*b843c749SSergey Zigachev
267*b843c749SSergey Zigachev REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0,
268*b843c749SSergey Zigachev ABM1_IPCSC_COEFF_SEL_R, 2,
269*b843c749SSergey Zigachev ABM1_IPCSC_COEFF_SEL_G, 4,
270*b843c749SSergey Zigachev ABM1_IPCSC_COEFF_SEL_B, 2);
271*b843c749SSergey Zigachev
272*b843c749SSergey Zigachev REG_UPDATE(BL1_PWM_CURRENT_ABM_LEVEL,
273*b843c749SSergey Zigachev BL1_PWM_CURRENT_ABM_LEVEL, backlight);
274*b843c749SSergey Zigachev
275*b843c749SSergey Zigachev REG_UPDATE(BL1_PWM_TARGET_ABM_LEVEL,
276*b843c749SSergey Zigachev BL1_PWM_TARGET_ABM_LEVEL, backlight);
277*b843c749SSergey Zigachev
278*b843c749SSergey Zigachev REG_UPDATE(BL1_PWM_USER_LEVEL,
279*b843c749SSergey Zigachev BL1_PWM_USER_LEVEL, backlight);
280*b843c749SSergey Zigachev
281*b843c749SSergey Zigachev REG_UPDATE_2(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES,
282*b843c749SSergey Zigachev ABM1_LS_MIN_PIXEL_VALUE_THRES, 0,
283*b843c749SSergey Zigachev ABM1_LS_MAX_PIXEL_VALUE_THRES, 1000);
284*b843c749SSergey Zigachev
285*b843c749SSergey Zigachev REG_SET_3(DC_ABM1_HGLS_REG_READ_PROGRESS, 0,
286*b843c749SSergey Zigachev ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, 1,
287*b843c749SSergey Zigachev ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, 1,
288*b843c749SSergey Zigachev ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, 1);
289*b843c749SSergey Zigachev }
290*b843c749SSergey Zigachev
dce_abm_get_current_backlight_8_bit(struct abm * abm)291*b843c749SSergey Zigachev static unsigned int dce_abm_get_current_backlight_8_bit(struct abm *abm)
292*b843c749SSergey Zigachev {
293*b843c749SSergey Zigachev struct dce_abm *abm_dce = TO_DCE_ABM(abm);
294*b843c749SSergey Zigachev unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL);
295*b843c749SSergey Zigachev
296*b843c749SSergey Zigachev return (backlight >> 8);
297*b843c749SSergey Zigachev }
298*b843c749SSergey Zigachev
dce_abm_set_level(struct abm * abm,uint32_t level)299*b843c749SSergey Zigachev static bool dce_abm_set_level(struct abm *abm, uint32_t level)
300*b843c749SSergey Zigachev {
301*b843c749SSergey Zigachev struct dce_abm *abm_dce = TO_DCE_ABM(abm);
302*b843c749SSergey Zigachev
303*b843c749SSergey Zigachev REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
304*b843c749SSergey Zigachev 1, 80000);
305*b843c749SSergey Zigachev
306*b843c749SSergey Zigachev /* setDMCUParam_ABMLevel */
307*b843c749SSergey Zigachev REG_UPDATE_2(MASTER_COMM_CMD_REG,
308*b843c749SSergey Zigachev MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_LEVEL_SET,
309*b843c749SSergey Zigachev MASTER_COMM_CMD_REG_BYTE2, level);
310*b843c749SSergey Zigachev
311*b843c749SSergey Zigachev /* notifyDMCUMsg */
312*b843c749SSergey Zigachev REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
313*b843c749SSergey Zigachev
314*b843c749SSergey Zigachev return true;
315*b843c749SSergey Zigachev }
316*b843c749SSergey Zigachev
dce_abm_immediate_disable(struct abm * abm)317*b843c749SSergey Zigachev static bool dce_abm_immediate_disable(struct abm *abm)
318*b843c749SSergey Zigachev {
319*b843c749SSergey Zigachev struct dce_abm *abm_dce = TO_DCE_ABM(abm);
320*b843c749SSergey Zigachev
321*b843c749SSergey Zigachev REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
322*b843c749SSergey Zigachev 1, 80000);
323*b843c749SSergey Zigachev
324*b843c749SSergey Zigachev /* setDMCUParam_ABMLevel */
325*b843c749SSergey Zigachev REG_UPDATE_2(MASTER_COMM_CMD_REG,
326*b843c749SSergey Zigachev MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_LEVEL_SET,
327*b843c749SSergey Zigachev MASTER_COMM_CMD_REG_BYTE2, MCP_DISABLE_ABM_IMMEDIATELY);
328*b843c749SSergey Zigachev
329*b843c749SSergey Zigachev /* notifyDMCUMsg */
330*b843c749SSergey Zigachev REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
331*b843c749SSergey Zigachev
332*b843c749SSergey Zigachev abm->stored_backlight_registers.BL_PWM_CNTL =
333*b843c749SSergey Zigachev REG_READ(BL_PWM_CNTL);
334*b843c749SSergey Zigachev abm->stored_backlight_registers.BL_PWM_CNTL2 =
335*b843c749SSergey Zigachev REG_READ(BL_PWM_CNTL2);
336*b843c749SSergey Zigachev abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL =
337*b843c749SSergey Zigachev REG_READ(BL_PWM_PERIOD_CNTL);
338*b843c749SSergey Zigachev
339*b843c749SSergey Zigachev REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
340*b843c749SSergey Zigachev &abm->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
341*b843c749SSergey Zigachev return true;
342*b843c749SSergey Zigachev }
343*b843c749SSergey Zigachev
dce_abm_init_backlight(struct abm * abm)344*b843c749SSergey Zigachev static bool dce_abm_init_backlight(struct abm *abm)
345*b843c749SSergey Zigachev {
346*b843c749SSergey Zigachev struct dce_abm *abm_dce = TO_DCE_ABM(abm);
347*b843c749SSergey Zigachev uint32_t value;
348*b843c749SSergey Zigachev
349*b843c749SSergey Zigachev /* It must not be 0, so we have to restore them
350*b843c749SSergey Zigachev * Bios bug w/a - period resets to zero,
351*b843c749SSergey Zigachev * restoring to cache values which is always correct
352*b843c749SSergey Zigachev */
353*b843c749SSergey Zigachev REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value);
354*b843c749SSergey Zigachev if (value == 0 || value == 1) {
355*b843c749SSergey Zigachev if (abm->stored_backlight_registers.BL_PWM_CNTL != 0) {
356*b843c749SSergey Zigachev REG_WRITE(BL_PWM_CNTL,
357*b843c749SSergey Zigachev abm->stored_backlight_registers.BL_PWM_CNTL);
358*b843c749SSergey Zigachev REG_WRITE(BL_PWM_CNTL2,
359*b843c749SSergey Zigachev abm->stored_backlight_registers.BL_PWM_CNTL2);
360*b843c749SSergey Zigachev REG_WRITE(BL_PWM_PERIOD_CNTL,
361*b843c749SSergey Zigachev abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL);
362*b843c749SSergey Zigachev REG_UPDATE(LVTMA_PWRSEQ_REF_DIV,
363*b843c749SSergey Zigachev BL_PWM_REF_DIV,
364*b843c749SSergey Zigachev abm->stored_backlight_registers.
365*b843c749SSergey Zigachev LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
366*b843c749SSergey Zigachev } else {
367*b843c749SSergey Zigachev /* TODO: Note: This should not really happen since VBIOS
368*b843c749SSergey Zigachev * should have initialized PWM registers on boot.
369*b843c749SSergey Zigachev */
370*b843c749SSergey Zigachev REG_WRITE(BL_PWM_CNTL, 0xC000FA00);
371*b843c749SSergey Zigachev REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0);
372*b843c749SSergey Zigachev }
373*b843c749SSergey Zigachev } else {
374*b843c749SSergey Zigachev abm->stored_backlight_registers.BL_PWM_CNTL =
375*b843c749SSergey Zigachev REG_READ(BL_PWM_CNTL);
376*b843c749SSergey Zigachev abm->stored_backlight_registers.BL_PWM_CNTL2 =
377*b843c749SSergey Zigachev REG_READ(BL_PWM_CNTL2);
378*b843c749SSergey Zigachev abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL =
379*b843c749SSergey Zigachev REG_READ(BL_PWM_PERIOD_CNTL);
380*b843c749SSergey Zigachev
381*b843c749SSergey Zigachev REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
382*b843c749SSergey Zigachev &abm->stored_backlight_registers.
383*b843c749SSergey Zigachev LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
384*b843c749SSergey Zigachev }
385*b843c749SSergey Zigachev
386*b843c749SSergey Zigachev /* Have driver take backlight control
387*b843c749SSergey Zigachev * TakeBacklightControl(true)
388*b843c749SSergey Zigachev */
389*b843c749SSergey Zigachev value = REG_READ(BIOS_SCRATCH_2);
390*b843c749SSergey Zigachev value |= ATOM_S2_VRI_BRIGHT_ENABLE;
391*b843c749SSergey Zigachev REG_WRITE(BIOS_SCRATCH_2, value);
392*b843c749SSergey Zigachev
393*b843c749SSergey Zigachev /* Enable the backlight output */
394*b843c749SSergey Zigachev REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1);
395*b843c749SSergey Zigachev
396*b843c749SSergey Zigachev /* Unlock group 2 backlight registers */
397*b843c749SSergey Zigachev REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
398*b843c749SSergey Zigachev BL_PWM_GRP1_REG_LOCK, 0);
399*b843c749SSergey Zigachev
400*b843c749SSergey Zigachev return true;
401*b843c749SSergey Zigachev }
402*b843c749SSergey Zigachev
dce_abm_set_backlight_level(struct abm * abm,unsigned int backlight_level,unsigned int frame_ramp,unsigned int controller_id,bool use_smooth_brightness)403*b843c749SSergey Zigachev static bool dce_abm_set_backlight_level(
404*b843c749SSergey Zigachev struct abm *abm,
405*b843c749SSergey Zigachev unsigned int backlight_level,
406*b843c749SSergey Zigachev unsigned int frame_ramp,
407*b843c749SSergey Zigachev unsigned int controller_id,
408*b843c749SSergey Zigachev bool use_smooth_brightness)
409*b843c749SSergey Zigachev {
410*b843c749SSergey Zigachev struct dce_abm *abm_dce = TO_DCE_ABM(abm);
411*b843c749SSergey Zigachev
412*b843c749SSergey Zigachev DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
413*b843c749SSergey Zigachev backlight_level, backlight_level);
414*b843c749SSergey Zigachev
415*b843c749SSergey Zigachev /* If DMCU is in reset state, DMCU is uninitialized */
416*b843c749SSergey Zigachev if (use_smooth_brightness)
417*b843c749SSergey Zigachev dmcu_set_backlight_level(abm_dce,
418*b843c749SSergey Zigachev backlight_level,
419*b843c749SSergey Zigachev frame_ramp,
420*b843c749SSergey Zigachev controller_id);
421*b843c749SSergey Zigachev else
422*b843c749SSergey Zigachev driver_set_backlight_level(abm_dce, backlight_level);
423*b843c749SSergey Zigachev
424*b843c749SSergey Zigachev return true;
425*b843c749SSergey Zigachev }
426*b843c749SSergey Zigachev
427*b843c749SSergey Zigachev static const struct abm_funcs dce_funcs = {
428*b843c749SSergey Zigachev .abm_init = dce_abm_init,
429*b843c749SSergey Zigachev .set_abm_level = dce_abm_set_level,
430*b843c749SSergey Zigachev .init_backlight = dce_abm_init_backlight,
431*b843c749SSergey Zigachev .set_backlight_level = dce_abm_set_backlight_level,
432*b843c749SSergey Zigachev .get_current_backlight_8_bit = dce_abm_get_current_backlight_8_bit,
433*b843c749SSergey Zigachev .set_abm_immediate_disable = dce_abm_immediate_disable
434*b843c749SSergey Zigachev };
435*b843c749SSergey Zigachev
dce_abm_construct(struct dce_abm * abm_dce,struct dc_context * ctx,const struct dce_abm_registers * regs,const struct dce_abm_shift * abm_shift,const struct dce_abm_mask * abm_mask)436*b843c749SSergey Zigachev static void dce_abm_construct(
437*b843c749SSergey Zigachev struct dce_abm *abm_dce,
438*b843c749SSergey Zigachev struct dc_context *ctx,
439*b843c749SSergey Zigachev const struct dce_abm_registers *regs,
440*b843c749SSergey Zigachev const struct dce_abm_shift *abm_shift,
441*b843c749SSergey Zigachev const struct dce_abm_mask *abm_mask)
442*b843c749SSergey Zigachev {
443*b843c749SSergey Zigachev struct abm *base = &abm_dce->base;
444*b843c749SSergey Zigachev
445*b843c749SSergey Zigachev base->ctx = ctx;
446*b843c749SSergey Zigachev base->funcs = &dce_funcs;
447*b843c749SSergey Zigachev base->stored_backlight_registers.BL_PWM_CNTL = 0;
448*b843c749SSergey Zigachev base->stored_backlight_registers.BL_PWM_CNTL2 = 0;
449*b843c749SSergey Zigachev base->stored_backlight_registers.BL_PWM_PERIOD_CNTL = 0;
450*b843c749SSergey Zigachev base->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV = 0;
451*b843c749SSergey Zigachev
452*b843c749SSergey Zigachev abm_dce->regs = regs;
453*b843c749SSergey Zigachev abm_dce->abm_shift = abm_shift;
454*b843c749SSergey Zigachev abm_dce->abm_mask = abm_mask;
455*b843c749SSergey Zigachev }
456*b843c749SSergey Zigachev
dce_abm_create(struct dc_context * ctx,const struct dce_abm_registers * regs,const struct dce_abm_shift * abm_shift,const struct dce_abm_mask * abm_mask)457*b843c749SSergey Zigachev struct abm *dce_abm_create(
458*b843c749SSergey Zigachev struct dc_context *ctx,
459*b843c749SSergey Zigachev const struct dce_abm_registers *regs,
460*b843c749SSergey Zigachev const struct dce_abm_shift *abm_shift,
461*b843c749SSergey Zigachev const struct dce_abm_mask *abm_mask)
462*b843c749SSergey Zigachev {
463*b843c749SSergey Zigachev struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_KERNEL);
464*b843c749SSergey Zigachev
465*b843c749SSergey Zigachev if (abm_dce == NULL) {
466*b843c749SSergey Zigachev BREAK_TO_DEBUGGER();
467*b843c749SSergey Zigachev return NULL;
468*b843c749SSergey Zigachev }
469*b843c749SSergey Zigachev
470*b843c749SSergey Zigachev dce_abm_construct(abm_dce, ctx, regs, abm_shift, abm_mask);
471*b843c749SSergey Zigachev
472*b843c749SSergey Zigachev abm_dce->base.funcs = &dce_funcs;
473*b843c749SSergey Zigachev
474*b843c749SSergey Zigachev return &abm_dce->base;
475*b843c749SSergey Zigachev }
476*b843c749SSergey Zigachev
dce_abm_destroy(struct abm ** abm)477*b843c749SSergey Zigachev void dce_abm_destroy(struct abm **abm)
478*b843c749SSergey Zigachev {
479*b843c749SSergey Zigachev struct dce_abm *abm_dce = TO_DCE_ABM(*abm);
480*b843c749SSergey Zigachev
481*b843c749SSergey Zigachev abm_dce->base.funcs->set_abm_immediate_disable(*abm);
482*b843c749SSergey Zigachev
483*b843c749SSergey Zigachev kfree(abm_dce);
484*b843c749SSergey Zigachev *abm = NULL;
485*b843c749SSergey Zigachev }
486