1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_AUX_ENGINE_DCE110_H__ 27 #define __DAL_AUX_ENGINE_DCE110_H__ 28 #include "aux_engine.h" 29 30 #define AUX_COMMON_REG_LIST(id)\ 31 SRI(AUX_CONTROL, DP_AUX, id), \ 32 SRI(AUX_ARB_CONTROL, DP_AUX, id), \ 33 SRI(AUX_SW_DATA, DP_AUX, id), \ 34 SRI(AUX_SW_CONTROL, DP_AUX, id), \ 35 SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \ 36 SRI(AUX_SW_STATUS, DP_AUX, id), \ 37 SR(AUXN_IMPCAL), \ 38 SR(AUXP_IMPCAL) 39 40 struct dce110_aux_registers { 41 uint32_t AUX_CONTROL; 42 uint32_t AUX_ARB_CONTROL; 43 uint32_t AUX_SW_DATA; 44 uint32_t AUX_SW_CONTROL; 45 uint32_t AUX_INTERRUPT_CONTROL; 46 uint32_t AUX_SW_STATUS; 47 uint32_t AUXN_IMPCAL; 48 uint32_t AUXP_IMPCAL; 49 50 uint32_t AUX_RESET_MASK; 51 }; 52 53 enum { /* This is the timeout as defined in DP 1.2a, 54 * 2.3.4 "Detailed uPacket TX AUX CH State Description". 55 */ 56 AUX_TIMEOUT_PERIOD = 400, 57 58 /* Ideally, the SW timeout should be just above 550usec 59 * which is programmed in HW. 60 * But the SW timeout of 600usec is not reliable, 61 * because on some systems, delay_in_microseconds() 62 * returns faster than it should. 63 * EPR #379763: by trial-and-error on different systems, 64 * 700usec is the minimum reliable SW timeout for polling 65 * the AUX_SW_STATUS.AUX_SW_DONE bit. 66 * This timeout expires *only* when there is 67 * AUX Error or AUX Timeout conditions - not during normal operation. 68 * During normal operation, AUX_SW_STATUS.AUX_SW_DONE bit is set 69 * at most within ~240usec. That means, 70 * increasing this timeout will not affect normal operation, 71 * and we'll timeout after 72 * SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD = 2400usec. 73 * This timeout is especially important for 74 * converters, resume from S3, and CTS. 75 */ 76 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER = 6 77 }; 78 struct aux_engine_dce110 { 79 struct aux_engine base; 80 const struct dce110_aux_registers *regs; 81 struct { 82 uint32_t aux_control; 83 uint32_t aux_arb_control; 84 uint32_t aux_sw_data; 85 uint32_t aux_sw_control; 86 uint32_t aux_interrupt_control; 87 uint32_t aux_sw_status; 88 } addr; 89 uint32_t timeout_period; 90 }; 91 92 struct aux_engine_dce110_init_data { 93 uint32_t engine_id; 94 uint32_t timeout_period; 95 struct dc_context *ctx; 96 const struct dce110_aux_registers *regs; 97 }; 98 99 struct aux_engine *dce110_aux_engine_construct( 100 struct aux_engine_dce110 *aux_engine110, 101 struct dc_context *ctx, 102 uint32_t inst, 103 uint32_t timeout_period, 104 const struct dce110_aux_registers *regs); 105 106 void dce110_engine_destroy(struct aux_engine **engine); 107 108 bool dce110_aux_engine_acquire( 109 struct aux_engine *aux_engine, 110 struct ddc *ddc); 111 #endif 112